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[Armadeus-commitlog] SF.net SVN: armadeus: [764] trunk/firmware
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From: <Fa...@us...> - 2008-03-03 13:19:38
|
Revision: 764
http://armadeus.svn.sourceforge.net/armadeus/?rev=764&view=rev
Author: FabM
Date: 2008-03-03 05:19:41 -0800 (Mon, 03 Mar 2008)
Log Message:
-----------
[firmware][bus_led] Simple design to switch led,[apf_pkg] package for simulate read and write (imx), [Xtools] some tools to report synthezis problems
Added Paths:
-----------
trunk/firmware/Xtools/
trunk/firmware/Xtools/brief.py
trunk/firmware/Xtools/catcolor
trunk/firmware/apf_pkg/
trunk/firmware/apf_pkg/apf_test_pkg.vhd
trunk/firmware/bus_led/
trunk/firmware/bus_led/Makefile
trunk/firmware/bus_led/README
trunk/firmware/bus_led/TODO
trunk/firmware/bus_led/src/
trunk/firmware/bus_led/src/bus_led.ucf
trunk/firmware/bus_led/src/bus_led.vhd
trunk/firmware/bus_led/src/bus_led_top.vhd
trunk/firmware/bus_led/testbench/
trunk/firmware/bus_led/testbench/led_top_tb.vhd
Added: trunk/firmware/Xtools/brief.py
===================================================================
--- trunk/firmware/Xtools/brief.py (rev 0)
+++ trunk/firmware/Xtools/brief.py 2008-03-03 13:19:41 UTC (rev 764)
@@ -0,0 +1,54 @@
+#!/usr/bin/python
+# Just a little script to print
+# message from Xilinx synthesis
+# Fabien Marteau
+# 23/02/2008
+
+import re
+import sys
+
+
+def report(file):
+ # Key words message definition
+ error = re.compile('^error',re.I)
+ warning = re.compile('^warning',re.I)
+ info = re.compile('^info',re.I)
+ for line in file:
+ if error.match(line):
+ print error.sub('\033[01;31mERROR\033[00m',line)
+ if warning.match(line):
+ print warning.sub('\033[01;33mWARNING\033[00m',line)
+ if info.match(line):
+ print info.sub('\033[01;32mINFO\033[00m',line)
+
+print '---------------------------------------------------'
+print ' Xst messages :'
+file = open(sys.argv[1] + ".log" , 'r')
+report(file)
+file.close()
+print '---------------------------------------------------'
+print ' Ngdbuild messages :'
+file = open(sys.argv[1] + ".ngdlog",'r')
+report(file)
+file.close()
+print '---------------------------------------------------'
+print ' Map messages :'
+file = open(sys.argv[1] + ".maplog",'r')
+report(file)
+file.close()
+print '---------------------------------------------------'
+print ' Par messages :'
+file = open(sys.argv[1] + ".parlog",'r')
+report(file)
+file.close()
+print '---------------------------------------------------'
+print ' trace messages :'
+file = open(sys.argv[1] + ".tracelog",'r')
+report(file)
+file.close()
+print '---------------------------------------------------'
+print ' Bit messages :'
+file = open(sys.argv[1] + ".bitlog",'r')
+report(file)
+file.close()
+
Property changes on: trunk/firmware/Xtools/brief.py
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/firmware/Xtools/catcolor
===================================================================
--- trunk/firmware/Xtools/catcolor (rev 0)
+++ trunk/firmware/Xtools/catcolor 2008-03-03 13:19:41 UTC (rev 764)
@@ -0,0 +1,7 @@
+#!/bin/bash
+cat $1 \
+ | sed "s/^ERROR/[01\;31mERROR[00m/"\
+ | sed "s/^WARNING/[01\;33mWARNING[00m/"\
+ | sed "s/^INFO/[01\;32mINFO[0m/"
+
+
Property changes on: trunk/firmware/Xtools/catcolor
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/firmware/apf_pkg/apf_test_pkg.vhd
===================================================================
--- trunk/firmware/apf_pkg/apf_test_pkg.vhd (rev 0)
+++ trunk/firmware/apf_pkg/apf_test_pkg.vhd 2008-03-03 13:19:41 UTC (rev 764)
@@ -0,0 +1,103 @@
+
+----------------------------------------------
+-- Design Name : Test bench utils
+-- File Name : apf_test_pkg.vhw
+-- Function : Defines communication function between imx and fpga
+-- Author : Fabien Marteau
+-- Version : 1.00
+---------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+package apf_test_pkg is
+ -- read and write procedures
+ procedure imx_write(
+ address : in std_logic_vector (15 downto 0);
+ value : in std_logic_vector (15 downto 0);
+ signal gls_clk : in std_logic ;
+ signal imx_cs_n : out std_logic ;
+ signal imx_oe_n : out std_logic ;
+ signal imx_eb3_n : out std_logic ;
+ signal imx_address : out std_logic_vector (12 downto 1);
+ signal imx_data : out std_logic_vector (15 downto 0)
+);
+
+procedure imx_read(
+ address : in std_logic_vector (15 downto 0);
+ value : out std_logic_vector (15 downto 0);
+ signal gls_clk : in std_logic ;
+ signal imx_cs_n : out std_logic ;
+ signal imx_oe_n : out std_logic ;
+ signal imx_eb3_n : out std_logic ;
+ signal imx_address : out std_logic_vector (12 downto 1);
+ signal imx_data : in std_logic_vector (15 downto 0)
+ );
+
+
+end package apf_test_pkg;
+
+package body apf_test_pkg is
+
+ -- Write value from imx
+ procedure imx_write(
+ address : in std_logic_vector (15 downto 0);
+ value : in std_logic_vector (15 downto 0);
+ signal gls_clk : in std_logic ;
+ signal imx_cs_n : out std_logic ;
+ signal imx_oe_n : out std_logic ;
+ signal imx_eb3_n : out std_logic ;
+ signal imx_address : out std_logic_vector (12 downto 1);
+ signal imx_data : out std_logic_vector (15 downto 0)
+) is
+begin
+ -- Write value
+ wait until falling_edge(gls_clk);
+ wait for 4 ns;
+ imx_address <= address(12 downto 1);
+ imx_cs_n <= '0';
+ imx_eb3_n <= '0';
+ wait until falling_edge(gls_clk);
+ wait for 2500 ps;
+ imx_data <= value;
+ wait until falling_edge(gls_clk); --
+ wait until falling_edge(gls_clk); -- WSC = 2
+ wait for 1 ns;
+ imx_cs_n <= '1';
+ imx_eb3_n <= '1';
+ imx_address <= (others => 'Z');
+ imx_data <= (others => 'Z');
+end procedure imx_write;
+
+ -- Read a value from imx
+procedure imx_read(
+address : in std_logic_vector (15 downto 0);
+value : out std_logic_vector (15 downto 0);
+signal gls_clk : in std_logic ;
+signal imx_cs_n : out std_logic ;
+signal imx_oe_n : out std_logic ;
+signal imx_eb3_n : out std_logic ;
+signal imx_address : out std_logic_vector (12 downto 1);
+signal imx_data : in std_logic_vector (15 downto 0)
+ ) is
+ begin
+ -- Read value
+ wait until falling_edge(gls_clk);
+ wait for 4 ns;
+ imx_address <= address(12 downto 1);
+ imx_cs_n <= '0';
+ imx_oe_n <= '0';
+ wait until falling_edge(gls_clk);--
+ wait until falling_edge(gls_clk);-- WSC = 2
+ wait until rising_edge(gls_clk);
+ value := imx_data;
+ wait until falling_edge(gls_clk);
+ imx_cs_n <= '1';
+ imx_oe_n <= '1';
+ imx_address <= (others => 'Z');
+ wait for 20 ns;
+
+ end procedure imx_read;
+
+
+
+end package body apf_test_pkg;
Added: trunk/firmware/bus_led/Makefile
===================================================================
--- trunk/firmware/bus_led/Makefile (rev 0)
+++ trunk/firmware/bus_led/Makefile 2008-03-03 13:19:41 UTC (rev 764)
@@ -0,0 +1,235 @@
+# Makefile for VHDL synthesis and simulation
+# version 1.0
+# Fabien Marteau
+
+# project name
+PROJECT=bus_led_top
+# vhdl files
+FILES = src/bus_led.vhd src/bus_led_top.vhd
+# pin configuration
+UCF_FILE = src/bus_led.ucf
+# Synthesis constraints file
+XCF_FILE =
+# testbench
+SIMTOP = led_top_tb
+SIMFILES = ../apf_pkg/apf_test_pkg.vhd testbench/led_top_tb.vhd
+# Simu break condition
+GHDL_SIM_OPT = --assert-level=error
+#GHDL_SIM_OPT = --stop-time=500ns
+
+# FPGA options
+PART = xc3s200-4-tq144
+
+############################
+# Personnals options
+############################
+
+CAT=../Xtools/catcolor
+BRIEF=../Xtools/brief.py
+
+
+############################
+# Xilinx options
+############################
+BIN = bin
+WORK = work
+
+SYNTH = xst
+NGDBUILD = ngdbuild
+MAP = map
+PAR = par
+TRACE = trce
+BITGEN = bitgen
+
+ifdef $(XCF_FILE)
+XCF = -uc $(XCF_FILE)\n
+endif
+
+##############################
+# GHDL options
+##############################
+
+SIMDIR = simu
+SYNTHFILES = bin/bus_led_ise/netgen/synthesis
+
+GHDL_CMD = ghdl
+GHDL_FLAGS = --ieee=synopsys --warn-no-vital-generic
+#GHDL_FLAGS = --ieee=synopsys -P~/Xilinx92i/coregen/ip/xilinx/primary/com/xilinx/ip/unisim --warn-no-vital-generic
+
+VIEW_CMD = /usr/bin/gtkwave
+
+OBJS_FILES = $(patsubst %.vhd, %.o, $(notdir $(FILES)) )
+OBJS_SIMFILES = $(patsubst %.vhd, %.o, $(notdir $(SIMFILES)) )
+
+#################################
+# Synthesis with xst
+#################################
+
+messages : bit
+ $(BRIEF) $(BIN)/$(PROJECT)
+
+
+bit : $(BIN)/$(PROJECT).ncd trace
+ -$(BITGEN) -intstyle xflow -w \
+ -g DebugBitstream:No \
+ -g Binary:no \
+ -g CRC:Enable \
+ -g ConfigRate:6 \
+ -g CclkPin:PullUp \
+ -g M0Pin:PullUp \
+ -g M1Pin:PullUp \
+ -g M2Pin:PullUp \
+ -g ProgPin:PullUp \
+ -g DonePin:PullUp \
+ -g TckPin:PullUp \
+ -g TdiPin:PullUp \
+ -g TdoPin:PullUp \
+ -g TmsPin:PullUp \
+ -g UnusedPin:PullDown \
+ -g UserID:0xFFFFFFFF \
+ -g DCMShutdown:Disable \
+ -g DCIUpdateMode:AsRequired \
+ -g StartUpClk:CClk \
+ -g DONE_cycle:4 \
+ -g GTS_cycle:5 \
+ -g GWE_cycle:6 \
+ -g LCK_cycle:NoWait \
+ -g Match_cycle:Auto \
+ -g Security:None \
+ -g DonePipe:No \
+ -g DriveDone:No \
+ $(BIN)/$(PROJECT).ncd > $(BIN)/$(PROJECT).bitlog
+ $(CAT) $(BIN)/$(PROJECT).bitlog
+ cp $(BIN)/$(PROJECT).bit /tftpboot/
+
+trace: $(BIN)/$(PROJECT).ncd $(BIN)/$(PROJECT).pcf
+ -$(TRACE) -intstyle xflow -e 3 -l 3 -s 5 -xml $(BIN)/$(PROJECT) $(BIN)/$(PROJECT).ncd -o $(BIN)/$(PROJECT).twr $(BIN)/$(PROJECT).pcf > $(BIN)/$(PROJECT).tracelog
+ $(CAT) $(BIN)/$(PROJECT).tracelog
+
+$(BIN)/$(PROJECT).ncd : par
+
+par : $(BIN)/$(PROJECT)_map.ncd $(BIN)/$(PROJECT).pcf
+ - sh -c 'pid=$$$$; $(PAR) -w -intstyle xflow -ol std -t 1 $(BIN)/$(PROJECT)_map.ncd $(BIN)/$(PROJECT).ncd $(BIN)/$(PROJECT).pcf | (sed "/^PAR done/q";kill $$pid)' > $(BIN)/$(PROJECT).parlog
+ $(CAT) $(BIN)/$(PROJECT).parlog
+ - killall -9 par
+
+$(BIN)/$(PROJECT).pcf $(BIN)/$(PROJECT)_map.ncd : map
+
+map : $(BIN)/$(PROJECT).ngd
+ - sh -c 'pid=$$$$ ; $(MAP) -intstyle xflow -p $(PART) -cm area -pr b -k 4 -c 100 -o $(BIN)/$(PROJECT)_map.ncd $(BIN)/$(PROJECT).ngd $(BIN)/$(PROJECT).pcf | (sed "/^See MAP report file/q" ; kill $$pid ) ' > $(BIN)/$(PROJECT).maplog
+ $(CAT) $(BIN)/$(PROJECT).maplog
+ - killall -9 map
+
+$(BIN)/$(PROJECT).ngd : ngdbuild
+
+ngdbuild : $(BIN)/$(PROJECT).ngr $(BIN)/$(PROJECT).ngc $(BIN)/$(PROJECT).lso
+ -$(NGDBUILD) -intstyle xflow -dd _ngo -nt timestamp -p $(PART) $(BIN)/$(PROJECT).ngc $(BIN)/$(PROJECT).ngd -uc $(UCF_FILE) > $(BIN)/$(PROJECT).ngdlog
+ $(CAT) $(BIN)/$(PROJECT).ngdlog
+
+$(BIN)/$(PROJECT).ngc $(BIN)/$(PROJECT).ngr $(BIN)/$(PROJECT).lso : synthesis
+
+synthesis : $(BIN)/$(PROJECT).prj $(BIN)/$(PROJECT).xst
+ $(SYNTH) -ifn $(BIN)/$(PROJECT).xst -ofn $(BIN)/$(PROJECT).log \
+ | sed "s/^ERROR/[01\;31mERROR[00m/"\
+ | sed "s/^WARNING/[01\;33mWARNING[00m/"\
+ | sed "s/^INFO/[01\;32mINFO[0m/"
+
+$(BIN)/$(PROJECT).xst $(BIN)/$(PROJECT).prj :
+ @mkdir -p $(BIN)
+ @touch $(BIN)/$(PROJECT);
+ @for f in $(FILES); do \
+ echo vhdl $(WORK) \"$$f\" >> $(BIN)/$(PROJECT).prj;\
+ done
+ @echo work > $(BIN)/$(PROJECT).lso
+ @mkdir -p ./bin/xst/projnav.tmp
+ @echo " \
+ set -tmpdir "./bin/xst/projnav.tmp" \n\
+ set -xsthdpdir "./bin/xst" \n\
+ run \n\
+ -ifn $(BIN)/$(PROJECT).prj \n\
+ -ifmt mixed \n\
+ -ofn $(BIN)/$(PROJECT) \n\
+ -ofmt NGC \n\
+ -p $(PART) \n\
+ -top $(PROJECT) \n\
+ -opt_mode Speed \n\
+ -opt_level 1 \n\
+ $(XCF)\
+ -iuc NO \n\
+ -lso $(BIN)/$(PROJECT).lso \n\
+ -keep_hierarchy NO \n\
+ -rtlview Yes \n\
+ -glob_opt AllClockNets \n\
+ -read_cores YES \n\
+ -write_timing_constraints NO \n\
+ -cross_clock_analysis NO \n\
+ -hierarchy_separator / \n\
+ -bus_delimiter <> \n\
+ -case maintain \n\
+ -slice_utilization_ratio 100 \n\
+ -bram_utilization_ratio 100 \n\
+ -verilog2001 YES \n\
+ -fsm_extract YES -fsm_encoding Auto \n\
+ -safe_implementation No \n\
+ -fsm_style lut \n\
+ -ram_extract Yes \n\
+ -ram_style Auto \n\
+ -rom_extract Yes \n\
+ -mux_style Auto \n\
+ -decoder_extract YES \n\
+ -priority_extract YES \n\
+ -shreg_extract YES \n\
+ -shift_extract YES \n\
+ -xor_collapse YES \n\
+ -rom_style Auto \n\
+ -auto_bram_packing NO \n\
+ -mux_extract YES \n\
+ -resource_sharing YES \n\
+ -async_to_sync NO \n\
+ -mult_style auto \n\
+ -iobuf YES \n\
+ -max_fanout 500 \n\
+ -bufg 8 \n\
+ -register_duplication YES \n\
+ -register_balancing No \n\
+ -slice_packing YES \n\
+ -optimize_primitives NO \n\
+ -use_clock_enable Yes \n\
+ -use_sync_set Yes \n\
+ -use_sync_reset Yes \n\
+ -iob auto \n\
+ -equivalent_register_removal YES \n\
+ -slice_utilization_ratio_maxmargin 5\n\
+ " >> $(BIN)/$(PROJECT).xst
+
+clean : ghdl-clean
+ -rm -rf $(BIN)
+ -rm -rf _ngo
+ -rm xilinx_device_details.xml
+
+########################
+# Simulation with GHDL
+########################
+
+ghdl-compil :
+ mkdir -p simu
+ $(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=simu --work=work $(SIMFILES) $(FILES)
+ $(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=simu --work=work $(SIMTOP)
+ @mv $(SIMTOP) simu/$(SIMTOP)
+
+#TODO: make it working !
+ghdl-simsynth :
+ $(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=simu --work=work $(SYNTHFILES) $(SIMFILES)
+ $(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=simu --work=work $(SIMTOP)
+ @mv $(SIMTOP) simu/$(SIMTOP)
+
+ghdl-run :
+ @$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
+
+ghdl-view:
+ gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd
+
+ghdl-clean :
+ $(GHDL_CMD) --clean --workdir=simu
+ -rm -rf simu
+
Added: trunk/firmware/bus_led/README
===================================================================
--- trunk/firmware/bus_led/README (rev 0)
+++ trunk/firmware/bus_led/README 2008-03-03 13:19:41 UTC (rev 764)
@@ -0,0 +1,60 @@
+Simple design to blink a led from the i.mx.
+
+1) Description
+
+Led is branched on fpga P116 with this schematics :
+
+ 3.3v
+ -----
+ |
+ -----
+ | |
+ | | 330 Ohms
+ | |
+ -----
+ |
+ -------
+ \ / --/
+ \ / /--->
+ -------
+ |
+FPGA16 -----
+(P116)
+
+See ucf file in sr/bus_led.ucf for more details
+NET "LED" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
+
+To change the value from uboot use mw.w command and write
+on address 0x12000000 :
+mw.w 12000000 0001 1 # led off
+mw.w 12000000 0000 1 # led on
+
+2) Simulation
+
+The testbench is in testbench/ directory using apf_test_pkg.vhd in
+apf_pkg/ directory, to simulate it you can use ghdl using the makefile.
+compile:
+>make ghdl-compil
+
+run (the end of test finish with assert error "end of test"):
+>make ghdl-run
+
+And see graph result with gtkwave:
+>make ghdl-view
+
+3) Synthesis
+
+To synthetize the design, you need Xilinx webpack installed correctly
+and you can use make:
+>make
+This will make synthesis, place & route and bitgen, and will copy the
+bitstream in /tftpboot/ directory
+
+4) Configure
+
+To configure, you need tftpboot installed on your computer, and on
+uboot type:
+>tftpboot 08000000 bus_led_top.bit
+>fpga load 0 08000000 1ffd5
+
+
Added: trunk/firmware/bus_led/TODO
===================================================================
--- trunk/firmware/bus_led/TODO (rev 0)
+++ trunk/firmware/bus_led/TODO 2008-03-03 13:19:41 UTC (rev 764)
@@ -0,0 +1,3 @@
+
+ - correct the design with correct synchro
+ - include the linux driver
Added: trunk/firmware/bus_led/src/bus_led.ucf
===================================================================
--- trunk/firmware/bus_led/src/bus_led.ucf (rev 0)
+++ trunk/firmware/bus_led/src/bus_led.ucf 2008-03-03 13:19:41 UTC (rev 764)
@@ -0,0 +1,46 @@
+# Clock at 96MHz
+NET "clk" LOC = "P55" | IOSTANDARD = LVCMOS33 ;
+NET "clk" TNM_NET = "clk";
+TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %;
+
+NET "imx_cs_n" LOC = "P59" | IOSTANDARD = LVCMOS33;
+NET "imx_eb3_n" LOC = "P60" | IOSTANDARD = LVCMOS33;
+NET "imx_oe_n" LOC = "P63" | IOSTANDARD = LVCMOS33;
+
+NET "LED" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
+
+NET "imx_addr<1>" LOC = "P23" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<2>" LOC = "P24" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<3>" LOC = "P25" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<4>" LOC = "P26" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<5>" LOC = "P27" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<6>" LOC = "P28" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<7>" LOC = "P30" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<8>" LOC = "P31" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<9>" LOC = "P32" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<10>" LOC = "P33" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<11>" LOC = "P35" | IOSTANDARD = LVCMOS33;
+NET "imx_addr<12>" LOC = "P36" | IOSTANDARD = LVCMOS33;
+
+# IMX connection
+NET "imx_data<0>" LOC = "P1" | IOSTANDARD = LVCMOS33;
+NET "imx_data<1>" LOC = "P2" | IOSTANDARD = LVCMOS33;
+NET "imx_data<2>" LOC = "P4" | IOSTANDARD = LVCMOS33;
+NET "imx_data<3>" LOC = "P5" | IOSTANDARD = LVCMOS33;
+NET "imx_data<4>" LOC = "P6" | IOSTANDARD = LVCMOS33;
+NET "imx_data<5>" LOC = "P7" | IOSTANDARD = LVCMOS33;
+NET "imx_data<6>" LOC = "P8" | IOSTANDARD = LVCMOS33;
+NET "imx_data<7>" LOC = "P10" | IOSTANDARD = LVCMOS33;
+NET "imx_data<8>" LOC = "P11" | IOSTANDARD = LVCMOS33;
+NET "imx_data<9>" LOC = "P12" | IOSTANDARD = LVCMOS33;
+NET "imx_data<10>" LOC = "P13" | IOSTANDARD = LVCMOS33;
+NET "imx_data<11>" LOC = "P14" | IOSTANDARD = LVCMOS33;
+NET "imx_data<12>" LOC = "P15" | IOSTANDARD = LVCMOS33;
+NET "imx_data<13>" LOC = "P17" | IOSTANDARD = LVCMOS33;
+NET "imx_data<14>" LOC = "P18" | IOSTANDARD = LVCMOS33;
+NET "imx_data<15>" LOC = "P20" | IOSTANDARD = LVCMOS33;
+
+# Test (X10 on devfull) connection
+NET "imx_data0_test" LOC = "P102" | IOSTANDARD = LVCMOS33 ;
+NET "imx_addr1_test" LOC = "P97" | IOSTANDARD = LVCMOS33 ;
+
Added: trunk/firmware/bus_led/src/bus_led.vhd
===================================================================
--- trunk/firmware/bus_led/src/bus_led.vhd (rev 0)
+++ trunk/firmware/bus_led/src/bus_led.vhd 2008-03-03 13:19:41 UTC (rev 764)
@@ -0,0 +1,86 @@
+---------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau
+--
+-- Creation Date : 15/02/2008
+-- File : bus_led.vhd
+--
+-- Abstract :
+--
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+---------------------------------------------------------------------------
+Entity bus_led is
+ ---------------------------------------------------------------------------
+ port
+ (
+ -- imx signals
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_addr : in std_logic_vector(12 downto 1);
+ imx_cs_n : in std_logic ;
+ imx_eb3_n : in std_logic ;
+ imx_oe_n : in std_logic ;
+ -- Clock 96MHz
+ clk : in std_logic ;
+ LED : out std_logic ;
+ -- Reset active low
+ Rst_n : in std_logic
+ );
+end entity;
+
+
+---------------------------------------------------------------------------
+Architecture RTL of bus_led is
+ ---------------------------------------------------------------------------
+ signal Reg : std_logic_vector(15 downto 0) := (others => '0');
+
+begin
+
+ -- Led connection
+ LED <= Reg(0);
+
+ write : process (clk,Rst_n)
+ begin
+ if Rst_n = '0' then
+ Reg <= (others => '0');
+ elsif rising_edge(clk) then
+ if (imx_cs_n = '0' and imx_oe_n = '1' and imx_eb3_n = '0' ) then
+ case imx_addr is
+ when "000000000000" =>
+ -- Save imx_data value in Reg
+ Reg <= imx_data;
+ when others =>
+ Reg <= Reg;
+ end case;
+
+ end if;
+ end if;
+ end process write;
+
+ read : process (clk, Rst_n)
+ begin
+ if Rst_n = '0' then
+ imx_data <= (others => 'Z');
+ elsif falling_edge(clk) then
+ if(imx_cs_n = '0' and imx_oe_n = '0' and imx_eb3_n = '1' ) then
+ case imx_addr is
+ when "000000000000" =>
+ -- Write Reg value on imx_data bus
+ imx_data <= Reg;
+ when others =>
+ -- High impedance if others address
+ imx_data <= (others => 'Z');
+ end case;
+ else
+ -- High impedance if others address
+ imx_data <= (others => 'Z');
+ end if;
+ end if;
+ end process read;
+
+end architecture RTL;
+
Added: trunk/firmware/bus_led/src/bus_led_top.vhd
===================================================================
--- trunk/firmware/bus_led/src/bus_led_top.vhd (rev 0)
+++ trunk/firmware/bus_led/src/bus_led_top.vhd 2008-03-03 13:19:41 UTC (rev 764)
@@ -0,0 +1,76 @@
+----------------------------------------------------------------------------------
+-- Company: ARMadeus Systems
+-- Engineer: Fabien Marteau
+--
+-- Create Date:
+-- Design Name:
+-- Module Name:
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+
+
+entity bus_led_top
+is
+ port (
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_data0_test : out std_logic;
+ imx_addr1_test : out std_logic ;
+ imx_addr : in std_logic_vector(12 downto 1);
+ imx_cs_n : in std_logic ;
+ imx_eb3_n : in std_logic ;
+ imx_oe_n : in std_logic ;
+ clk : in std_logic ;
+ LED : out std_logic);
+
+end entity bus_led_top ;
+
+architecture hierarchical
+ of bus_led_top is
+ component bus_led
+ port(
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_addr : in std_logic_vector(12 downto 1);
+ imx_cs_n : in std_logic ;
+ imx_eb3_n : in std_logic ;
+ imx_oe_n : in std_logic ;
+ clk : in std_logic ;
+ LED : out std_logic ;
+ Rst_n : in std_logic);
+ end component;
+
+ -- Asynchrone reset active low
+ signal Rst_n : std_logic ;
+ begin
+
+ Rst_n <= '1';
+ imx_data0_test <= imx_data(0);
+ imx_addr1_test <= imx_addr(1);
+
+ connect_bus_led : bus_led
+ port map(
+ imx_data => imx_data,
+ imx_addr => imx_addr,
+ imx_cs_n => imx_cs_n,
+ imx_eb3_n => imx_eb3_n,
+ imx_oe_n => imx_oe_n,
+ clk => clk,
+ LED => LED,
+ Rst_n => Rst_n);
+
+end architecture ;
+
Added: trunk/firmware/bus_led/testbench/led_top_tb.vhd
===================================================================
--- trunk/firmware/bus_led/testbench/led_top_tb.vhd (rev 0)
+++ trunk/firmware/bus_led/testbench/led_top_tb.vhd 2008-03-03 13:19:41 UTC (rev 764)
@@ -0,0 +1,100 @@
+----------------------------------------------------------------------------------
+-- Company : ARMadeus Systems
+-- Author(s) : Fabien Marteau
+--
+-- Creation Date : 14/02/2008
+-- File : led_top_tb.vhd
+--
+-- Abstract : Testbench for simple design that switch a led with the imx
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+use ieee.std_logic_arith.all;
+use work.apf_test_pkg.ALL;
+
+----------------------------------------------------------------------------------
+Entity led_top_tb is
+----------------------------------------------------------------------------------
+ end entity led_top_tb;
+
+
+----------------------------------------------------------------------------------
+Architecture RTL of led_top_tb is
+ ----------------------------------------------------------------------------------
+
+ CONSTANT HALF_PERIODE : time := 5 ns; -- Half clock period
+
+ signal imx_data : std_logic_vector(15 downto 0);
+ signal imx_data0_test : std_logic ;
+ signal imx_addr1_test : std_logic ;
+ signal imx_addr : std_logic_vector (12 downto 1);
+ signal imx_cs_n : std_logic ;
+ signal imx_eb3_n : std_logic ;
+ signal imx_oe_n : std_logic ;
+ signal clk : std_logic ;
+ signal LED : std_logic ;
+ -- signal Rst_n : std_logic ;
+
+ component bus_led_top
+ port (
+ imx_data : inout std_logic_vector(15 downto 0);
+ imx_data0_test : out std_logic ;
+ imx_addr1_test : out std_logic ;
+ imx_addr : in std_logic_vector(12 downto 1);
+ imx_cs_n : in std_logic ;
+ imx_eb3_n : in std_logic ;
+ imx_oe_n : in std_logic ;
+ clk : in std_logic ;
+ LED : out std_logic );
+ end component bus_led_top;
+
+begin
+ -- Test stimulus
+ stimulus : process
+ variable value : std_logic_vector (15 downto 0);
+ begin
+ imx_oe_n <= '1';
+ imx_eb3_n <= '1';
+ imx_cs_n <= '1';
+ imx_addr <= (others => 'Z');
+ imx_data <= (others => 'Z');
+
+ wait for HALF_PERIODE*20;
+
+ for i in 0 to 600 loop
+ imx_write(x"0000",conv_std_logic_vector(i,16),clk,imx_cs_n,imx_oe_n,imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ imx_read(x"0000",value,clk,imx_cs_n,imx_oe_n,imx_eb3_n,imx_addr(12 downto 1),imx_data);
+ assert value = conv_std_logic_vector(i,16) report "error reading imx_data" severity error;
+ end loop;
+
+ assert false report "End of test" severity error;
+ end process stimulus;
+
+ -- 100MHz Clock
+ Clockp : process
+ begin
+ clk <= '1';
+ wait for HALF_PERIODE;
+ clk <= '0';
+ wait for HALF_PERIODE;
+ end process Clockp;
+
+ connect_bus_led : bus_led_top
+ port map(
+ imx_data => imx_data,
+ imx_data0_test => imx_data0_test,
+ imx_addr1_test => imx_addr1_test,
+ imx_addr => imx_addr,
+ imx_cs_n => imx_cs_n,
+ imx_eb3_n => imx_eb3_n,
+ imx_oe_n => imx_oe_n,
+ clk => clk,
+ LED => LED);
+
+-- Rst_n => Rst_n);
+
+end architecture RTL;
+
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