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[Armadeus-commitlog] SF.net SVN: armadeus: [761] trunk/firmware/BRAMTest
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From: <th...@us...> - 2008-02-10 14:50:59
|
Revision: 761
http://armadeus.svn.sourceforge.net/armadeus/?rev=761&view=rev
Author: thom25
Date: 2008-02-10 06:50:48 -0800 (Sun, 10 Feb 2008)
Log Message:
-----------
fix compilation errors
Modified Paths:
--------------
trunk/firmware/BRAMTest/BRAMTest.vhdl
trunk/firmware/BRAMTest/BRAMTest_APF.ucf
trunk/firmware/BRAMTest/BRAMtest.ise
Modified: trunk/firmware/BRAMTest/BRAMTest.vhdl
===================================================================
--- trunk/firmware/BRAMTest/BRAMTest.vhdl 2008-02-10 14:33:27 UTC (rev 760)
+++ trunk/firmware/BRAMTest/BRAMTest.vhdl 2008-02-10 14:50:48 UTC (rev 761)
@@ -1,156 +1,156 @@
-----------------------------------------------------------------------------------
--- Company: Armadeus Project
--- Engineer: michael lerjen
---
--- Create Date: 22:04:02 04/12/2006
--- Design Name:
--- Module Name:
--- Project Name:
--- Target Devices:
--- Tool versions:
--- Description:
---
--- Dependencies:
---
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-library UNISIM;
-use UNISIM.VComponents.all;
-
-entity BRAMTest_Top is -- this is the top
- Port ( DataxD : inout std_logic_vector(15 downto 0);
- AddrxDI : in std_logic_vector(9 downto 0);
- CSxBI : in std_logic;
- WRxBI : in std_logic;
- RDxBI : in std_logic;
- ClkxCI : in std_logic
- --ResetxRB : in std_logic
- );
-end BRAMTest_Top;
-
-
-
-architecture hierarchical of BRAMTest_Top is
-signal DataOutRAMxD : std_logic_vector(15 downto 0);
-signal CSBRAM : std_logic := '0';
-signal WRBRAM : std_logic := '0';
-signal CLKBRAM : std_logic := '0';
-
-begin
-
-
- -- RAMB16_S18: Virtex-II/II-Pro, Spartan-3 1k x 16 + 2 Parity bits Single-Port RAM
- -- Xilinx HDL Language Template version 6.3.1i
-
- RAMB16_S18_inst : RAMB16_S18
- generic map (
- INIT => X"00000", -- Value of output RAM registers at startup
- SRVAL => X"00000", -- Ouput value upon SSR assertion
- WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
- INIT_00 => X"1100001100000000000000000000000000000000000000000000000010010110",
- INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
- INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
- INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
- port map (
- DO => DataOutRAMxD, -- 16-bit Data Output
- DOP => open, -- 2-bit parity Output
- ADDR => AddrxDI, -- 10-bit Address Input
- CLK => CLKBRAM, -- Clock
- DI => DataxD, -- 16-bit Data Input
- DIP => "00", -- 2-bit parity Input
- EN => CSBRAM , -- RAM Enable Input
- SSR => '0', -- Synchronous Set/Reset Input
- WE => WRBRAM -- Write Enable Input
- );
-
-
- OutputEnable: process (DataOutRAMxD, CSxBI, RDxBI)
- begin
- if (CSxBI = '0' and RDxBI = '0') then -- fix me
- DataxD <= DataOutRAMxD;
- else
- DataxD <= (others => 'Z'); --
- end if;
- end process OutputEnable;
-
- CSBRAM <= not CSxBI;
- WRBRAM <= not WRxBI;
- CLKBRAM <= ClkxCI;
- -- End of RAMB16_S18_inst instantiation
-end hierarchical;
+----------------------------------------------------------------------------------
+-- Company: Armadeus Project
+-- Engineer: michael lerjen
+--
+-- Create Date: 22:04:02 04/12/2006
+-- Design Name:
+-- Module Name:
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+entity BRAMTest_Top is -- this is the top
+ Port ( DataxD : inout std_logic_vector(15 downto 0);
+ AddrxDI : in std_logic_vector(12 downto 0);
+ CSxBI : in std_logic;
+ WRxBI : in std_logic;
+ RDxBI : in std_logic;
+ ClkxCI : in std_logic
+ --ResetxRB : in std_logic
+ );
+end BRAMTest_Top;
+
+
+
+architecture hierarchical of BRAMTest_Top is
+signal DataOutRAMxD : std_logic_vector(15 downto 0);
+signal CSBRAM : std_logic := '0';
+signal WRBRAM : std_logic := '0';
+signal CLKBRAM : std_logic := '0';
+
+begin
+
+
+ -- RAMB16_S18: Virtex-II/II-Pro, Spartan-3 1k x 16 + 2 Parity bits Single-Port RAM
+ -- Xilinx HDL Language Template version 6.3.1i
+
+ RAMB16_S18_inst : RAMB16_S18
+ generic map (
+ INIT => X"00000", -- Value of output RAM registers at startup
+ SRVAL => X"00000", -- Ouput value upon SSR assertion
+ WRITE_MODE => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
+ INIT_00 => X"1100001100000000000000000000000000000000000000000000000010010110",
+ INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => DataOutRAMxD, -- 16-bit Data Output
+ DOP => open, -- 2-bit parity Output
+ ADDR => AddrxDI(9 downto 0), -- 10-bit Address Input
+ CLK => CLKBRAM, -- Clock
+ DI => DataxD, -- 16-bit Data Input
+ DIP => "00", -- 2-bit parity Input
+ EN => CSBRAM , -- RAM Enable Input
+ SSR => '0', -- Synchronous Set/Reset Input
+ WE => WRBRAM -- Write Enable Input
+ );
+
+
+ OutputEnable: process (DataOutRAMxD, CSxBI, RDxBI)
+ begin
+ if (CSxBI = '0' and RDxBI = '0') then -- fix me
+ DataxD <= DataOutRAMxD;
+ else
+ DataxD <= (others => 'Z'); --
+ end if;
+ end process OutputEnable;
+
+ CSBRAM <= not CSxBI;
+ WRBRAM <= not WRxBI;
+ CLKBRAM <= ClkxCI;
+ -- End of RAMB16_S18_inst instantiation
+end hierarchical;
Modified: trunk/firmware/BRAMTest/BRAMTest_APF.ucf
===================================================================
--- trunk/firmware/BRAMTest/BRAMTest_APF.ucf 2008-02-10 14:33:27 UTC (rev 760)
+++ trunk/firmware/BRAMTest/BRAMTest_APF.ucf 2008-02-10 14:50:48 UTC (rev 761)
@@ -1,65 +1,42 @@
-NET "AddrxDI<10>" LOC = "P33" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<11>" LOC = "P35" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<12>" LOC = "P36" | IOSTANDARD = LVCMOS33 ;
-NET "User<0>" LOC = "P92" | IOSTANDARD = LVCMOS33 ;
-NET "User<1>" LOC = "P93" | IOSTANDARD = LVCMOS33 ;
-NET "User<2>" LOC = "P95" | IOSTANDARD = LVCMOS33 ;
-NET "User<3>" LOC = "P96" | IOSTANDARD = LVCMOS33 ;
-NET "User<4>" LOC = "P97" | IOSTANDARD = LVCMOS33 ;
-NET "User<5>" LOC = "P98" | IOSTANDARD = LVCMOS33 ;
-NET "User<6>" LOC = "P99" | IOSTANDARD = LVCMOS33 ;
-NET "User<7>" LOC = "P100" | IOSTANDARD = LVCMOS33 ;
-NET "User<8>" LOC = "P102" | IOSTANDARD = LVCMOS33 ;
-NET "User<9>" LOC = "P103" | IOSTANDARD = LVCMOS33 ;
-NET "User<10>" LOC = "P104" | IOSTANDARD = LVCMOS33 ;
-NET "User<11>" LOC = "P105" | IOSTANDARD = LVCMOS33 ;
-NET "User<12>" LOC = "P107" | IOSTANDARD = LVCMOS33 ;
-NET "User<13>" LOC = "P108" | IOSTANDARD = LVCMOS33 ;
-NET "User<14>" LOC = "P112" | IOSTANDARD = LVCMOS33 ;
-NET "User<15>" LOC = "P113" | IOSTANDARD = LVCMOS33 ;
-NET "User<16>" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
-NET "User<17>" LOC = "P118" | IOSTANDARD = LVCMOS33 ;
-NET "User<18>" LOC = "P119" | IOSTANDARD = LVCMOS33 ;
-NET "User<19>" LOC = "P122" | IOSTANDARD = LVCMOS33 ;
-NET "ClkxCI" TNM_NET = "ClkxCI";
-TIMESPEC "TS_ClkxCI" = PERIOD "ClkxCI" 10 ns HIGH 50 %;
-
-#PACE: Start of Constraints generated by PACE
-
-#PACE: Start of PACE I/O Pin Assignments
-NET "AddrxDI<0>" LOC = "P21" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<1>" LOC = "P23" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<2>" LOC = "P24" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<3>" LOC = "P25" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<4>" LOC = "P26" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<5>" LOC = "P27" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<6>" LOC = "P28" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<7>" LOC = "P30" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<8>" LOC = "P31" | IOSTANDARD = LVCMOS33 ;
-NET "AddrxDI<9>" LOC = "P32" | IOSTANDARD = LVCMOS33 ;
-NET "ClkxCI" LOC = "P55" | IOSTANDARD = LVCMOS33 ;
-NET "CSxBI" LOC = "P59" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<0>" LOC = "P1" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<10>" LOC = "P13" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<11>" LOC = "P14" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<12>" LOC = "P15" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<13>" LOC = "P17" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<14>" LOC = "P18" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<15>" LOC = "P20" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<1>" LOC = "P2" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<2>" LOC = "P4" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<3>" LOC = "P5" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<4>" LOC = "P6" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<5>" LOC = "P7" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<6>" LOC = "P8" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<7>" LOC = "P10" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<8>" LOC = "P11" | IOSTANDARD = LVCMOS33 ;
-NET "DataxD<9>" LOC = "P12" | IOSTANDARD = LVCMOS33 ;
-NET "WRxBI" LOC = "P60" | IOSTANDARD = LVCMOS33 ;
-NET "RDxBI" LOC = "P63" | IOSTANDARD = LVCMOS33 ;
-
-#PACE: Start of PACE Area Constraints
-
-#PACE: Start of PACE Prohibit Constraints
-
-#PACE: End of Constraints generated by PACE
+NET "ClkxCI" TNM_NET = "ClkxCI";
+TIMESPEC "TS_ClkxCI" = PERIOD "ClkxCI" 10 ns HIGH 50 %;
+
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "AddrxDI<0>" LOC = "P21" | IOSTANDARD = LVCMOS33 ;
+NET "AddrxDI<1>" LOC = "P23" | IOSTANDARD = LVCMOS33 ;
+NET "AddrxDI<2>" LOC = "P24" | IOSTANDARD = LVCMOS33 ;
+NET "AddrxDI<3>" LOC = "P25" | IOSTANDARD = LVCMOS33 ;
+NET "AddrxDI<4>" LOC = "P26" | IOSTANDARD = LVCMOS33 ;
+NET "AddrxDI<5>" LOC = "P27" | IOSTANDARD = LVCMOS33 ;
+NET "AddrxDI<6>" LOC = "P28" | IOSTANDARD = LVCMOS33 ;
+NET "AddrxDI<7>" LOC = "P30" | IOSTANDARD = LVCMOS33 ;
+NET "AddrxDI<8>" LOC = "P31" | IOSTANDARD = LVCMOS33 ;
+NET "AddrxDI<9>" LOC = "P32" | IOSTANDARD = LVCMOS33 ;
+NET "ClkxCI" LOC = "P55" | IOSTANDARD = LVCMOS33 ;
+NET "CSxBI" LOC = "P59" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<0>" LOC = "P1" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<10>" LOC = "P13" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<11>" LOC = "P14" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<12>" LOC = "P15" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<13>" LOC = "P17" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<14>" LOC = "P18" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<15>" LOC = "P20" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<1>" LOC = "P2" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<2>" LOC = "P4" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<3>" LOC = "P5" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<4>" LOC = "P6" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<5>" LOC = "P7" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<6>" LOC = "P8" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<7>" LOC = "P10" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<8>" LOC = "P11" | IOSTANDARD = LVCMOS33 ;
+NET "DataxD<9>" LOC = "P12" | IOSTANDARD = LVCMOS33 ;
+NET "WRxBI" LOC = "P60" | IOSTANDARD = LVCMOS33 ;
+NET "RDxBI" LOC = "P63" | IOSTANDARD = LVCMOS33 ;
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
Modified: trunk/firmware/BRAMTest/BRAMtest.ise
===================================================================
(Binary files differ)
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