[Armadeus-commitlog] SF.net SVN: armadeus: [624] trunk/firmware
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[Armadeus-commitlog] SF.net SVN: armadeus: [624] trunk/firmware
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From: <th...@us...> - 2007-08-27 14:36:26
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Revision: 624
http://armadeus.svn.sourceforge.net/armadeus/?rev=624&view=rev
Author: thom25
Date: 2007-08-26 07:27:43 -0700 (Sun, 26 Aug 2007)
Log Message:
-----------
add SRAM test VHDL code for the Devfull
Added Paths:
-----------
trunk/firmware/sram_test/
trunk/firmware/sram_test/sram_test.ise
trunk/firmware/sram_test/sram_test.ucf
trunk/firmware/sram_test/sram_test.vhd
Added: trunk/firmware/sram_test/sram_test.ise
===================================================================
(Binary files differ)
Property changes on: trunk/firmware/sram_test/sram_test.ise
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: trunk/firmware/sram_test/sram_test.ucf
===================================================================
--- trunk/firmware/sram_test/sram_test.ucf (rev 0)
+++ trunk/firmware/sram_test/sram_test.ucf 2007-08-26 14:27:43 UTC (rev 624)
@@ -0,0 +1,102 @@
+#NET "ClkxCI" TNM_NET = "ClkxCI";
+#TIMESPEC "TS_ClkxCI" = PERIOD "ClkxCI" 10 ns HIGH 50 %;
+
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+
+# -------------------- Generic -----------------------
+
+NET "AddrxDI<0>" LOC = "P21" ;
+NET "AddrxDI<1>" LOC = "P23" ;
+NET "AddrxDI<2>" LOC = "P24" ;
+NET "AddrxDI<3>" LOC = "P25" ;
+NET "AddrxDI<4>" LOC = "P26" ;
+NET "AddrxDI<5>" LOC = "P27" ;
+NET "AddrxDI<6>" LOC = "P28" ;
+NET "AddrxDI<7>" LOC = "P30" ;
+NET "AddrxDI<8>" LOC = "P31" ;
+NET "AddrxDI<9>" LOC = "P32" ;
+NET "AddrxDI<10>" LOC = "P33" ;
+NET "AddrxDI<11>" LOC = "P35" ;
+NET "AddrxDI<12>" LOC = "P36" ;
+
+NET "ClkxCI" LOC = "P55" ;
+NET "CSxBI" LOC = "P59" ;
+NET "DataxD<0>" LOC = "P1" ;
+NET "DataxD<10>" LOC = "P13" ;
+NET "DataxD<11>" LOC = "P14" ;
+NET "DataxD<12>" LOC = "P15" ;
+NET "DataxD<13>" LOC = "P17" ;
+NET "DataxD<14>" LOC = "P18" ;
+NET "DataxD<15>" LOC = "P20" ;
+NET "DataxD<1>" LOC = "P2" ;
+NET "DataxD<2>" LOC = "P4" ;
+NET "DataxD<3>" LOC = "P5" ;
+NET "DataxD<4>" LOC = "P6" ;
+NET "DataxD<5>" LOC = "P7" ;
+NET "DataxD<6>" LOC = "P8" ;
+NET "DataxD<7>" LOC = "P10" ;
+NET "DataxD<8>" LOC = "P11" ;
+NET "DataxD<9>" LOC = "P12" ;
+NET "WRxBI" LOC = "P60" ;
+NET "RDxBI" LOC = "P63" ;
+
+# -------------------Test Specific FOR A CY7C1021 !!!!!!---------------------------
+
+NET "SRAM_Addr<0>" LOC = "P74" ;
+NET "SRAM_Addr<1>" LOC = "P77" ;
+NET "SRAM_Addr<2>" LOC = "P79" ;
+NET "SRAM_Addr<3>" LOC = "P82" ;
+NET "SRAM_Addr<4>" LOC = "P84" ;
+NET "SRAM_Addr<5>" LOC = "P73" ;
+NET "SRAM_Addr<6>" LOC = "P53" ;
+NET "SRAM_Addr<7>" LOC = "P51" ;
+NET "SRAM_Addr<8>" LOC = "P99" ;
+NET "SRAM_Addr<9>" LOC = "P100" ;
+NET "SRAM_Addr<10>" LOC = "P102" ;
+NET "SRAM_Addr<11>" LOC = "P103" ;
+NET "SRAM_Addr<12>" LOC = "P86" ;
+NET "SRAM_Addr<13>" LOC = "P87" ;
+NET "SRAM_Addr<14>" LOC = "P108" ;
+NET "SRAM_Addr<15>" LOC = "P107" ;
+
+# different mapping for a CY7C1011
+#NET "SRAM_Addr<12>" LOC = "P104" ;
+#NET "SRAM_Addr<13>" LOC = "P86" ;
+#NET "SRAM_Addr<14>" LOC = "P87" ;
+#NET "SRAM_Addr<15>" LOC = "P108" ;
+#NET "SRAM_Addr<16>" LOC = "P107" ;
+#NET "SRAM_Addr<17>" LOC = "P85" ;
+
+NET "SRAM_Data<0>" LOC = "P52" ;
+NET "SRAM_Data<1>" LOC = "P50" ;
+NET "SRAM_Data<2>" LOC = "P46" ;
+NET "SRAM_Data<3>" LOC = "P41" ;
+NET "SRAM_Data<4>" LOC = "P83" ;
+NET "SRAM_Data<5>" LOC = "P80" ;
+NET "SRAM_Data<6>" LOC = "P78" ;
+NET "SRAM_Data<7>" LOC = "P76" ;
+NET "SRAM_Data<8>" LOC = "P98" ;
+NET "SRAM_Data<9>" LOC = "P97" ;
+NET "SRAM_Data<10>" LOC = "P96" ;
+NET "SRAM_Data<11>" LOC = "P95" ;
+NET "SRAM_Data<12>" LOC = "P93" ;
+NET "SRAM_Data<13>" LOC = "P92" ;
+NET "SRAM_Data<14>" LOC = "P90" ;
+NET "SRAM_Data<15>" LOC = "P89" ;
+
+NET "SRAM_WEn" LOC = "P105" ;
+NET "SRAM_OEn" LOC = "P47" ;
+NET "SRAM_CEn" LOC = "P56" ;
+NET "SRAM_BLEn" LOC = "P40" ;
+NET "SRAM_BHEn" LOC = "P44" ;
+
+#NET "DEBUG" LOC = "P116";
+
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
\ No newline at end of file
Added: trunk/firmware/sram_test/sram_test.vhd
===================================================================
--- trunk/firmware/sram_test/sram_test.vhd (rev 0)
+++ trunk/firmware/sram_test/sram_test.vhd 2007-08-26 14:27:43 UTC (rev 624)
@@ -0,0 +1,141 @@
+--------------------------------------------------------------------------------
+-- Company: Armadeus Systems
+-- Engineer: NC
+--
+-- Create Date: 23:04:42 08/26/07
+-- Design Name: DEVFULL SRAM TEST
+-- Module Name: SRAM_test - Behavioral
+-- Project Name:
+-- Target Device:
+-- Tool versions:
+-- Description: Used to access the DevFull SRAM (CY7C1021) from UBOOT
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+--use IEEE.STD_LOGIC_ARITH.all;
+--use IEEE.STD_LOGIC_UNSIGNED.all;
+--library UNISIM;
+--use UNISIM.VComponents.all;
+--library XilinxCoreLib;
+--use XilinxCoreLib.all;
+
+
+entity sram_test is -- this is the top
+ port ( DataxD : inout std_logic_vector(15 downto 0);
+ AddrxDI : in std_logic_vector(12 downto 0);
+ WRxBI : in std_logic;
+ RDxBI : in std_logic;
+
+ ClkxCI : in std_logic; --imx bus clock
+ CSxBI : in std_logic; -- fpga CS
+
+ SRAM_Addr : out std_logic_vector(15 downto 0); -- CY7C1021
+ SRAM_Data : inout std_logic_vector(15 downto 0);
+ SRAM_WEn : out std_logic;
+ SRAM_OEn : out std_logic;
+ SRAM_CEn : out std_logic;
+ SRAM_BLEn : out std_logic;
+ SRAM_BHEn : out std_logic
+ );
+end sram_test;
+
+architecture hierarchical of sram_test is
+
+ type readAccessType is ('0','1','2');
+ subtype reg is std_logic_vector (12 downto 0);
+
+ constant SRAM_READ : readAccessType := '0';
+ constant INTERNAL_READ : readAccessType := '1';
+ constant OTHER_READ : readAccessType := '2';
+ constant DATA_REGISTER : reg := b"0000000000010";
+ constant ADDRESS_REGISTER: reg := b"0000000000000";
+
+ signal resetn : std_logic;
+ signal DataxD_out : std_logic_vector(15 downto 0);
+ signal regSRAM_Data_out : std_logic_vector(15 downto 0);
+ signal SRAM_Addr_out : std_logic_vector(15 downto 0);
+ signal regSRAM_WEn_out : std_logic;
+ signal regSRAM_OEn_out : std_logic;
+ signal readAccess : readAccessType;
+
+begin
+
+ resetn <= '1';
+
+ -----------------------------------------------------------------------------
+ -- Process
+ -- purpose: Register Write from businterface
+ -----------------------------------------------------------------------------
+ TestRegister_write : process (CSxBI, ClkxCI, WRxBI, AddrxDI, DataxD )
+ begin -- process TestRegister_write
+ if resetn = '0' then -- asynchronous reset (active low)
+ regSRAM_Data_out <= (others => 'Z');
+ elsif ClkxCI'event and ClkxCI = '1' then -- rising clock edge
+ if CSxBI = '0' and WRxBI = '0' then
+ case AddrxDI is
+ when ADDRESS_REGISTER =>
+ SRAM_Addr_out <= DataxD(15 downto 0);
+ regSRAM_WEn_out <= '1';
+ when DATA_REGISTER =>
+ regSRAM_Data_out <= DataxD(15 downto 0);
+ regSRAM_WEn_out <= '0';
+ when others =>
+ regSRAM_Data_out <= (others => '0');
+ regSRAM_WEn_out <= '1';
+ end case;
+ else
+ regSRAM_Data_out <= (others => 'Z');
+ regSRAM_WEn_out <= '1';
+ end if;
+ end if;
+ end process TestRegister_write;
+
+
+SRAM_read_process : process (ClkxCI, readAccess, SRAM_Data )
+begin -- process TestRegister_write
+ if ClkxCI'event and ClkxCI = '1' then
+ if readAccess = SRAM_READ then
+ DataxD_out <= SRAM_Data(15 downto 0);
+ elsif readAccess = INTERNAL_READ then
+ DataxD_out <= (others => '0');
+ else -- other
+ DataxD_out <= (others => 'Z');
+ end if;
+ end if;
+end process SRAM_read_process;
+
+ TestRegister_read : process (CSxBI, RDxBI, AddrxDI, DataxD, ClkxCI )
+ begin -- process TestRegister_write
+
+ if CSxBI = '0' and RDxBI = '0' then
+ case AddrxDI is
+ when DATA_REGISTER => -- data register
+ regSRAM_OEn_out <= '0';
+ readAccess <= SRAM_READ; -- SRAM read
+ when others =>
+ readAccess <= INTERNAL_READ; -- INTERNAL read
+ regSRAM_OEn_out <= '1';
+ end case;
+ else
+ readAccess <= OTHER_READ;
+ regSRAM_OEn_out <= '1';
+ end if;
+ end process TestRegister_read;
+
+
+ DataxD <= DataxD_out;
+ SRAM_Addr <= SRAM_Addr_out(15 downto 0);
+ SRAM_Data <= regSRAM_Data_out;
+ SRAM_CEn <= CSxBI;
+ SRAM_OEn <= regSRAM_OEn_out;
+ SRAM_WEn <= regSRAM_WEn_out;
+ SRAM_BLEn <= '0';
+ SRAM_BHEn <= '0';
+ end hierarchical;
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