armadeus-commitlog Mailing List for armadeus (Page 38)
Brought to you by:
sszy
Menu
▾
▴
armadeus-commitlog — Armadeus GIT commit logs
You can subscribe to this list here.
| 2006 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
(1) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2007 |
Jan
(43) |
Feb
(8) |
Mar
(7) |
Apr
(8) |
May
(14) |
Jun
(6) |
Jul
(4) |
Aug
(17) |
Sep
(18) |
Oct
(19) |
Nov
(52) |
Dec
(30) |
| 2008 |
Jan
(6) |
Feb
(6) |
Mar
(15) |
Apr
(22) |
May
(13) |
Jun
(11) |
Jul
(41) |
Aug
(10) |
Sep
(14) |
Oct
(21) |
Nov
(4) |
Dec
(66) |
| 2009 |
Jan
(67) |
Feb
(57) |
Mar
(90) |
Apr
(54) |
May
(64) |
Jun
(76) |
Jul
(14) |
Aug
(18) |
Sep
(18) |
Oct
(20) |
Nov
(15) |
Dec
(36) |
| 2010 |
Jan
(28) |
Feb
(25) |
Mar
(32) |
Apr
(23) |
May
(22) |
Jun
(62) |
Jul
(36) |
Aug
(16) |
Sep
(12) |
Oct
(20) |
Nov
(44) |
Dec
(25) |
| 2011 |
Jan
(36) |
Feb
(49) |
Mar
(28) |
Apr
(38) |
May
(26) |
Jun
(52) |
Jul
(33) |
Aug
(32) |
Sep
(19) |
Oct
(26) |
Nov
(13) |
Dec
(32) |
| 2012 |
Jan
(38) |
Feb
(34) |
Mar
(91) |
Apr
(35) |
May
(31) |
Jun
(72) |
Jul
(23) |
Aug
(13) |
Sep
(33) |
Oct
(47) |
Nov
(18) |
Dec
(22) |
| 2013 |
Jan
(31) |
Feb
(22) |
Mar
(26) |
Apr
(11) |
May
(38) |
Jun
(15) |
Jul
(37) |
Aug
(68) |
Sep
(34) |
Oct
(11) |
Nov
(26) |
Dec
(31) |
| 2014 |
Jan
(60) |
Feb
(55) |
Mar
(21) |
Apr
(31) |
May
(17) |
Jun
(35) |
Jul
(24) |
Aug
(17) |
Sep
(11) |
Oct
(23) |
Nov
(10) |
Dec
(23) |
| 2015 |
Jan
(15) |
Feb
(34) |
Mar
(46) |
Apr
(23) |
May
(12) |
Jun
(14) |
Jul
(18) |
Aug
(22) |
Sep
(6) |
Oct
(2) |
Nov
(1) |
Dec
(6) |
| 2016 |
Jan
(5) |
Feb
(7) |
Mar
(10) |
Apr
(10) |
May
(17) |
Jun
(6) |
Jul
(4) |
Aug
(6) |
Sep
(22) |
Oct
(8) |
Nov
(9) |
Dec
(5) |
| 2017 |
Jan
(11) |
Feb
(12) |
Mar
(27) |
Apr
(9) |
May
(1) |
Jun
(5) |
Jul
(11) |
Aug
(10) |
Sep
(6) |
Oct
(10) |
Nov
(4) |
Dec
(6) |
| 2018 |
Jan
(6) |
Feb
(13) |
Mar
(9) |
Apr
(7) |
May
(10) |
Jun
(9) |
Jul
(21) |
Aug
(13) |
Sep
(10) |
Oct
(4) |
Nov
(6) |
Dec
(1) |
| 2019 |
Jan
(6) |
Feb
(2) |
Mar
(5) |
Apr
(6) |
May
(19) |
Jun
(14) |
Jul
(18) |
Aug
(3) |
Sep
(5) |
Oct
(7) |
Nov
(8) |
Dec
(4) |
| 2020 |
Jan
(10) |
Feb
(3) |
Mar
(9) |
Apr
(7) |
May
(2) |
Jun
(18) |
Jul
(3) |
Aug
|
Sep
|
Oct
(7) |
Nov
|
Dec
(1) |
| 2021 |
Jan
(9) |
Feb
(6) |
Mar
(4) |
Apr
(11) |
May
(7) |
Jun
(5) |
Jul
(2) |
Aug
(4) |
Sep
(10) |
Oct
(9) |
Nov
(5) |
Dec
|
| 2022 |
Jan
(2) |
Feb
(12) |
Mar
(3) |
Apr
(5) |
May
(1) |
Jun
(3) |
Jul
(2) |
Aug
(1) |
Sep
(4) |
Oct
(4) |
Nov
(1) |
Dec
(3) |
| 2023 |
Jan
(5) |
Feb
(3) |
Mar
(3) |
Apr
(2) |
May
(1) |
Jun
(3) |
Jul
(3) |
Aug
(2) |
Sep
(1) |
Oct
(1) |
Nov
|
Dec
(4) |
| 2024 |
Jan
(2) |
Feb
(3) |
Mar
(8) |
Apr
(4) |
May
(1) |
Jun
(13) |
Jul
(7) |
Aug
(1) |
Sep
(6) |
Oct
(5) |
Nov
(11) |
Dec
(7) |
| 2025 |
Jan
(3) |
Feb
(1) |
Mar
(6) |
Apr
(4) |
May
(4) |
Jun
(1) |
Jul
(1) |
Aug
(7) |
Sep
(4) |
Oct
(4) |
Nov
(4) |
Dec
(1) |
| 2026 |
Jan
(3) |
Feb
(7) |
Mar
(3) |
Apr
(1) |
May
(6) |
Jun
(3) |
Jul
(1) |
Aug
|
Sep
|
Oct
|
Nov
|
Dec
|
|
From: jorasse <jo...@us...> - 2015-02-14 15:32:29
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 0311ec9e797a27e47cf21134db4030d574951dec (commit)
from a586d7a89dbbeca995a5f4575e8199c7ae191fbb (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0311ec9e797a27e47cf21134db4030d574951dec
Author: Eric Jarrige <eri...@ar...>
Date: Sat Feb 14 16:32:08 2015 +0100
[BUILDROOT] apf51: Bump to U-Boot 2015.01
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf51_defconfig | 8 ++++----
buildroot/configs/apf51mainline_defconfig | 8 ++++----
buildroot/configs/apf51test_defconfig | 8 ++++----
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/buildroot/configs/apf51_defconfig b/buildroot/configs/apf51_defconfig
index ad6a626..cb684b0 100644
--- a/buildroot/configs/apf51_defconfig
+++ b/buildroot/configs/apf51_defconfig
@@ -87,11 +87,11 @@ BR2_TARGET_ROOTFS_UBIFS_MAXLEBCNT=135301
BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-with-nand-spl.imx"
BR2_TARGET_UBOOT_NETWORK=y
diff --git a/buildroot/configs/apf51mainline_defconfig b/buildroot/configs/apf51mainline_defconfig
index 844d547..ed6ef38 100644
--- a/buildroot/configs/apf51mainline_defconfig
+++ b/buildroot/configs/apf51mainline_defconfig
@@ -80,11 +80,11 @@ BR2_TARGET_ROOTFS_UBIFS_MAXLEBCNT=135301
BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-with-nand-spl.imx"
BR2_TARGET_UBOOT_NETWORK=y
diff --git a/buildroot/configs/apf51test_defconfig b/buildroot/configs/apf51test_defconfig
index 94986ad..a76ff8f 100644
--- a/buildroot/configs/apf51test_defconfig
+++ b/buildroot/configs/apf51test_defconfig
@@ -162,11 +162,11 @@ BR2_TARGET_ROOTFS_UBIFS_MAXLEBCNT=135301
BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-with-nand-spl.imx"
BR2_TARGET_UBOOT_NETWORK=y
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-14 11:06:33
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via a586d7a89dbbeca995a5f4575e8199c7ae191fbb (commit)
from 4d3fdecdfea9b6609b9e099dc530f83e322bb5d1 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a586d7a89dbbeca995a5f4575e8199c7ae191fbb
Author: Eric Jarrige <eri...@ar...>
Date: Sat Feb 14 12:06:14 2015 +0100
[UBOOT] 2015.01: apf6: don't use env vars in bootstrap
-----------------------------------------------------------------------
Summary of changes:
.../602-apf6-in_bootstrap_dont_use_env_vars.patch} | 0
1 files changed, 0 insertions(+), 0 deletions(-)
copy patches/u-boot/{2014.07/506-apf6-in_bootstrap_dont_use_env_vars.patch => 2015.01/602-apf6-in_bootstrap_dont_use_env_vars.patch} (100%)
diff --git a/patches/u-boot/2014.07/506-apf6-in_bootstrap_dont_use_env_vars.patch b/patches/u-boot/2015.01/602-apf6-in_bootstrap_dont_use_env_vars.patch
similarity index 100%
copy from patches/u-boot/2014.07/506-apf6-in_bootstrap_dont_use_env_vars.patch
copy to patches/u-boot/2015.01/602-apf6-in_bootstrap_dont_use_env_vars.patch
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-14 10:53:13
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 4d3fdecdfea9b6609b9e099dc530f83e322bb5d1 (commit)
from 4892533aaed1ea972a2df61208e7907574dfd853 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4d3fdecdfea9b6609b9e099dc530f83e322bb5d1
Author: Eric Jarrige <eri...@ar...>
Date: Sat Feb 14 11:53:00 2015 +0100
[BUILDROOT] apf28: Bump to U-Boot 2015.01
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf28_defconfig | 8 ++++----
buildroot/configs/apf28mainline_defconfig | 8 ++++----
buildroot/configs/apf28test_defconfig | 8 ++++----
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/buildroot/configs/apf28_defconfig b/buildroot/configs/apf28_defconfig
index 27ec9f9..c426250 100644
--- a/buildroot/configs/apf28_defconfig
+++ b/buildroot/configs/apf28_defconfig
@@ -80,11 +80,11 @@ BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_ROOTFS_UBI_SUBSIZE=0
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2 "
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_SB=y
BR2_TARGET_UBOOT_NETWORK=y
BR2_TARGET_UBOOT_SERVERIP="192.168.0.2"
diff --git a/buildroot/configs/apf28mainline_defconfig b/buildroot/configs/apf28mainline_defconfig
index 9fb8586..d7cf4f1 100644
--- a/buildroot/configs/apf28mainline_defconfig
+++ b/buildroot/configs/apf28mainline_defconfig
@@ -82,11 +82,11 @@ BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_ROOTFS_UBI_SUBSIZE=0
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2 "
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)mainline-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)mainline-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_SB=y
BR2_TARGET_UBOOT_NETWORK=y
BR2_TARGET_UBOOT_SERVERIP="192.168.0.2"
diff --git a/buildroot/configs/apf28test_defconfig b/buildroot/configs/apf28test_defconfig
index dc2bf3d..e898a31 100644
--- a/buildroot/configs/apf28test_defconfig
+++ b/buildroot/configs/apf28test_defconfig
@@ -145,11 +145,11 @@ BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_ROOTFS_UBI_SUBSIZE=0
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2 "
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_SB=y
BR2_TARGET_UBOOT_NETWORK=y
BR2_TARGET_UBOOT_SERVERIP="192.168.0.2"
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-14 09:16:33
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 4892533aaed1ea972a2df61208e7907574dfd853 (commit)
from a4820719e97475820dfdae034da4ca32d4f39864 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4892533aaed1ea972a2df61208e7907574dfd853
Author: Eric Jarrige <eri...@ar...>
Date: Sat Feb 14 10:16:13 2015 +0100
[BUILDROOT] apf27: Bump to U-Boot 2015.01
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf27_defconfig | 8 ++++----
buildroot/configs/apf27_webradio_defconfig | 8 ++++----
buildroot/configs/apf27mainline_defconfig | 8 ++++----
buildroot/configs/apf27test_defconfig | 8 ++++----
buildroot/configs/apf27xenomai_defconfig | 8 ++++----
buildroot/configs/apf27xenomaimainline_defconfig | 8 ++++----
6 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/buildroot/configs/apf27_defconfig b/buildroot/configs/apf27_defconfig
index b38430c..5c512fa 100644
--- a/buildroot/configs/apf27_defconfig
+++ b/buildroot/configs/apf27_defconfig
@@ -81,11 +81,11 @@ BR2_TARGET_ROOTFS_UBIFS_MAXLEBCNT=2047
BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-with-spl.bin"
BR2_TARGET_UBOOT_NETWORK=y
diff --git a/buildroot/configs/apf27_webradio_defconfig b/buildroot/configs/apf27_webradio_defconfig
index c095656..0f16c96 100644
--- a/buildroot/configs/apf27_webradio_defconfig
+++ b/buildroot/configs/apf27_webradio_defconfig
@@ -86,11 +86,11 @@ BR2_TARGET_ROOTFS_UBIFS_MAXLEBCNT=2047
BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-with-spl.bin"
BR2_TARGET_UBOOT_NETWORK=y
diff --git a/buildroot/configs/apf27mainline_defconfig b/buildroot/configs/apf27mainline_defconfig
index 2dd879a..6d59d00 100644
--- a/buildroot/configs/apf27mainline_defconfig
+++ b/buildroot/configs/apf27mainline_defconfig
@@ -84,11 +84,11 @@ BR2_TARGET_ROOTFS_UBIFS_MAXLEBCNT=2047
BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)mainline-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)mainline-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-with-spl.bin"
BR2_TARGET_UBOOT_NETWORK=y
diff --git a/buildroot/configs/apf27test_defconfig b/buildroot/configs/apf27test_defconfig
index d19b0c9..e3ab26b 100644
--- a/buildroot/configs/apf27test_defconfig
+++ b/buildroot/configs/apf27test_defconfig
@@ -158,11 +158,11 @@ BR2_TARGET_ROOTFS_UBIFS_MAXLEBCNT=2047
BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-with-spl.bin"
BR2_TARGET_UBOOT_NETWORK=y
diff --git a/buildroot/configs/apf27xenomai_defconfig b/buildroot/configs/apf27xenomai_defconfig
index 1d9fa90..3672723 100644
--- a/buildroot/configs/apf27xenomai_defconfig
+++ b/buildroot/configs/apf27xenomai_defconfig
@@ -82,11 +82,11 @@ BR2_TARGET_ROOTFS_UBIFS_MAXLEBCNT=2047
BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-with-spl.bin"
BR2_TARGET_UBOOT_NETWORK=y
diff --git a/buildroot/configs/apf27xenomaimainline_defconfig b/buildroot/configs/apf27xenomaimainline_defconfig
index e5340f2..19c7e3a 100644
--- a/buildroot/configs/apf27xenomaimainline_defconfig
+++ b/buildroot/configs/apf27xenomaimainline_defconfig
@@ -86,11 +86,11 @@ BR2_TARGET_ROOTFS_UBIFS_MAXLEBCNT=2047
BR2_TARGET_ROOTFS_UBI=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)mainline-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)mainline-u-boot-2015.01.h"
BR2_TARGET_UBOOT_FORMAT_CUSTOM=y
BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot-with-spl.bin"
BR2_TARGET_UBOOT_NETWORK=y
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-13 17:07:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via a4820719e97475820dfdae034da4ca32d4f39864 (commit)
from 580d5919ab6fac192581f033caf5431165af24e9 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a4820719e97475820dfdae034da4ca32d4f39864
Author: Eric Jarrige <eri...@ar...>
Date: Fri Feb 13 18:07:13 2015 +0100
[UBOOT] 2015.01: apf28: update config to be used with mainline kernel
-----------------------------------------------------------------------
Summary of changes:
...ot-2014.04.h => apf28mainline-u-boot-2015.01.h} | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
copy buildroot/target/device/armadeus/apf28/{apf28mainline-u-boot-2014.04.h => apf28mainline-u-boot-2015.01.h} (99%)
diff --git a/buildroot/target/device/armadeus/apf28/apf28mainline-u-boot-2014.04.h b/buildroot/target/device/armadeus/apf28/apf28mainline-u-boot-2015.01.h
similarity index 99%
copy from buildroot/target/device/armadeus/apf28/apf28mainline-u-boot-2014.04.h
copy to buildroot/target/device/armadeus/apf28/apf28mainline-u-boot-2015.01.h
index fa9b4a0..3b6d788 100644
--- a/buildroot/target/device/armadeus/apf28/apf28mainline-u-boot-2014.04.h
+++ b/buildroot/target/device/armadeus/apf28/apf28mainline-u-boot-2015.01.h
@@ -115,7 +115,6 @@
/* Environment */
#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
-#define CONFIG_ENV_IS_IN_NAND
/* Environment is in NAND */
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 128kB */
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-13 17:06:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 580d5919ab6fac192581f033caf5431165af24e9 (commit)
from 702a684188659d057fde75759bfa24eedd3be106 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 580d5919ab6fac192581f033caf5431165af24e9
Author: Eric Jarrige <eri...@ar...>
Date: Fri Feb 13 18:06:25 2015 +0100
[UBOOT] 2015.01: apf27: update config to be used with mainline kernel
-----------------------------------------------------------------------
Summary of changes:
...ot-2015.01.h => apf27mainline-u-boot-2015.01.h} | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
copy buildroot/target/device/armadeus/apf27/{apf27-u-boot-2015.01.h => apf27mainline-u-boot-2015.01.h} (99%)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2015.01.h b/buildroot/target/device/armadeus/apf27/apf27mainline-u-boot-2015.01.h
similarity index 99%
copy from buildroot/target/device/armadeus/apf27/apf27-u-boot-2015.01.h
copy to buildroot/target/device/armadeus/apf27/apf27mainline-u-boot-2015.01.h
index 5ce3427..b3f009f 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2015.01.h
+++ b/buildroot/target/device/armadeus/apf27/apf27mainline-u-boot-2015.01.h
@@ -178,7 +178,7 @@
__stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
" ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
-#define ACFG_CONSOLE_DEV ttySMX0
+#define ACFG_CONSOLE_DEV ttymxc0
#define CONFIG_BOOTCOMMAND "run ubifsboot"
#define CONFIG_SYS_AUTOLOAD "no"
/*
@@ -202,6 +202,7 @@
"kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \
"rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \
"board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \
+ "fdt_addr_r=A1000000\0" \
"kernel_addr_r=A0000000\0" \
"check_env=if test -n ${flash_env_version}; " \
"then env default env_version; " \
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-13 17:05:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 702a684188659d057fde75759bfa24eedd3be106 (commit)
via c161dca9b8a220d6dc2bd92b7db4d3fa0d5590d3 (commit)
from 83753c3130c41f439d90554c35bbf3be6c5b54c8 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 702a684188659d057fde75759bfa24eedd3be106
Author: Eric Jarrige <eri...@ar...>
Date: Fri Feb 13 18:04:57 2015 +0100
[UBOOT] apf9328: Bump to U-Boot 2015.01
commit c161dca9b8a220d6dc2bd92b7db4d3fa0d5590d3
Author: Eric Jarrige <eri...@ar...>
Date: Fri Feb 13 18:03:41 2015 +0100
[UBOOT] 2015.01: apf9328: Fix compil issue
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf9328_defconfig | 8 ++++----
buildroot/configs/apf9328test_defconfig | 8 ++++----
buildroot/configs/apf9328xenomai_defconfig | 8 ++++----
.../armadeus/apf9328/apf9328-u-boot-2015.01.h | 1 -
4 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/buildroot/configs/apf9328_defconfig b/buildroot/configs/apf9328_defconfig
index d40c971..631aaf4 100644
--- a/buildroot/configs/apf9328_defconfig
+++ b/buildroot/configs/apf9328_defconfig
@@ -67,11 +67,11 @@ BR2_TARGET_ROOTFS_JFFS2=y
BR2_TARGET_ROOTFS_JFFS2_PAD=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_NETWORK=y
BR2_TARGET_UBOOT_SERVERIP="192.168.0.2"
BR2_TARGET_UBOOT_IPADDR="192.168.0.10"
diff --git a/buildroot/configs/apf9328test_defconfig b/buildroot/configs/apf9328test_defconfig
index 8c6db0c..1d458fc 100644
--- a/buildroot/configs/apf9328test_defconfig
+++ b/buildroot/configs/apf9328test_defconfig
@@ -125,11 +125,11 @@ BR2_TARGET_ROOTFS_JFFS2=y
BR2_TARGET_ROOTFS_JFFS2_PAD=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_NETWORK=y
BR2_TARGET_UBOOT_SERVERIP="192.168.0.2"
BR2_TARGET_UBOOT_IPADDR="192.168.0.10"
diff --git a/buildroot/configs/apf9328xenomai_defconfig b/buildroot/configs/apf9328xenomai_defconfig
index 5df6d35..9ab95bc 100644
--- a/buildroot/configs/apf9328xenomai_defconfig
+++ b/buildroot/configs/apf9328xenomai_defconfig
@@ -71,11 +71,11 @@ BR2_TARGET_ROOTFS_JFFS2=y
BR2_TARGET_ROOTFS_JFFS2_PAD=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2014.04.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.04"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2015.01"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2015.01"
BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
-BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.04.h"
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2015.01.h"
BR2_TARGET_UBOOT_NETWORK=y
BR2_TARGET_UBOOT_SERVERIP="192.168.0.2"
BR2_TARGET_UBOOT_IPADDR="192.168.0.10"
diff --git a/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2015.01.h b/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2015.01.h
index 56e4852..1bd8cbf 100644
--- a/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2015.01.h
+++ b/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2015.01.h
@@ -18,7 +18,6 @@
#define CONFIG_ARM920T /* this is an ARM920T CPU */
#define CONFIG_IMX /* in a Motorola MC9328MXL Chip */
#define CONFIG_MACH_TYPE 906 /* APF9328 */
-#define CONFIG_SYS_GENERIC_BOARD
/*
* Enable the call to miscellaneous platform dependent initialization.
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-12 10:46:57
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 83753c3130c41f439d90554c35bbf3be6c5b54c8 (commit)
from 4018ef7c9e393b6f8713d412b256dd01cc96af21 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 83753c3130c41f439d90554c35bbf3be6c5b54c8
Author: Eric Jarrige <eri...@ar...>
Date: Thu Feb 12 11:46:45 2015 +0100
[UBOOT] 2015.01: update apf27 U-Boot config
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf27/apf27-u-boot-2015.01.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2015.01.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2015.01.h
index 22102f8..5ce3427 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2015.01.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2015.01.h
@@ -76,6 +76,8 @@
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII /* MII support */
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-12 10:46:10
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 4018ef7c9e393b6f8713d412b256dd01cc96af21 (commit)
via c5c83a9f94798348c3ca84bb2aa28e410898d9dc (commit)
from 7528ab0f4bd3205b06a4540177829c258382c03c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4018ef7c9e393b6f8713d412b256dd01cc96af21
Author: Eric Jarrige <eri...@ar...>
Date: Thu Feb 12 11:45:29 2015 +0100
[UBOOT] 2015.01: add apf51 U-Boot config
commit c5c83a9f94798348c3ca84bb2aa28e410898d9dc
Author: Eric Jarrige <eri...@ar...>
Date: Thu Feb 12 11:45:00 2015 +0100
[UBOOT] 2015.01: add apf28 U-Boot config
-----------------------------------------------------------------------
Summary of changes:
...f28-u-boot-2014.04.h => apf28-u-boot-2015.01.h} | 1 -
...f51-u-boot-2014.04.h => apf51-u-boot-2015.01.h} | 11 +++++------
2 files changed, 5 insertions(+), 7 deletions(-)
copy buildroot/target/device/armadeus/apf28/{apf28-u-boot-2014.04.h => apf28-u-boot-2015.01.h} (99%)
copy buildroot/target/device/armadeus/apf51/{apf51-u-boot-2014.04.h => apf51-u-boot-2015.01.h} (99%)
diff --git a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2014.04.h b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2015.01.h
similarity index 99%
copy from buildroot/target/device/armadeus/apf28/apf28-u-boot-2014.04.h
copy to buildroot/target/device/armadeus/apf28/apf28-u-boot-2015.01.h
index 8b6facf..8b94528 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2014.04.h
+++ b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2015.01.h
@@ -115,7 +115,6 @@
/* Environment */
#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
-#define CONFIG_ENV_IS_IN_NAND
/* Environment is in NAND */
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 128kB */
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2015.01.h
similarity index 99%
copy from buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
copy to buildroot/target/device/armadeus/apf51/apf51-u-boot-2015.01.h
index 10633c3..515a8bb 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2014.04.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2015.01.h
@@ -15,9 +15,9 @@
/*
* SoC configurations
*/
-#define CONFIG_ARMV7 /* This is armv7 Cortex-A8 CPU */
#define CONFIG_MX51 /* in a Freescale i.MX51 Chip */
#define CONFIG_MACH_TYPE 2795 /* APF51 */
+#define CONFIG_SYS_GENERIC_BOARD
/*
* Enable the call to miscellaneous platform dependent initialization.
@@ -34,7 +34,6 @@
/*
* SPL
*/
-#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx"
@@ -90,8 +89,10 @@
#define CONFIG_CMD_DNS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
+#define CONFIG_CMD_FUSE
#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_IIM /* imx iim fuse */
#define CONFIG_CMD_MII /* MII support */
#define CONFIG_CMD_MMC
#define CONFIG_CMD_MTDPARTS /* MTD partition support */
@@ -436,9 +437,7 @@
* Fuses - IIM
*/
-#define CONFIG_IMX_IIM
-#define CONFIG_IIM_MAC_BANK 1
-#define CONFIG_IIM_MAC_ROW 9
+#define CONFIG_FSL_IIM
/*
* I2C
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-12 10:42:59
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 7528ab0f4bd3205b06a4540177829c258382c03c (commit)
from b7f162d3b29b48f64dfebe08dce93b66b735b31a (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7528ab0f4bd3205b06a4540177829c258382c03c
Author: Eric Jarrige <eri...@ar...>
Date: Thu Feb 12 11:42:47 2015 +0100
[UBOOT] 2015.01: apf51: fix FPGA management failure
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2015.01/401-apf51.patch | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/patches/u-boot/2015.01/401-apf51.patch b/patches/u-boot/2015.01/401-apf51.patch
index 44dceaf..2a595d5 100644
--- a/patches/u-boot/2015.01/401-apf51.patch
+++ b/patches/u-boot/2015.01/401-apf51.patch
@@ -716,7 +716,7 @@ new file mode 100644
index 0000000..665928e
--- /dev/null
+++ b/board/armadeus/apf51/fpga.c
-@@ -0,0 +1,240 @@
+@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2002-2010
+ * Nicolas Colombain <nic...@ar...>
@@ -778,7 +778,8 @@ index 0000000..665928e
+ slave_parallel,
+ 3713568l / 8,
+ (void *)&fpga_fns,
-+ 0}
++ 0,
++ &spartan3_op}
+};
+
+/*
hooks/post-receive
--
armadeus
|
|
From: Fabien M <fa...@us...> - 2015-02-12 08:15:30
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via b7f162d3b29b48f64dfebe08dce93b66b735b31a (commit)
via be0af964be82b0e56262fc3d77209f3f505b255e (commit)
from d42cb157071e99f1d104e39143e882f875ccdba0 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit b7f162d3b29b48f64dfebe08dce93b66b735b31a
Author: Fabien Marteau <fab...@ar...>
Date: Thu Feb 12 09:13:34 2015 +0100
[LINUX] dos->unix file format
commit be0af964be82b0e56262fc3d77209f3f505b255e
Author: Fabien Marteau <fab...@ar...>
Date: Thu Feb 12 09:12:36 2015 +0100
[LINUX] more return checking
-----------------------------------------------------------------------
Summary of changes:
.../modules/fpga/dev_tools/loader/altera_cvp.c | 1078 ++++++++++----------
1 files changed, 545 insertions(+), 533 deletions(-)
diff --git a/target/linux/modules/fpga/dev_tools/loader/altera_cvp.c b/target/linux/modules/fpga/dev_tools/loader/altera_cvp.c
index 5b0f207..0e6ad94 100644
--- a/target/linux/modules/fpga/dev_tools/loader/altera_cvp.c
+++ b/target/linux/modules/fpga/dev_tools/loader/altera_cvp.c
@@ -1,533 +1,545 @@
-/*
- * altera_cvp.c -- driver for configuring Altera FPGAs via CvP
- *
- * Written by: Andres Cassinelli <aca...@al...>
- * Altera Corporation
- *
- * Copyright (C) 2012 Altera Corporation. All Rights Reserved.
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license. The text of
- * the BSD license is provided below.
- *
- * BSD License
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * Alternatively, provided that this notice is retained in full, this software
- * may be distributed under the terms of the GNU General Public License ("GPL")
- * version 2, in which case the provisions of the GPL apply INSTEAD OF those
- * given above. A copy of the GPL may be found in the file GPLv2.txt provided
- * with this distribution in the same directory as this file.
- *
- * THIS SOFTWARE IS PROVIDED BY ALTERA CORPORATION "AS IS" AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT ARE
- * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
- * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/device.h> /* dev_err(), etc. */
-#include <linux/pci.h>
-#include <linux/init.h>
-#include <linux/cdev.h>
-#include <asm/uaccess.h> /* copy_to/from_user */
-#include <linux/slab.h> /* kmalloc */
-#include <linux/file.h>
-#include <linux/fs.h>
-#include "altera_cvp.h"
-
-/* PCIe Vendor & Device IDs are parameters passed to the module when it's loaded */
-static unsigned short vid = 0x1172; /* default to Altera's Vendor ID */
-static unsigned short did = 0xE001; /* default to PCIe Reference Design Device ID */
-module_param(vid, ushort, S_IRUGO);
-module_param(did, ushort, S_IRUGO);
-
-struct altera_cvp_dev cvp_dev; /* contents initialized in altera_cvp_init() */
-static unsigned int altera_cvp_major; /* major number to use */
-
-/* CvP helper functions */
-
-static int altera_cvp_get_offset_and_mask(int bit, int *byte_offset, u8 *mask)
-{
- switch (bit) {
- case DATA_ENCRYPTED:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
- *mask = MASK_DATA_ENCRYPTED;
- break;
- case DATA_COMPRESSED:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
- *mask = MASK_DATA_COMPRESSED;
- break;
- case CVP_CONFIG_READY:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
- *mask = MASK_CVP_CONFIG_READY;
- break;
- case CVP_CONFIG_ERROR:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
- *mask = MASK_CVP_CONFIG_ERROR;
- break;
- case CVP_EN:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
- *mask = MASK_CVP_EN;
- break;
- case USER_MODE:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
- *mask = MASK_USER_MODE;
- break;
- case PLD_CLK_IN_USE:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS + 1;
- *mask = MASK_PLD_CLK_IN_USE;
- break;
- case CVP_MODE:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_MODE_CTRL;
- *mask = MASK_CVP_MODE;
- break;
- case HIP_CLK_SEL:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_MODE_CTRL;
- *mask = MASK_HIP_CLK_SEL;
- break;
- case CVP_CONFIG:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_PROG_CTRL;
- *mask = MASK_CVP_CONFIG;
- break;
- case START_XFER:
- *byte_offset = OFFSET_VSEC + OFFSET_CVP_PROG_CTRL;
- *mask = MASK_START_XFER;
- break;
- case CVP_CFG_ERR_LATCH:
- *byte_offset = OFFSET_VSEC + OFFSET_UNC_IE_STATUS;
- *mask = MASK_CVP_CFG_ERR_LATCH;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static int altera_cvp_read_bit(int bit, u8 *value)
-{
- int byte_offset;
- u8 byte_val, byte_mask;
- if (altera_cvp_get_offset_and_mask(bit, &byte_offset, &byte_mask))
- return -EINVAL;
- if (pci_read_config_byte(cvp_dev.pci_dev, byte_offset, &byte_val))
- return -EAGAIN;
- *value = (byte_val & byte_mask) ? 1 : 0;
- return 0;
-}
-
-static int altera_cvp_write_bit(int bit, u8 value)
-{
- int byte_offset;
- u8 byte_val, byte_mask;
-
- switch (bit) {
- case CVP_MODE:
- case HIP_CLK_SEL:
- case CVP_CONFIG:
- case START_XFER:
- case CVP_CFG_ERR_LATCH:
- altera_cvp_get_offset_and_mask(bit, &byte_offset, &byte_mask);
- pci_read_config_byte(cvp_dev.pci_dev, byte_offset, &byte_val);
- byte_val = value ? (byte_val | byte_mask) : (byte_val & ~byte_mask);
- pci_write_config_byte(cvp_dev.pci_dev, byte_offset, byte_val);
- return 0;
- default:
- return -EINVAL; /* only the bits above are writeable */
- }
-}
-
-static int altera_cvp_set_num_clks(int num_clks)
-{
- if (num_clks < 1 || num_clks > 64)
- return -EINVAL;
- if (num_clks == 64)
- num_clks = 0x00;
- return (pci_write_config_byte(cvp_dev.pci_dev,
- OFFSET_VSEC+OFFSET_CVP_NUMCLKS,
- num_clks));
-}
-
-#define NUM_REG_WRITES 244
-#define DUMMY_VALUE 0x00000000
-/**
- * altera_cvp_switch_clk() - switch between CvP clock and internal clock
- *
- * Issues dummy memory writes to the PCIe HIP, allowing the Control Block to
- * switch between the HIP's CvP clock and the internal clock.
- */
-static int altera_cvp_switch_clk(void)
-{
- int i;
- altera_cvp_set_num_clks(1);
- for (i = 0; i < NUM_REG_WRITES; i++) {
- iowrite32(DUMMY_VALUE, cvp_dev.wr_addr);
- }
- return 0;
-}
-
-static int altera_cvp_set_data_type(void)
-{
- int error, num_clks;
- u8 compr, encr;
-
- if ((error = altera_cvp_read_bit(DATA_COMPRESSED, &compr)) ||
- (error = altera_cvp_read_bit(DATA_ENCRYPTED, &encr)))
- return error;
-
- if (compr)
- num_clks = 8;
- else if (encr)
- num_clks = 4;
- else
- num_clks = 1;
-
- return (altera_cvp_set_num_clks(num_clks));
-}
-
-static int altera_cvp_send_data(u32 *data, unsigned long num_words)
-{
-#ifdef DEBUG
- u8 bit_val;
- unsigned int i;
- for (i = 0; i < num_words; i++) {
- iowrite32(data[i], cvp_dev.wr_addr);
- if (i + 1 % ERR_CHK_INTERVAL == 0) {
- altera_cvp_read_bit(CVP_CONFIG_ERROR, &bit_val);
- if (bit_val) {
- dev_err(&cvp_dev.pci_dev->dev, "CB detected a CRC error "
- "between words %d and %d\n",
- i + 1 - ERR_CHK_INTERVAL,
- i + 1);
- return -EAGAIN;
- }
- }
- }
- dev_info(&cvp_dev.pci_dev->dev, "A total of %ld 32-bit words were "
- "sent to the FPGA\n", num_words);
-#else
- iowrite32_rep(cvp_dev.wr_addr, data, num_words);
-#endif /* DEBUG */
- return 0;
-}
-
-/* Polls the requested bit until it has the specified value (or until timeout) */
-/* Returns 0 once the bit has that value, error code on timeout */
-static int altera_cvp_wait_for_bit(int bit, u8 value)
-{
- u8 bit_val;
- static DECLARE_WAIT_QUEUE_HEAD(cvp_wq);
-
- altera_cvp_read_bit(bit, &bit_val);
- if (bit_val != value) {
- wait_event_timeout(cvp_wq, 0, MAX_WAIT);
- altera_cvp_read_bit(bit, &bit_val);
- if (bit_val != value) {
- dev_info(&cvp_dev.pci_dev->dev, "Timed out while "
- "polling bit %d\n", bit);
- return -EAGAIN;
- }
- }
- return 0;
-}
-
-static int altera_cvp_setup(void)
-{
- altera_cvp_write_bit(HIP_CLK_SEL, 1);
- altera_cvp_write_bit(CVP_MODE, 1);
- altera_cvp_switch_clk(); /* allow CB to sense if system reset is issued */
- altera_cvp_write_bit(CVP_CONFIG, 1); /* request CB to begin CvP transfer */
-
- if (altera_cvp_wait_for_bit(CVP_CONFIG_READY, 1)) /* wait until CB is ready */
- return -EAGAIN;
-
- altera_cvp_switch_clk();
- altera_cvp_write_bit(START_XFER, 1);
- altera_cvp_set_data_type();
- dev_info(&cvp_dev.pci_dev->dev, "Now starting CvP...\n");
- return 0; /* success */
-}
-
-static int altera_cvp_teardown(void)
-{
- u8 bit_val;
-
- /* if necessary, flush remainder buffer */
- if (cvp_dev.remain_size > 0) {
- u32 last_word = 0;
- memcpy(&last_word, cvp_dev.remain, cvp_dev.remain_size);
- altera_cvp_send_data(&last_word, cvp_dev.remain_size);
- }
-
- altera_cvp_write_bit(START_XFER, 0);
- altera_cvp_write_bit(CVP_CONFIG, 0); /* request CB to end CvP transfer */
- altera_cvp_switch_clk();
-
- if (altera_cvp_wait_for_bit(CVP_CONFIG_READY, 0)) /* wait until CB is ready */
- return -EAGAIN;
-
- altera_cvp_read_bit(CVP_CFG_ERR_LATCH, &bit_val);
- if (bit_val) {
- dev_err(&cvp_dev.pci_dev->dev, "Configuration error detected, "
- "CvP has failed\n");
- altera_cvp_write_bit(CVP_CFG_ERR_LATCH, 1); /* clear error bit */
- }
-
- altera_cvp_write_bit(CVP_MODE, 0);
- altera_cvp_write_bit(HIP_CLK_SEL, 0);
-
- if (!bit_val) { /* wait for application layer to be ready */
- altera_cvp_wait_for_bit(PLD_CLK_IN_USE, 1);
- altera_cvp_wait_for_bit(USER_MODE, 1);
- dev_info(&cvp_dev.pci_dev->dev, "CvP successful, application "
- "layer now ready\n");
- }
-
- return 0; /* success */
-}
-
-/* Open and close */
-
-int altera_cvp_open(struct inode *inode, struct file *filp)
-{
- /* enforce single-open */
- if (!atomic_dec_and_test(&cvp_dev.is_available)) {
- atomic_inc(&cvp_dev.is_available);
- return -EBUSY;
- }
-
- if ((filp->f_flags & O_ACCMODE) != O_RDONLY) {
- u8 cvp_enabled = 0;
- if (altera_cvp_read_bit(CVP_EN, &cvp_enabled))
- return -EAGAIN;
- if (cvp_enabled) {
- return altera_cvp_setup();
- } else {
- dev_err(&cvp_dev.pci_dev->dev, "CvP is not enabled in "
- "the design on this "
- "FPGA\n");
- return -EOPNOTSUPP;
- }
- }
- return 0; /* success */
-}
-
-int altera_cvp_release(struct inode *inode, struct file *filp)
-{
- atomic_inc(&cvp_dev.is_available); /* release the device */
- if ((filp->f_flags & O_ACCMODE) != O_RDONLY) {
- return altera_cvp_teardown();
- }
- return 0; /* success */
-}
-
-/* Read and write */
-
-ssize_t altera_cvp_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos)
-{
- int dev_size = NUM_VSEC_REGS * BYTES_IN_REG;
- int i, byte_offset;
- u8 *out_buf;
- ssize_t ret_val; /* number of bytes successfully read */
-
- if (*f_pos >= dev_size)
- return 0; /* we're at EOF already */
- if (*f_pos + count > dev_size)
- count = dev_size - *f_pos; /* we can only read until EOF */
-
- out_buf = kmalloc(count, GFP_KERNEL);
-
- for (i = 0; i < count; i++) {
- byte_offset = OFFSET_VSEC + *f_pos + i;
- pci_read_config_byte(cvp_dev.pci_dev, byte_offset, &out_buf[i]);
- }
-
- if (copy_to_user(buf, out_buf, count)) {
- ret_val = -EFAULT;
- } else {
- *f_pos += count;
- ret_val = count;
- }
-
- kfree(out_buf);
- return ret_val;
-}
-
-ssize_t altera_cvp_write(struct file * filp, const char __user *buf, size_t count, loff_t *f_pos)
-{
- ssize_t ret_val; /* number of bytes successfully transferred */
- u8 *send_buf;
- size_t send_buf_size;
-
- send_buf_size = count + cvp_dev.remain_size;
- send_buf = kmalloc(send_buf_size, GFP_KERNEL);
-
- if (cvp_dev.remain_size > 0)
- memcpy(send_buf, cvp_dev.remain, cvp_dev.remain_size);
-
- if (copy_from_user(send_buf + cvp_dev.remain_size, buf, count)) {
- ret_val = -EFAULT;
- goto exit;
- }
-
- /* calculate new remainder */
- cvp_dev.remain_size = send_buf_size % 4;
-
- /* save bytes in new remainder in cvp_dev */
- if (cvp_dev.remain_size > 0)
- memcpy(cvp_dev.remain,
- send_buf + (send_buf_size - cvp_dev.remain_size),
- cvp_dev.remain_size);
-
- if (altera_cvp_send_data((u32 *)send_buf, send_buf_size / 4)) {
- ret_val = -EAGAIN;
- goto exit;
- }
-
- *f_pos += count;
- ret_val = count;
-exit:
- kfree (send_buf);
- return ret_val;
-}
-
-struct file_operations altera_cvp_fops = {
- .owner = THIS_MODULE,
- .llseek = no_llseek,
- .read = altera_cvp_read,
- .write = altera_cvp_write,
- .open = altera_cvp_open,
- .release = altera_cvp_release,
-};
-
-/* PCI functions */
-
-static int altera_cvp_probe(struct pci_dev *dev, const struct pci_device_id *id)
-{
- int rc = 0;
-
- if((dev->vendor == vid) && (dev->device == did)) {
- rc = pci_enable_device(dev);
- if (rc) {
- dev_err(&dev->dev, "pci_enable device() failed\n");
- return rc;
- }
- dev_info(&dev->dev, "Found and enabled PCI device with "
- "VID 0x%04X, DID 0x%04X\n", vid, did);
-
- rc = pci_request_regions(dev, ALTERA_CVP_DRIVER_NAME);
- if (rc) {
- dev_err(&dev->dev, "pci_request_regions() failed\n");
- return rc;
- }
-
- cvp_dev.wr_addr = pci_iomap(dev, 0, 0);
-
- cvp_dev.pci_dev = dev; /* store pointer for PCI API calls */
- return 0;
- } else {
- dev_err(&dev->dev, "This PCI device does not match "
- "VID 0x%04X, DID 0x%04X\n", vid, did);
- return -ENODEV;
- }
-}
-
-static void altera_cvp_remove(struct pci_dev *dev)
-{
- pci_iounmap(dev, cvp_dev.wr_addr);
- pci_disable_device(dev);
- pci_release_regions(dev);
-}
-
-/* PCIe HIP on FPGA can have any combination of IDs based on design settings */
-static struct pci_device_id pci_ids[] = {
- { PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID), },
- { 0, }
-};
-MODULE_DEVICE_TABLE(pci, pci_ids);
-
-static struct pci_driver cvp_driver = {
- .name = ALTERA_CVP_DRIVER_NAME,
- .id_table = pci_ids,
- .probe = altera_cvp_probe,
- .remove = altera_cvp_remove,
-};
-
-/* Module functions */
-
-static int __init altera_cvp_init(void)
-{
- int rc = 0;
- dev_t dev;
-
- rc = alloc_chrdev_region(&dev, 0, 1, ALTERA_CVP_DEVFILE);
- if (rc) {
- printk(KERN_ERR "%s: Allocation of char device numbers "
- "failed\n", ALTERA_CVP_DRIVER_NAME);
- goto exit;
- }
-
- cvp_dev.dev = dev; /* store major and minor numbers for char device */
- altera_cvp_major = MAJOR(dev);
-
- rc = pci_register_driver(&cvp_driver);
- if (rc) {
- printk(KERN_ERR "%s: PCI driver registration failed\n",
- ALTERA_CVP_DRIVER_NAME);
- unregister_chrdev_region(MKDEV(altera_cvp_major, 0), 1);
- goto exit;
- }
-
- cdev_init(&cvp_dev.cdev, &altera_cvp_fops);
- cvp_dev.cdev.owner = THIS_MODULE;
- rc = cdev_add(&cvp_dev.cdev, dev, 1);
- if (rc) {
- printk(KERN_ERR "%s: Unable to add char device to the "
- "system\n", ALTERA_CVP_DRIVER_NAME);
- pci_unregister_driver(&cvp_driver);
- goto exit;
- }
-
- cvp_dev.remain_size = 0;
- atomic_set(&cvp_dev.is_available, 1);
- printk("successfully init Altera CVP with major %d\n", altera_cvp_major);
-exit:
- return rc;
-}
-
-static void __exit altera_cvp_exit(void)
-{
- cdev_del(&cvp_dev.cdev);
- unregister_chrdev_region(MKDEV(altera_cvp_major, 0), 1);
- pci_unregister_driver(&cvp_driver);
-}
-
-module_init(altera_cvp_init);
-module_exit(altera_cvp_exit);
-
-MODULE_AUTHOR("Andres Cassinelli <aca...@al...>");
-MODULE_DESCRIPTION("Configuration driver for Altera CvP-capable FPGAs");
-MODULE_VERSION(ALTERA_CVP_DRIVER_VERSION);
-MODULE_LICENSE("Dual BSD/GPL");
-
+/*
+ * altera_cvp.c -- driver for configuring Altera FPGAs via CvP
+ *
+ * Written by: Andres Cassinelli <aca...@al...>
+ * Altera Corporation
+ *
+ * Copyright (C) 2012 Altera Corporation. All Rights Reserved.
+ *
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license. The text of
+ * the BSD license is provided below.
+ *
+ * BSD License
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * Alternatively, provided that this notice is retained in full, this software
+ * may be distributed under the terms of the GNU General Public License ("GPL")
+ * version 2, in which case the provisions of the GPL apply INSTEAD OF those
+ * given above. A copy of the GPL may be found in the file GPLv2.txt provided
+ * with this distribution in the same directory as this file.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ALTERA CORPORATION "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h> /* dev_err(), etc. */
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/cdev.h>
+#include <asm/uaccess.h> /* copy_to/from_user */
+#include <linux/slab.h> /* kmalloc */
+#include <linux/file.h>
+#include <linux/fs.h>
+#include "altera_cvp.h"
+
+/* PCIe Vendor & Device IDs are parameters passed to the module when it's loaded */
+static unsigned short vid = 0x1172; /* default to Altera's Vendor ID */
+static unsigned short did = 0xE001; /* default to PCIe Reference Design Device ID */
+module_param(vid, ushort, S_IRUGO);
+module_param(did, ushort, S_IRUGO);
+
+struct altera_cvp_dev cvp_dev; /* contents initialized in altera_cvp_init() */
+static unsigned int altera_cvp_major; /* major number to use */
+
+/* CvP helper functions */
+
+static int altera_cvp_get_offset_and_mask(int bit, int *byte_offset, u8 *mask)
+{
+ switch (bit) {
+ case DATA_ENCRYPTED:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
+ *mask = MASK_DATA_ENCRYPTED;
+ break;
+ case DATA_COMPRESSED:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
+ *mask = MASK_DATA_COMPRESSED;
+ break;
+ case CVP_CONFIG_READY:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
+ *mask = MASK_CVP_CONFIG_READY;
+ break;
+ case CVP_CONFIG_ERROR:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
+ *mask = MASK_CVP_CONFIG_ERROR;
+ break;
+ case CVP_EN:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
+ *mask = MASK_CVP_EN;
+ break;
+ case USER_MODE:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS;
+ *mask = MASK_USER_MODE;
+ break;
+ case PLD_CLK_IN_USE:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_STATUS + 1;
+ *mask = MASK_PLD_CLK_IN_USE;
+ break;
+ case CVP_MODE:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_MODE_CTRL;
+ *mask = MASK_CVP_MODE;
+ break;
+ case HIP_CLK_SEL:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_MODE_CTRL;
+ *mask = MASK_HIP_CLK_SEL;
+ break;
+ case CVP_CONFIG:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_PROG_CTRL;
+ *mask = MASK_CVP_CONFIG;
+ break;
+ case START_XFER:
+ *byte_offset = OFFSET_VSEC + OFFSET_CVP_PROG_CTRL;
+ *mask = MASK_START_XFER;
+ break;
+ case CVP_CFG_ERR_LATCH:
+ *byte_offset = OFFSET_VSEC + OFFSET_UNC_IE_STATUS;
+ *mask = MASK_CVP_CFG_ERR_LATCH;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int altera_cvp_read_bit(int bit, u8 *value)
+{
+ int byte_offset;
+ u8 byte_val, byte_mask;
+ if (altera_cvp_get_offset_and_mask(bit, &byte_offset, &byte_mask))
+ return -EINVAL;
+ if (pci_read_config_byte(cvp_dev.pci_dev, byte_offset, &byte_val))
+ return -EAGAIN;
+ *value = (byte_val & byte_mask) ? 1 : 0;
+ return 0;
+}
+
+static int altera_cvp_write_bit(int bit, u8 value)
+{
+ int byte_offset;
+ u8 byte_val, byte_mask;
+
+ switch (bit) {
+ case CVP_MODE:
+ case HIP_CLK_SEL:
+ case CVP_CONFIG:
+ case START_XFER:
+ case CVP_CFG_ERR_LATCH:
+ if(altera_cvp_get_offset_and_mask(bit, &byte_offset, &byte_mask))
+ return -EINVAL;
+ pci_read_config_byte(cvp_dev.pci_dev, byte_offset, &byte_val);
+ byte_val = value ? (byte_val | byte_mask) : (byte_val & ~byte_mask);
+ pci_write_config_byte(cvp_dev.pci_dev, byte_offset, byte_val);
+ return 0;
+ default:
+ return -EINVAL; /* only the bits above are writeable */
+ }
+}
+
+static int altera_cvp_set_num_clks(int num_clks)
+{
+ if (num_clks < 1 || num_clks > 64)
+ return -EINVAL;
+ if (num_clks == 64)
+ num_clks = 0x00;
+ return (pci_write_config_byte(cvp_dev.pci_dev,
+ OFFSET_VSEC+OFFSET_CVP_NUMCLKS,
+ num_clks));
+}
+
+#define NUM_REG_WRITES 244
+#define DUMMY_VALUE 0x00000000
+/**
+ * altera_cvp_switch_clk() - switch between CvP clock and internal clock
+ *
+ * Issues dummy memory writes to the PCIe HIP, allowing the Control Block to
+ * switch between the HIP's CvP clock and the internal clock.
+ */
+static int altera_cvp_switch_clk(void)
+{
+ int i;
+ altera_cvp_set_num_clks(1);
+ for (i = 0; i < NUM_REG_WRITES; i++) {
+ iowrite32(DUMMY_VALUE, cvp_dev.wr_addr);
+ }
+ return 0;
+}
+
+static int altera_cvp_set_data_type(void)
+{
+ int error, num_clks;
+ u8 compr, encr;
+
+ if ((error = altera_cvp_read_bit(DATA_COMPRESSED, &compr)) ||
+ (error = altera_cvp_read_bit(DATA_ENCRYPTED, &encr)))
+ return error;
+
+ if (compr)
+ num_clks = 8;
+ else if (encr)
+ num_clks = 4;
+ else
+ num_clks = 1;
+
+ return (altera_cvp_set_num_clks(num_clks));
+}
+
+static int altera_cvp_send_data(u32 *data, unsigned long num_words)
+{
+#ifdef DEBUG
+ u8 bit_val;
+ unsigned int i;
+ for (i = 0; i < num_words; i++) {
+ iowrite32(data[i], cvp_dev.wr_addr);
+ if (i + 1 % ERR_CHK_INTERVAL == 0) {
+ altera_cvp_read_bit(CVP_CONFIG_ERROR, &bit_val);
+ if (bit_val) {
+ dev_err(&cvp_dev.pci_dev->dev, "CB detected a CRC error "
+ "between words %d and %d\n",
+ i + 1 - ERR_CHK_INTERVAL,
+ i + 1);
+ return -EAGAIN;
+ }
+ }
+ }
+ dev_info(&cvp_dev.pci_dev->dev, "A total of %ld 32-bit words were "
+ "sent to the FPGA\n", num_words);
+#else
+ iowrite32_rep(cvp_dev.wr_addr, data, num_words);
+#endif /* DEBUG */
+ return 0;
+}
+
+/* Polls the requested bit until it has the specified value (or until timeout) */
+/* Returns 0 once the bit has that value, error code on timeout */
+static int altera_cvp_wait_for_bit(int bit, u8 value)
+{
+ u8 bit_val;
+ static DECLARE_WAIT_QUEUE_HEAD(cvp_wq);
+
+ altera_cvp_read_bit(bit, &bit_val);
+ if (bit_val != value) {
+ wait_event_timeout(cvp_wq, 0, MAX_WAIT);
+ altera_cvp_read_bit(bit, &bit_val);
+ if (bit_val != value) {
+ dev_info(&cvp_dev.pci_dev->dev, "Timed out while "
+ "polling bit %d\n", bit);
+ return -EAGAIN;
+ }
+ }
+ return 0;
+}
+
+static int altera_cvp_setup(void)
+{
+ if(altera_cvp_write_bit(HIP_CLK_SEL, 1))
+ return -EINVAL;
+ if(altera_cvp_write_bit(CVP_MODE, 1))
+ return -EINVAL;
+ altera_cvp_switch_clk(); /* allow CB to sense if system reset is issued */
+ if(altera_cvp_write_bit(CVP_CONFIG, 1)) /* request CB to begin CvP transfer */
+ return -EINVAL;
+
+ if (altera_cvp_wait_for_bit(CVP_CONFIG_READY, 1)) /* wait until CB is ready */
+ return -EAGAIN;
+
+ altera_cvp_switch_clk();
+ if(altera_cvp_write_bit(START_XFER, 1))
+ return -EINVAL;
+ altera_cvp_set_data_type();
+ dev_info(&cvp_dev.pci_dev->dev, "Now starting CvP...\n");
+ return 0; /* success */
+}
+
+static int altera_cvp_teardown(void)
+{
+ u8 bit_val;
+
+ /* if necessary, flush remainder buffer */
+ if (cvp_dev.remain_size > 0) {
+ u32 last_word = 0;
+ memcpy(&last_word, cvp_dev.remain, cvp_dev.remain_size);
+ altera_cvp_send_data(&last_word, cvp_dev.remain_size);
+ }
+
+ if(altera_cvp_write_bit(START_XFER, 0))
+ return -EINVAL;
+ if(altera_cvp_write_bit(CVP_CONFIG, 0)) /* request CB to end CvP transfer */
+ return -EINVAL;
+ altera_cvp_switch_clk();
+
+ if (altera_cvp_wait_for_bit(CVP_CONFIG_READY, 0)) /* wait until CB is ready */
+ return -EAGAIN;
+
+ altera_cvp_read_bit(CVP_CFG_ERR_LATCH, &bit_val);
+ if (bit_val) {
+ dev_err(&cvp_dev.pci_dev->dev, "Configuration error detected, "
+ "CvP has failed\n");
+ if(altera_cvp_write_bit(CVP_CFG_ERR_LATCH, 1)) /* clear error bit */
+ return -EINVAL;
+ }
+
+ if(altera_cvp_write_bit(CVP_MODE, 0))
+ return -EINVAL;
+ if(altera_cvp_write_bit(HIP_CLK_SEL, 0))
+ return -EINVAL;
+
+ if (!bit_val) { /* wait for application layer to be ready */
+ if(altera_cvp_wait_for_bit(PLD_CLK_IN_USE, 1))
+ return -EAGAIN;
+ if(altera_cvp_wait_for_bit(USER_MODE, 1))
+ return -EAGAIN;
+ dev_info(&cvp_dev.pci_dev->dev, "CvP successful, application "
+ "layer now ready\n");
+ }
+
+ return 0; /* success */
+}
+
+/* Open and close */
+
+int altera_cvp_open(struct inode *inode, struct file *filp)
+{
+ /* enforce single-open */
+ if (!atomic_dec_and_test(&cvp_dev.is_available)) {
+ atomic_inc(&cvp_dev.is_available);
+ return -EBUSY;
+ }
+
+ if ((filp->f_flags & O_ACCMODE) != O_RDONLY) {
+ u8 cvp_enabled = 0;
+ if (altera_cvp_read_bit(CVP_EN, &cvp_enabled))
+ return -EAGAIN;
+ if (cvp_enabled) {
+ return altera_cvp_setup();
+ } else {
+ dev_err(&cvp_dev.pci_dev->dev, "CvP is not enabled in "
+ "the design on this "
+ "FPGA\n");
+ return -EOPNOTSUPP;
+ }
+ }
+ return 0; /* success */
+}
+
+int altera_cvp_release(struct inode *inode, struct file *filp)
+{
+ atomic_inc(&cvp_dev.is_available); /* release the device */
+ if ((filp->f_flags & O_ACCMODE) != O_RDONLY) {
+ return altera_cvp_teardown();
+ }
+ return 0; /* success */
+}
+
+/* Read and write */
+
+ssize_t altera_cvp_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos)
+{
+ int dev_size = NUM_VSEC_REGS * BYTES_IN_REG;
+ int i, byte_offset;
+ u8 *out_buf;
+ ssize_t ret_val; /* number of bytes successfully read */
+
+ if (*f_pos >= dev_size)
+ return 0; /* we're at EOF already */
+ if (*f_pos + count > dev_size)
+ count = dev_size - *f_pos; /* we can only read until EOF */
+
+ out_buf = kmalloc(count, GFP_KERNEL);
+
+ for (i = 0; i < count; i++) {
+ byte_offset = OFFSET_VSEC + *f_pos + i;
+ pci_read_config_byte(cvp_dev.pci_dev, byte_offset, &out_buf[i]);
+ }
+
+ if (copy_to_user(buf, out_buf, count)) {
+ ret_val = -EFAULT;
+ } else {
+ *f_pos += count;
+ ret_val = count;
+ }
+
+ kfree(out_buf);
+ return ret_val;
+}
+
+ssize_t altera_cvp_write(struct file * filp, const char __user *buf, size_t count, loff_t *f_pos)
+{
+ ssize_t ret_val; /* number of bytes successfully transferred */
+ u8 *send_buf;
+ size_t send_buf_size;
+
+ send_buf_size = count + cvp_dev.remain_size;
+ send_buf = kmalloc(send_buf_size, GFP_KERNEL);
+
+ if (cvp_dev.remain_size > 0)
+ memcpy(send_buf, cvp_dev.remain, cvp_dev.remain_size);
+
+ if (copy_from_user(send_buf + cvp_dev.remain_size, buf, count)) {
+ ret_val = -EFAULT;
+ goto exit;
+ }
+
+ /* calculate new remainder */
+ cvp_dev.remain_size = send_buf_size % 4;
+
+ /* save bytes in new remainder in cvp_dev */
+ if (cvp_dev.remain_size > 0)
+ memcpy(cvp_dev.remain,
+ send_buf + (send_buf_size - cvp_dev.remain_size),
+ cvp_dev.remain_size);
+
+ if (altera_cvp_send_data((u32 *)send_buf, send_buf_size / 4)) {
+ ret_val = -EAGAIN;
+ goto exit;
+ }
+
+ *f_pos += count;
+ ret_val = count;
+exit:
+ kfree (send_buf);
+ return ret_val;
+}
+
+struct file_operations altera_cvp_fops = {
+ .owner = THIS_MODULE,
+ .llseek = no_llseek,
+ .read = altera_cvp_read,
+ .write = altera_cvp_write,
+ .open = altera_cvp_open,
+ .release = altera_cvp_release,
+};
+
+/* PCI functions */
+
+static int altera_cvp_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+ int rc = 0;
+
+ if((dev->vendor == vid) && (dev->device == did)) {
+ rc = pci_enable_device(dev);
+ if (rc) {
+ dev_err(&dev->dev, "pci_enable device() failed\n");
+ return rc;
+ }
+ dev_info(&dev->dev, "Found and enabled PCI device with "
+ "VID 0x%04X, DID 0x%04X\n", vid, did);
+
+ rc = pci_request_regions(dev, ALTERA_CVP_DRIVER_NAME);
+ if (rc) {
+ dev_err(&dev->dev, "pci_request_regions() failed\n");
+ return rc;
+ }
+
+ cvp_dev.wr_addr = pci_iomap(dev, 0, 0);
+
+ cvp_dev.pci_dev = dev; /* store pointer for PCI API calls */
+ return 0;
+ } else {
+ dev_err(&dev->dev, "This PCI device does not match "
+ "VID 0x%04X, DID 0x%04X\n", vid, did);
+ return -ENODEV;
+ }
+}
+
+static void altera_cvp_remove(struct pci_dev *dev)
+{
+ pci_iounmap(dev, cvp_dev.wr_addr);
+ pci_disable_device(dev);
+ pci_release_regions(dev);
+}
+
+/* PCIe HIP on FPGA can have any combination of IDs based on design settings */
+static struct pci_device_id pci_ids[] = {
+ { PCI_DEVICE(PCI_ANY_ID, PCI_ANY_ID), },
+ { 0, }
+};
+MODULE_DEVICE_TABLE(pci, pci_ids);
+
+static struct pci_driver cvp_driver = {
+ .name = ALTERA_CVP_DRIVER_NAME,
+ .id_table = pci_ids,
+ .probe = altera_cvp_probe,
+ .remove = altera_cvp_remove,
+};
+
+/* Module functions */
+
+static int __init altera_cvp_init(void)
+{
+ int rc = 0;
+ dev_t dev;
+
+ rc = alloc_chrdev_region(&dev, 0, 1, ALTERA_CVP_DEVFILE);
+ if (rc) {
+ printk(KERN_ERR "%s: Allocation of char device numbers "
+ "failed\n", ALTERA_CVP_DRIVER_NAME);
+ goto exit;
+ }
+
+ cvp_dev.dev = dev; /* store major and minor numbers for char device */
+ altera_cvp_major = MAJOR(dev);
+
+ rc = pci_register_driver(&cvp_driver);
+ if (rc) {
+ printk(KERN_ERR "%s: PCI driver registration failed\n",
+ ALTERA_CVP_DRIVER_NAME);
+ unregister_chrdev_region(MKDEV(altera_cvp_major, 0), 1);
+ goto exit;
+ }
+
+ cdev_init(&cvp_dev.cdev, &altera_cvp_fops);
+ cvp_dev.cdev.owner = THIS_MODULE;
+ rc = cdev_add(&cvp_dev.cdev, dev, 1);
+ if (rc) {
+ printk(KERN_ERR "%s: Unable to add char device to the "
+ "system\n", ALTERA_CVP_DRIVER_NAME);
+ pci_unregister_driver(&cvp_driver);
+ goto exit;
+ }
+
+ cvp_dev.remain_size = 0;
+ atomic_set(&cvp_dev.is_available, 1);
+ printk("successfully init Altera CVP with major %d\n", altera_cvp_major);
+exit:
+ return rc;
+}
+
+static void __exit altera_cvp_exit(void)
+{
+ cdev_del(&cvp_dev.cdev);
+ unregister_chrdev_region(MKDEV(altera_cvp_major, 0), 1);
+ pci_unregister_driver(&cvp_driver);
+}
+
+module_init(altera_cvp_init);
+module_exit(altera_cvp_exit);
+
+MODULE_AUTHOR("Andres Cassinelli <aca...@al...>");
+MODULE_DESCRIPTION("Configuration driver for Altera CvP-capable FPGAs");
+MODULE_VERSION(ALTERA_CVP_DRIVER_VERSION);
+MODULE_LICENSE("Dual BSD/GPL");
+
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-11 12:23:25
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via d42cb157071e99f1d104e39143e882f875ccdba0 (commit)
from 372197f597a4d2affbb2d8539c69cc88cafc7e96 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d42cb157071e99f1d104e39143e882f875ccdba0
Author: Eric Jarrige <eri...@ar...>
Date: Wed Feb 11 13:22:45 2015 +0100
[BUILDROOT] 2013.11: fix network options to work with recent U-Boot release
-----------------------------------------------------------------------
Summary of changes:
...ot-Fix_config_options_with_newer_releases.patch | 53 ++++++++++++++++++++
1 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644 patches/buildroot/2013.11/051-U-Boot-Fix_config_options_with_newer_releases.patch
diff --git a/patches/buildroot/2013.11/051-U-Boot-Fix_config_options_with_newer_releases.patch b/patches/buildroot/2013.11/051-U-Boot-Fix_config_options_with_newer_releases.patch
new file mode 100644
index 0000000..cabc8e0
--- /dev/null
+++ b/patches/buildroot/2013.11/051-U-Boot-Fix_config_options_with_newer_releases.patch
@@ -0,0 +1,53 @@
+U-Boot: Quick fix network options to work with recent versions of U-Boot.
+To be replaced ASAP by any better solution...
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+--- a/boot/uboot/uboot.mk
++++ b/boot/uboot/uboot.mk
+@@ -63,16 +63,16 @@ UBOOT_MAKE_OPTS += \
+ CROSS_COMPILE="$(CCACHE) $(TARGET_CROSS)" \
+ ARCH=$(UBOOT_ARCH)
+
+-# Helper function to fill the U-Boot config.h file.
++# Helper function to fill U-Boot configs/$(UBOOT_BOARD_NAME).h file.
+ # Argument 1: option name
+ # Argument 2: option value
+ # If the option value is empty, this function does nothing.
+ define insert_define
+ $(if $(call qstrip,$(2)),
+- @echo "#ifdef $(strip $(1))" >> $(@D)/include/config.h
+- @echo "#undef $(strip $(1))" >> $(@D)/include/config.h
+- @echo "#endif" >> $(@D)/include/config.h
+- @echo '#define $(strip $(1)) $(call qstrip,$(2))' >> $(@D)/include/config.h)
++ @echo "#ifdef $(strip $(1))" >> $(@D)/include/configs/$(UBOOT_BOARD_NAME).h
++ @echo "#undef $(strip $(1))" >> $(@D)/include/configs/$(UBOOT_BOARD_NAME).h
++ @echo "#endif" >> $(@D)/include/configs/$(UBOOT_BOARD_NAME).h
++ @echo '#define $(strip $(1)) $(call qstrip,$(2))' >> $(@D)/include/configs/$(UBOOT_BOARD_NAME).h)
+ endef
+
+ ifneq ($(call qstrip,$(BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR)),)
+@@ -91,10 +91,10 @@ define UBOOT_CONFIGURE_CMDS
+ $(TARGET_CONFIGURE_OPTS) $(UBOOT_CONFIGURE_OPTS) \
+ $(MAKE) -C $(@D) $(UBOOT_MAKE_OPTS) \
+ $(UBOOT_BOARD_NAME)_config
+- @echo >> $(@D)/include/config.h
+- @echo "/* Add a wrapper around the values Buildroot sets. */" >> $(@D)/include/config.h
+- @echo "#ifndef __BR2_ADDED_CONFIG_H" >> $(@D)/include/config.h
+- @echo "#define __BR2_ADDED_CONFIG_H" >> $(@D)/include/config.h
++ @echo >> $(@D)/include/configs/$(UBOOT_BOARD_NAME).h
++ @echo "/* Add a wrapper around the values Buildroot sets. */" >> $(@D)/include/configs/$(UBOOT_BOARD_NAME).h
++ @echo "#ifndef __BR2_ADDED_CONFIG_H" >> $(@D)/include/configs/$(UBOOT_BOARD_NAME).h
++ @echo "#define __BR2_ADDED_CONFIG_H" >> $(@D)/include/configs/$(UBOOT_BOARD_NAME).h
+ $(call insert_define,DATE,$(DATE))
+ $(call insert_define,CONFIG_LOAD_SCRIPTS,1)
+ $(call insert_define,CONFIG_IPADDR,$(BR2_TARGET_UBOOT_IPADDR))
+@@ -103,7 +103,7 @@ define UBOOT_CONFIGURE_CMDS
+ $(call insert_define,CONFIG_SERVERIP,$(BR2_TARGET_UBOOT_SERVERIP))
+ $(call insert_define,CONFIG_ETHADDR,$(BR2_TARGET_UBOOT_ETHADDR))
+ $(call insert_define,CONFIG_ETH1ADDR,$(BR2_TARGET_UBOOT_ETH1ADDR))
+- @echo "#endif /* __BR2_ADDED_CONFIG_H */" >> $(@D)/include/config.h
++ @echo "#endif /* __BR2_ADDED_CONFIG_H */" >> $(@D)/include/configs/$(UBOOT_BOARD_NAME).h
+ endef
+
+ define UBOOT_BUILD_CMDS
hooks/post-receive
--
armadeus
|
|
From: Sébastien S. <ss...@us...> - 2015-02-10 10:37:30
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 372197f597a4d2affbb2d8539c69cc88cafc7e96 (commit)
from b62985620bc908511dc5ed26b0c2bbd851ec2601 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 372197f597a4d2affbb2d8539c69cc88cafc7e96
Author: Sébastien Szymanski <seb...@ar...>
Date: Tue Feb 10 11:40:59 2015 +0100
[UBOOT] 2014.07: apf6: don't use env vars in bootstrap
-----------------------------------------------------------------------
Summary of changes:
.../506-apf6-in_bootstrap_dont_use_env_vars.patch | 30 ++++++++++++++++++++
software/uboot_recover/apf6-u-boot.img | Bin 372844 -> 366848 bytes
software/uboot_recover/apf6-u-boot.spl | Bin 39936 -> 39936 bytes
software/uboot_recover/apf6_recovery.py | 2 -
4 files changed, 30 insertions(+), 2 deletions(-)
create mode 100644 patches/u-boot/2014.07/506-apf6-in_bootstrap_dont_use_env_vars.patch
diff --git a/patches/u-boot/2014.07/506-apf6-in_bootstrap_dont_use_env_vars.patch b/patches/u-boot/2014.07/506-apf6-in_bootstrap_dont_use_env_vars.patch
new file mode 100644
index 0000000..6268851
--- /dev/null
+++ b/patches/u-boot/2014.07/506-apf6-in_bootstrap_dont_use_env_vars.patch
@@ -0,0 +1,30 @@
+Index: uboot-2014.07/board/armadeus/apf6/apf6.c
+===================================================================
+--- uboot-2014.07.orig/board/armadeus/apf6/apf6.c
++++ uboot-2014.07/board/armadeus/apf6/apf6.c
+@@ -18,6 +18,7 @@
+ #include <asm/imx-common/video.h>
+ #include <asm/io.h>
+ #include <common.h>
++#include <environment.h>
+ #include <fsl_esdhc.h>
+ #include <linux/ctype.h>
+ #include <miiphy.h>
+@@ -327,9 +328,17 @@ int board_late_init(void)
+ u_char *firmware_buffer =
+ (u_char *) (CONFIG_SYS_LOAD_ADDR + CONFIG_SYS_MONITOR_LEN);
+ size_t size = 0;
++ struct src *psrc = (struct src *)SRC_BASE_ADDR;
++ unsigned reg = readl(&psrc->sbmr2);
+
+ SETUP_IOMUX_PADS(usb_pads);
+
++ /* In bootstrap don't use the the env vars */
++ if (((reg & 0x3000000) >> 24) == 0x1) {
++ set_default_env(NULL);
++ setenv("preboot", "");
++ }
++
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ setenv("fdt_file", "imx6q-apf6dev.dtb");
+ else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
diff --git a/software/uboot_recover/apf6-u-boot.img b/software/uboot_recover/apf6-u-boot.img
index a1fd604..8f10bcc 100644
Binary files a/software/uboot_recover/apf6-u-boot.img and b/software/uboot_recover/apf6-u-boot.img differ
diff --git a/software/uboot_recover/apf6-u-boot.spl b/software/uboot_recover/apf6-u-boot.spl
index 4a72baf..bb29280 100644
Binary files a/software/uboot_recover/apf6-u-boot.spl and b/software/uboot_recover/apf6-u-boot.spl differ
diff --git a/software/uboot_recover/apf6_recovery.py b/software/uboot_recover/apf6_recovery.py
index 4db47fc..bcdc6ee 100644
--- a/software/uboot_recover/apf6_recovery.py
+++ b/software/uboot_recover/apf6_recovery.py
@@ -133,8 +133,6 @@ if __name__ == "__main__":
uboot.waitForPrompt()
- uboot.resetEnv(False)
-
uboot.startYModem()
subprocess.check_call(SERIAL_DOWNLOAD_APP + " -k " + U_BOOT_SPL + " > " + port + " < " + port, shell=True)
uboot.waitForPrompt()
hooks/post-receive
--
armadeus
|
|
From: Sébastien S. <ss...@us...> - 2015-02-09 13:09:01
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via b62985620bc908511dc5ed26b0c2bbd851ec2601 (commit)
from 6d6a799a4d0266ea730927cd269f96e67be56031 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit b62985620bc908511dc5ed26b0c2bbd851ec2601
Author: Sébastien Szymanski <seb...@ar...>
Date: Mon Feb 9 14:13:42 2015 +0100
[LINUX] 3.19: move to 3.19
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf6_defconfig | 2 +-
.../armadeus/apf27/apf27-linux-3.19-rc5.config | 1 -
.../armadeus/apf28/apf28-linux-3.19-rc5.config | 1 -
.../armadeus/apf51/apf51-linux-3.19-rc5.config | 1 -
.../armadeus/apf6/apf6-linux-3.19-rc5.config | 1 -
patches/linux/3.19-rc5 | 1 -
6 files changed, 1 insertions(+), 6 deletions(-)
delete mode 120000 buildroot/target/device/armadeus/apf27/apf27-linux-3.19-rc5.config
delete mode 120000 buildroot/target/device/armadeus/apf28/apf28-linux-3.19-rc5.config
delete mode 120000 buildroot/target/device/armadeus/apf51/apf51-linux-3.19-rc5.config
delete mode 120000 buildroot/target/device/armadeus/apf6/apf6-linux-3.19-rc5.config
delete mode 120000 patches/linux/3.19-rc5
diff --git a/buildroot/configs/apf6_defconfig b/buildroot/configs/apf6_defconfig
index 7eb4867..55dc02a 100644
--- a/buildroot/configs/apf6_defconfig
+++ b/buildroot/configs/apf6_defconfig
@@ -23,7 +23,7 @@ BR2_TARGET_ARMADEUS_NR_SDRAM="2"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="512"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.19-rc5"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.19"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.19-rc5.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.19-rc5.config
deleted file mode 120000
index 449c4aa..0000000
--- a/buildroot/target/device/armadeus/apf27/apf27-linux-3.19-rc5.config
+++ /dev/null
@@ -1 +0,0 @@
-apf27-linux-3.19.config
\ No newline at end of file
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.19-rc5.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.19-rc5.config
deleted file mode 120000
index 05a3db3..0000000
--- a/buildroot/target/device/armadeus/apf28/apf28-linux-3.19-rc5.config
+++ /dev/null
@@ -1 +0,0 @@
-apf28-linux-3.19.config
\ No newline at end of file
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.19-rc5.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.19-rc5.config
deleted file mode 120000
index 90d7f8f..0000000
--- a/buildroot/target/device/armadeus/apf51/apf51-linux-3.19-rc5.config
+++ /dev/null
@@ -1 +0,0 @@
-apf51-linux-3.19.config
\ No newline at end of file
diff --git a/buildroot/target/device/armadeus/apf6/apf6-linux-3.19-rc5.config b/buildroot/target/device/armadeus/apf6/apf6-linux-3.19-rc5.config
deleted file mode 120000
index a5203ff..0000000
--- a/buildroot/target/device/armadeus/apf6/apf6-linux-3.19-rc5.config
+++ /dev/null
@@ -1 +0,0 @@
-apf6-linux-3.19.config
\ No newline at end of file
diff --git a/patches/linux/3.19-rc5 b/patches/linux/3.19-rc5
deleted file mode 120000
index 318956c..0000000
--- a/patches/linux/3.19-rc5
+++ /dev/null
@@ -1 +0,0 @@
-3.19
\ No newline at end of file
hooks/post-receive
--
armadeus
|
|
From: Sébastien S. <ss...@us...> - 2015-02-06 14:32:28
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 6d6a799a4d0266ea730927cd269f96e67be56031 (commit)
from 86189cb4de4616c2c0ae7915e6d5332449e81381 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 6d6a799a4d0266ea730927cd269f96e67be56031
Author: Sébastien Szymanski <seb...@ar...>
Date: Fri Feb 6 15:34:19 2015 +0100
[LINUX] APF6 (legacy): update
- bump to linux 3.10.31
- rework and update device trees
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf6legacy_defconfig | 2 +-
.../armadeus/apf6/apf6legacy-linux-3.10.config | 1 +
...rmadeus-add-apf6q-and-apf6dl-device-trees.patch | 692 ++++++++++++--------
3 files changed, 428 insertions(+), 267 deletions(-)
diff --git a/buildroot/configs/apf6legacy_defconfig b/buildroot/configs/apf6legacy_defconfig
index 6c32fcc..55bb54d 100644
--- a/buildroot/configs/apf6legacy_defconfig
+++ b/buildroot/configs/apf6legacy_defconfig
@@ -23,7 +23,7 @@ BR2_TARGET_ARMADEUS_SDRAM_SIZE="512"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_GIT=y
BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/wandboard-org/linux.git"
-BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="wandboard_imx_3.10.17_1.0.0_ga"
+BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="wandboard_imx_3.10.31_1.1.0_beta2"
BR2_LINUX_KERNEL_PATCH="../patches/linux/3.10.mx6_legacy"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/apf6legacy-linux-3.10.config"
diff --git a/buildroot/target/device/armadeus/apf6/apf6legacy-linux-3.10.config b/buildroot/target/device/armadeus/apf6/apf6legacy-linux-3.10.config
index b27c252..2abc708 100644
--- a/buildroot/target/device/armadeus/apf6/apf6legacy-linux-3.10.config
+++ b/buildroot/target/device/armadeus/apf6/apf6legacy-linux-3.10.config
@@ -19,6 +19,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_ARCH_MXC=y
CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y
+CONFIG_SOC_IMX6SX=y
CONFIG_WAND_RFKILL=y
CONFIG_SMP=y
CONFIG_VMSPLIT_2G=y
diff --git a/patches/linux/3.10.mx6_legacy/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch b/patches/linux/3.10.mx6_legacy/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
index e6d8bd4..bfb44d5 100644
--- a/patches/linux/3.10.mx6_legacy/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
+++ b/patches/linux/3.10.mx6_legacy/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
@@ -1,10 +1,10 @@
-Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6q-apf6dev.dts
+Index: linux-wandboard_imx_3.10.31_1.1.0_beta2/arch/arm/boot/dts/imx6q-apf6dev.dts
===================================================================
--- /dev/null
-+++ linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6q-apf6dev.dts
++++ linux-wandboard_imx_3.10.31_1.1.0_beta2/arch/arm/boot/dts/imx6q-apf6dev.dts
@@ -0,0 +1,30 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -16,8 +16,8 @@ Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6q-apf6dev.dts
+
+/dts-v1/;
+#include "imx6q.dtsi"
-+#include "imx6q-apf6.dtsi"
-+#include "imx6q-apf6dev.dtsi"
++#include "imx6qdl-apf6.dtsi"
++#include "imx6qdl-apf6dev.dtsi"
+
+/ {
+ model = "Armadeus APF6 i.MX6 Quad / Dual Module on APF6Dev Board";
@@ -33,13 +33,13 @@ Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6q-apf6dev.dts
+ status = "okay";
+};
+*/
-Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+Index: linux-wandboard_imx_3.10.31_1.1.0_beta2/arch/arm/boot/dts/imx6qdl-apf6.dtsi
===================================================================
--- /dev/null
-+++ linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl-apf6.dtsi
-@@ -0,0 +1,56 @@
++++ linux-wandboard_imx_3.10.31_1.1.0_beta2/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+@@ -0,0 +1,132 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -49,11 +49,13 @@ Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ *
+ */
+
++#include <dt-bindings/interrupt-controller/irq.h>
++
+/ {
+ wlan {
+ compatible = "ti,wilink6";
+ interrupt-parent = <&gpio2>;
-+ interrupts = <10 0x4>; /* gpio line 43, high level triggered */
++ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* gpio line 42, high level triggered */
+ clocks = <&refclock>, <&tcxoclock>;
+ clock-names = "refclock", "tcxoclock";
+
@@ -71,36 +73,110 @@ Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ };
+};
+
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet>;
++ phy-mode = "rgmii";
++ //phy-reset-duration = <10>;
++ //phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
+/* Bluetooth */
+&uart2 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart2_3>;
++ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* Wi-Fi */
-+/*
+&usdhc1 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc1_2>;
++ pinctrl-0 = <&pinctrl_usdhc1>;
++ non-removable;
+ status = "okay";
+};
-+*/
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc3_1>;
-+ //non-removable;
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ bus-width = <8>;
++ no-1-8-v;
++ non-removable;
+ status = "okay";
+};
-Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
++
++&iomuxc {
++ apf6 {
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
++ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x80000000
++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
++ >;
++ };
++
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
++ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* BT_EN */
++ >;
++ };
++
++ pinctrl_usdhc1: usdhc1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
++ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
++ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
++ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
++ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
++ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
++ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000 /* WL_EN */
++ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x80000000 /* WL_IRQ */
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
++ >;
++ };
++ };
++};
+Index: linux-wandboard_imx_3.10.31_1.1.0_beta2/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
===================================================================
--- /dev/null
-+++ linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
-@@ -0,0 +1,181 @@
++++ linux-wandboard_imx_3.10.31_1.1.0_beta2/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+@@ -0,0 +1,486 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -115,9 +191,82 @@ Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl-apf6dev.dt
+ mxcfb0 = &mxcfb1;
+ };
+
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_keys>;
++
++ user-button {
++ label = "User button";
++ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
++ linux,code = <0x100>;
++ gpio-key,wakeup;
++ };
++ };
++
++ gpio-leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_leds>;
++
++ user-led {
++ label = "User LED";
++ gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ default-state = "on";
++ };
++ };
++
++ mxcfb1: fb@0 {
++ compatible = "fsl,mxc_sdc_fb";
++ disp_dev = "hdmi";
++ interface_pix_fmt = "RGB24";
++ mode_str ="1920x1080M@60";
++ default_bpp = <24>;
++ int_clk = <0>;
++ late_init = <0>;
++ status = "okay";
++ };
++
++ sound {
++ compatible = "fsl,imx6-armadeus-sgtl5000",
++ "fsl,imx-audio-sgtl5000";
++ model = "imx6-armadeus-sgtl5000";
++ cpu-dai = <&ssi1>;
++ audio-codec = <&codec>;
++ audio-routing =
++ "MIC_IN", "Mic Jack",
++ "Mic Jack", "Mic Bias",
++ "Headphone Jack", "HP_OUT";
++ mux-int-port = <1>;
++ mux-ext-port = <3>;
++ };
++
++ sound-spdif {
++ compatible = "fsl,imx-audio-spdif";
++ model = "imx-spdif";
++ spdif-controller = <&spdif>;
++ spdif-out;
++ };
++
++ sound-hdmi {
++ compatible = "fsl,imx6q-audio-hdmi",
++ "fsl,imx-audio-hdmi";
++ model = "imx-audio-hdmi";
++ hdmi-controller = <&hdmi_audio>;
++ };
++
+ regulators {
+ compatible = "simple-bus";
+
++ reg_1p8v: 1p8v {
++ compatible = "regulator-fixed";
++ regulator-name = "1P8V";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ };
++
+ reg_2p5v: 2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
@@ -143,37 +292,44 @@ Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl-apf6dev.dt
+ };
+ };
+
-+ leds {
-+ compatible = "gpio-leds";
++ v4l2_cap_0 {
++ compatible = "fsl,imx6q-v4l2-capture";
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk_source = <0>;
++ status = "okay";
++ };
+
-+ user-led {
-+ label = "User LED";
-+ gpios = <&gpio7 12 0>;
-+ linux,default-trigger = "heartbeat";
-+ default-state = "on";
-+ };
++ v4l2_out {
++ compatible = "fsl,mxc_v4l2_output";
++ status = "okay";
+ };
++};
+
-+ keys {
-+ compatible = "gpio-keys";
++&audmux {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_audmux>;
++ status = "okay";
++};
+
-+ user-button {
-+ label = "User button";
-+ gpios = <&gpio1 9 0>;
-+ linux,code = <100>;
-+ };
-+ };
++&flexcan2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan2>;
++ status = "okay";
++};
+
-+ mxcfb1: fb@0 {
-+ compatible = "fsl,mxc_sdc_fb";
-+ disp_dev = "hdmi";
-+ interface_pix_fmt = "RGB24";
-+ mode_str ="1920x1080M@60";
-+ default_bpp = <24>;
-+ int_clk = <0>;
-+ late_init = <0>;
-+ status = "okay";
-+ };
++&ecspi1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi1>;
++ fsl,spi-num-chipselects = <3>;
++ cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>,
++ <&gpio4 10 GPIO_ACTIVE_HIGH>,
++ <&gpio4 11 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&hdmi_audio {
++ status = "okay";
+};
+
+&hdmi_core {
@@ -188,198 +344,278 @@ Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl-apf6dev.dt
+ status = "okay";
+};
+
-+&i2c3 {
-+ clock-frequency = <100000>;
++&i2c1 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c3_1>;
++ pinctrl-0 = <&pinctrl_i2c1>;
++ clock-frequency = <100000>;
+ status = "okay";
+
-+ hdmi: edid@50 {
-+ compatible = "fsl,imx6-hdmi-i2c";
-+ reg = <0x50>;
++ ov5640_mipi: ov5640_mipi@3c {
++ compatible = "ovti,ov5640_mipi";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_camera_ov5640>;
++ reg = <0x3c>;
++ clocks = <&clks 201>;
++ clock-names = "csi_mclk";
++ pwn-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
++ rst-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>;
++ DOVDD-supply = <®_1p8v>;
++ AVDD-supply = <®_2p5v>;
++ DVDD-supply = <®_1p8v>;
++ ipu_id = <0>;
++ csi_id = <0>;
++ mclk = <24000000>;
++ mclk_source = <0>;
+ };
+};
+
-+/*
-+&i2c1 {
-+ clock-frequency = <100000>;
++&i2c2 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c1_1>;
++ pinctrl-0 = <&pinctrl_i2c2>;
++ clock-frequency = <100000>;
+ status = "okay";
++
++ codec: sgtl5000@0a {
++ compatible = "fsl,sgtl5000";
++ reg = <0x0a>;
++ clocks = <&clks 201>;
++ VDDA-supply = <®_3p3v>;
++ VDDIO-supply = <®_3p3v>;
++ };
+};
+
-+&i2c2 {
-+ clock-frequency = <100000>;
++&i2c3 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c2_2>;
++ pinctrl-0 = <&pinctrl_i2c3>;
++ clock-frequency = <400000>;
+ status = "okay";
++
++ hdmi: edid@50 {
++ compatible = "fsl,imx6-hdmi-i2c";
++ reg = <0x50>;
++ };
+};
-+*/
+
-+&fec {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_enet_4>;
-+ phy-mode = "rgmii";
++&mipi_csi {
++ ipu_id = <0>;
++ csi_id = <0>;
++ v_channel = <0>;
++ lanes = <2>;
+ status = "okay";
+};
+
+/*
+&pcie {
-+ reset-gpio = <&gpio6 2 0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcie>;
++ reset-gpio = <&gpio6 2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+*/
-+/*
++
+&pwm3 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_pwm3_1>;
++ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
-+*/
++
++&spdif {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_spdif>;
++ status = "okay";
++};
++
++&ssi1 {
++ fsl,mode = "i2s-slave";
++ status = "okay";
++};
++
+/* GPS */
+&uart1 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart1_1>;
++ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+/* GSM */
+&uart3 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart3_3>;
++ pinctrl-0 = <&pinctrl_uart3 &pinctrl_gsm>;
++ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+/* console */
+&uart4 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart4_2>;
++ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
++ dr_mode = "host";
++ phy_type = "utmi";
+ status = "okay";
+};
+
+&usbotg {
-+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usbotg_1>;
-+ disable-over-current;
-+ dr_mode = "peripheral";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ vbus-supply = <®_usb_otg_vbus>;
++ dr_mode = "otg";
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc2_2>;
++ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
-+ vmmc-supply = <®_3p3v>;
-+ cd-gpios = <&gpio1 2 0>;
++ cd-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
-Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6dl-apf6dev.dts
-===================================================================
---- /dev/null
-+++ linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6dl-apf6dev.dts
-@@ -0,0 +1,24 @@
-+/*
-+ * Copyright 2014 Armadeus Systems
-+ *
-+ * Author: Armadeus Systems <su...@ar...>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
++&iomuxc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpios>;
+
-+/dts-v1/;
-+#include "imx6dl.dtsi"
-+#include "imx6dl-apf6.dtsi"
-+#include "imx6dl-apf6dev.dtsi"
++ apf6dev {
++ pinctrl_audmux: audmuxgrp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
++ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
++ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
++ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
++ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
++ >;
++ };
+
-+/ {
-+ model = "Armadeus APF6 i.MX6 Dual Lite Module on APF6Dev Board";
-+ compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl";
++ pinctrl_camera_ov5640: cameragrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x1b0b0 /* CSI_MCLK */
++ MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x80000000
++ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000
++ >;
++ };
+
-+ memory {
-+ reg = <0x10000000 0x40000000>;
-+ };
-+};
-Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6dl-apf6.dtsi
-===================================================================
---- /dev/null
-+++ linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6dl-apf6.dtsi
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2014 Armadeus Systems
-+ *
-+ * Author: Armadeus Systems <su...@ar...>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
++ pinctrl_ecspi1: ecspi1grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
++ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
++ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
++ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x80000000
++ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000
++ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000
++ >;
++ };
+
-+#include "imx6qdl-apf6.dtsi"
++ pinctrl_flexcan2: flexcan2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
++ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
++ >;
++ };
+
-+&iomuxc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hog>;
++ pinctrl_gpio_keys: gpiokeysgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
++ >;
++ };
++ pinctrl_gpio_leds: gpioledsgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
++ >;
++ };
+
-+ hog {
-+ pinctrl_hog: hoggrp {
++ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x80000000 /* WL_IRQ */
++ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x80000000
++ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x80000000
++ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x80000000
++ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
++ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x80000000
++ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000
++ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000
++ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000
+ >;
+ };
+
-+ pinctrl_uart2_3: uart2grp-3 {
++ pinctrl_gsm: gsmgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* GSM_POKIN */
++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* GSM_PWR_EN */
+ >;
+ };
-+ };
-+};
-Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6dl-apf6dev.dtsi
-===================================================================
---- /dev/null
-+++ linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6dl-apf6dev.dtsi
-@@ -0,0 +1,43 @@
-+/*
-+ * Copyright 2014 Armadeus Systems
-+ *
-+ * Author: Armadeus Systems <su...@ar...>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
+
-+#include "imx6qdl-apf6dev.dtsi"
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
++ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
++ >;
++ };
+
-+&iomuxc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hog>;
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
++ >;
++ };
++
++ pinctrl_ipu1_disp1: ipu1disp1grp {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
++ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
++ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
++ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
++ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
++ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
++ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
++ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
++ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
++ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
++ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
++ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
++ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
++ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
++ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
++ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
++ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
++ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
++ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
++ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
++ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
++ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
++ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
++ >;
++ };
+
-+ hog {
-+ pinctrl_hog: hoggrp {
++ pinctrl_pcie: pciegrp {
+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
-+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
+ MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x80000000
+ >;
+ };
+
-+ pinctrl_uart3_3: uart3grp-3 {
++ pinctrl_pwm3: pwm3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
@@ -388,60 +624,50 @@ Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6dl-apf6dev.dts
+ >;
+ };
+
-+ pinctrl_uart4_2: uart4grp-2 {
++ pinctrl_uart4: uart4grp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
+ >;
+ };
-+ };
-+};
-Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6q-apf6.dtsi
-===================================================================
---- /dev/null
-+++ linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6q-apf6.dtsi
-@@ -0,0 +1,34 @@
-+/*
-+ * Copyright 2014 Armadeus Systems
-+ *
-+ * Author: Armadeus Systems <su...@ar...>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
+
-+#include "imx6qdl-apf6.dtsi"
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ >;
++ };
+
-+&iomuxc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hog>;
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ >;
++ };
+
-+ hog {
-+ pinctrl_hog: hoggrp {
++ pinctrl_spdif: spdifgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x80000000 /* WL_IRQ */
++ MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0
+ >;
+ };
+
-+ pinctrl_uart2_3: uart2grp-3 {
++ pinctrl_touchscreen: touchscreengrp {
+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x80000000
+ >;
+ };
+ };
+};
-Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6q-apf6dev.dtsi
+Index: linux-wandboard_imx_3.10.31_1.1.0_beta2/arch/arm/boot/dts/imx6dl-apf6dev.dts
===================================================================
--- /dev/null
-+++ linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6q-apf6dev.dtsi
-@@ -0,0 +1,43 @@
++++ linux-wandboard_imx_3.10.31_1.1.0_beta2/arch/arm/boot/dts/imx6dl-apf6dev.dts
+@@ -0,0 +1,24 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -451,82 +677,16 @@ Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6q-apf6dev.dtsi
+ *
+ */
+
++/dts-v1/;
++#include "imx6dl.dtsi"
++#include "imx6qdl-apf6.dtsi"
+#include "imx6qdl-apf6dev.dtsi"
+
-+&iomuxc {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hog>;
-+
-+ hog {
-+ pinctrl_hog: hoggrp {
-+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
-+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
-+ MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x80000000
-+ >;
-+ };
-+
-+ pinctrl_uart3_3: uart3grp-3 {
-+ fsl,pins = <
-+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
-+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
-+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
-+ >;
-+ };
++/ {
++ model = "Armadeus APF6 i.MX6 Dual Lite Module on APF6Dev Board";
++ compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl";
+
-+ pinctrl_uart4_2: uart4grp-2 {
-+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
-+ >;
-+ };
++ memory {
++ reg = <0x10000000 0x40000000>;
+ };
+};
-Index: linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl.dtsi
-===================================================================
---- linux-wandboard_imx_3.10.17_1.0.0_ga.orig/arch/arm/boot/dts/imx6qdl.dtsi
-+++ linux-wandboard_imx_3.10.17_1.0.0_ga/arch/arm/boot/dts/imx6qdl.dtsi
-@@ -1166,6 +1166,29 @@
- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
- MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
-+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x80000000
-+ >;
-+ };
-+
-+ pinctrl_enet_4: enetgrp-4 {
-+ fsl,pins = <
-+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
-+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
-+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
-+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
-+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
-+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
-+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
-+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
-+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
-+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
-+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
-+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
-+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
-+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
-+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
-+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x80000000
-+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
- >;
- };
- };
-@@ -1354,6 +1377,12 @@
- MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
- >;
- };
-+ pinctrl_i2c3_5: i2c3grp-5 {
-+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
-+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
-+ >;
-+ };
- };
-
- ipu1 {
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-05 19:14:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 86189cb4de4616c2c0ae7915e6d5332449e81381 (commit)
from 57c92662fdba5844f216e2b523f92245b3879607 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 86189cb4de4616c2c0ae7915e6d5332449e81381
Author: Eric Jarrige <eri...@ar...>
Date: Thu Feb 5 20:14:09 2015 +0100
[UBOOT] 2015.01: add apf9328 U-Boot config
-----------------------------------------------------------------------
Summary of changes:
...8-u-boot-2014.04.h => apf9328-u-boot-2015.01.h} | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
copy buildroot/target/device/armadeus/apf9328/{apf9328-u-boot-2014.04.h => apf9328-u-boot-2015.01.h} (99%)
diff --git a/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2014.04.h b/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2015.01.h
similarity index 99%
copy from buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2014.04.h
copy to buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2015.01.h
index 1bd8cbf..56e4852 100644
--- a/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2014.04.h
+++ b/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2015.01.h
@@ -18,6 +18,7 @@
#define CONFIG_ARM920T /* this is an ARM920T CPU */
#define CONFIG_IMX /* in a Motorola MC9328MXL Chip */
#define CONFIG_MACH_TYPE 906 /* APF9328 */
+#define CONFIG_SYS_GENERIC_BOARD
/*
* Enable the call to miscellaneous platform dependent initialization.
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-05 19:13:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 57c92662fdba5844f216e2b523f92245b3879607 (commit)
from a31edb2a533dbd82d67a203ec919c6e23dc088b9 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 57c92662fdba5844f216e2b523f92245b3879607
Author: Eric Jarrige <eri...@ar...>
Date: Thu Feb 5 20:13:09 2015 +0100
[UBOOT] 2015.01: add apf27 U-Boot config
-----------------------------------------------------------------------
Summary of changes:
...f27-u-boot-2014.04.h => apf27-u-boot-2015.01.h} | 4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
copy buildroot/target/device/armadeus/apf27/{apf27-u-boot-2014.04.h => apf27-u-boot-2015.01.h} (99%)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2014.04.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2015.01.h
similarity index 99%
copy from buildroot/target/device/armadeus/apf27/apf27-u-boot-2014.04.h
copy to buildroot/target/device/armadeus/apf27/apf27-u-boot-2015.01.h
index 913fce3..22102f8 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2014.04.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2015.01.h
@@ -18,8 +18,7 @@
/*
* SoC configurations
*/
-#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */
-#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */
+#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */
#define CONFIG_MACH_TYPE 1698 /* APF27 */
#define CONFIG_SYS_GENERIC_BOARD
@@ -37,7 +36,6 @@
/*
* SPL
*/
-#define CONFIG_SPL
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
#define CONFIG_SPL_MAX_SIZE 2048
hooks/post-receive
--
armadeus
|
|
From: jorasse <jo...@us...> - 2015-02-05 19:08:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via a31edb2a533dbd82d67a203ec919c6e23dc088b9 (commit)
from ddaf6ce5fb03c550abd86d5959f833343653a826 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a31edb2a533dbd82d67a203ec919c6e23dc088b9
Author: Eric Jarrige <eri...@ar...>
Date: Thu Feb 5 20:07:51 2015 +0100
[UBOOT] 2015.01: add patchwork to support U-Boot 2015.01
-----------------------------------------------------------------------
Summary of changes:
...-restore-command-env-param-compatitbility.patch | 0
...02-arm-support-continuous-mmu-mem-mapping.patch | 97 ++
.../003-nand_large_file_download.patch} | 0
.../004-i2c-mxc-fix-mx51-i2c-declaration.patch | 40 +
patches/u-boot/2015.01/100-apf9328-Kconfig.patch | 26 +
.../101-mx1-timer.patch} | 0
.../u-boot/{2013.04 => 2015.01}/102-mx1-i2c.patch | 0
patches/u-boot/2015.01/103-apf9328.patch | 1185 +++++++++++++++++++
.../{2014.04 => 2015.01}/106-mx1-pllclk.patch | 0
.../107-mx1-pllclk-debug.patch | 0
.../u-boot/{2014.04 => 2015.01}/108-DM9000.patch | 0
.../300-imx27-fix_dcache_boot_issue.patch | 0
.../2015.01/301-apf27-support-boot-from-RAM.patch | 27 +
.../u-boot/2015.01/302-imx-nand-lock-unlock.patch | 98 ++
.../303-spartan.patch} | 0
.../304-apf27-misc-commands.patch} | 0
patches/u-boot/2015.01/400-imx51.patch | 522 +++++++++
patches/u-boot/2015.01/401-apf51.patch | 1025 +++++++++++++++++
patches/u-boot/2015.01/402-apf51-Kconfig.patch | 27 +
patches/u-boot/2015.01/403-apf51-nand-spl-NG.patch | 361 ++++++
patches/u-boot/2015.01/500-apf28-Kconfig.patch | 28 +
.../u-boot/2015.01/501-imx28-update-and-fix.patch | 60 +
patches/u-boot/2015.01/502-add-apf28.patch | 1208 ++++++++++++++++++++
patches/u-boot/2015.01/600-add-apf6.patch | 986 ++++++++++++++++
..._bootstrap_get_uboot_image_on_serial_port.patch | 17 +
25 files changed, 5707 insertions(+), 0 deletions(-)
copy patches/u-boot/{2014.07 => 2015.01}/001-restore-command-env-param-compatitbility.patch (100%)
create mode 100644 patches/u-boot/2015.01/002-arm-support-continuous-mmu-mem-mapping.patch
copy patches/u-boot/{2014.04/350-nand_large_file_download.patch => 2015.01/003-nand_large_file_download.patch} (100%)
create mode 100644 patches/u-boot/2015.01/004-i2c-mxc-fix-mx51-i2c-declaration.patch
create mode 100644 patches/u-boot/2015.01/100-apf9328-Kconfig.patch
copy patches/u-boot/{2014.04/111-mx1-timer.patch => 2015.01/101-mx1-timer.patch} (100%)
copy patches/u-boot/{2013.04 => 2015.01}/102-mx1-i2c.patch (100%)
create mode 100644 patches/u-boot/2015.01/103-apf9328.patch
copy patches/u-boot/{2014.04 => 2015.01}/106-mx1-pllclk.patch (100%)
copy patches/u-boot/{2014.04 => 2015.01}/107-mx1-pllclk-debug.patch (100%)
copy patches/u-boot/{2014.04 => 2015.01}/108-DM9000.patch (100%)
copy patches/u-boot/{2014.07 => 2015.01}/300-imx27-fix_dcache_boot_issue.patch (100%)
create mode 100644 patches/u-boot/2015.01/301-apf27-support-boot-from-RAM.patch
create mode 100644 patches/u-boot/2015.01/302-imx-nand-lock-unlock.patch
copy patches/u-boot/{2014.07/320-spartan.patch => 2015.01/303-spartan.patch} (100%)
copy patches/u-boot/{2014.04/340-apf27-misc-commands.patch => 2015.01/304-apf27-misc-commands.patch} (100%)
create mode 100644 patches/u-boot/2015.01/400-imx51.patch
create mode 100644 patches/u-boot/2015.01/401-apf51.patch
create mode 100644 patches/u-boot/2015.01/402-apf51-Kconfig.patch
create mode 100644 patches/u-boot/2015.01/403-apf51-nand-spl-NG.patch
create mode 100644 patches/u-boot/2015.01/500-apf28-Kconfig.patch
create mode 100644 patches/u-boot/2015.01/501-imx28-update-and-fix.patch
create mode 100644 patches/u-boot/2015.01/502-add-apf28.patch
create mode 100644 patches/u-boot/2015.01/600-add-apf6.patch
create mode 100644 patches/u-boot/2015.01/601-apf6-in_bootstrap_get_uboot_image_on_serial_port.patch
diff --git a/patches/u-boot/2014.07/001-restore-command-env-param-compatitbility.patch b/patches/u-boot/2015.01/001-restore-command-env-param-compatitbility.patch
similarity index 100%
copy from patches/u-boot/2014.07/001-restore-command-env-param-compatitbility.patch
copy to patches/u-boot/2015.01/001-restore-command-env-param-compatitbility.patch
diff --git a/patches/u-boot/2015.01/002-arm-support-continuous-mmu-mem-mapping.patch b/patches/u-boot/2015.01/002-arm-support-continuous-mmu-mem-mapping.patch
new file mode 100644
index 0000000..e462a7d
--- /dev/null
+++ b/patches/u-boot/2015.01/002-arm-support-continuous-mmu-mem-mapping.patch
@@ -0,0 +1,97 @@
+ARM: support continuous MMU memory mapping beside the regular identity mapping.
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
+index 939de10..25f0ff1 100644
+--- a/arch/arm/lib/cache-cp15.c
++++ b/arch/arm/lib/cache-cp15.c
+@@ -32,14 +32,14 @@ static void cp_delay (void)
+ asm volatile("" : : : "memory");
+ }
+
+-void set_section_dcache(int section, enum dcache_option option)
++void set_section_dcache(int section, int section_index, enum dcache_option option)
+ {
+ u32 *page_table = (u32 *)gd->arch.tlb_addr;
+ u32 value;
+
+ value = (section << MMU_SECTION_SHIFT) | (3 << 10);
+ value |= option;
+- page_table[section] = value;
++ page_table[section_index] = value;
+ }
+
+ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
+@@ -58,11 +58,11 @@ void mmu_set_region_dcache_behaviour(u32
+ debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
+ option);
+ for (upto = start; upto < end; upto++)
+- set_section_dcache(upto, option);
++ set_section_dcache(upto, upto, option);
+ mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+ }
+
+-__weak void dram_bank_mmu_setup(int bank)
++__weak void dram_bank_mmu_setup(int bank, int page_offset)
+ {
+ bd_t *bd = gd->bd;
+ int i;
+@@ -72,11 +72,11 @@ __weak void dram_bank_mmu_setup(int bank
+ i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
+ i++) {
+ #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+- set_section_dcache(i, DCACHE_WRITETHROUGH);
++ set_section_dcache(i, page_offset++, DCACHE_WRITETHROUGH);
+ #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+- set_section_dcache(i, DCACHE_WRITEALLOC);
++ set_section_dcache(i, page_offset++, DCACHE_WRITEALLOC);
+ #else
+- set_section_dcache(i, DCACHE_WRITEBACK);
++ set_section_dcache(i, page_offset++, DCACHE_WRITEBACK);
+ #endif
+ }
+ }
+@@ -86,14 +86,22 @@ static inline void mmu_setup(void)
+ {
+ int i;
+ u32 reg;
++ bd_t *bd = gd->bd;
++ int page_offset, continuity_offset;
+
+ arm_init_before_mmu();
+ /* Set up an identity-mapping for all 4GB, rw for everyone */
+ for (i = 0; i < 4096; i++)
+- set_section_dcache(i, DCACHE_OFF);
++ set_section_dcache(i, i, DCACHE_OFF);
+
++ continuity_offset = bd->bi_dram[0].start >> 20;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+- dram_bank_mmu_setup(i);
++ page_offset = (bd->bi_dram[i].start) >> 20;
++ /* direct identity mapping */
++ dram_bank_mmu_setup(i, page_offset);
++ /* secondary mapping to build a continous memory space */
++ dram_bank_mmu_setup(i, continuity_offset);
++ continuity_offset = (bd->bi_dram[i].start + bd->bi_dram[i].size) >> 20;
+ }
+
+ /* Copy the page table address to cp15 */
+diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
+--- a/arch/arm/include/asm/cache.h
++++ b/arch/arm/include/asm/cache.h
+@@ -27,12 +27,12 @@ static inline void invalidate_l2_cache(v
+
+ void l2_cache_enable(void);
+ void l2_cache_disable(void);
+-void set_section_dcache(int section, enum dcache_option option);
++void set_section_dcache(int section, int section_index, enum dcache_option option);
+
+ void arm_init_before_mmu(void);
+ void arm_init_domains(void);
+ void cpu_cache_initialization(void);
+-void dram_bank_mmu_setup(int bank);
++void dram_bank_mmu_setup(int bank, int page_offset);
+
+ #endif
+
diff --git a/patches/u-boot/2014.04/350-nand_large_file_download.patch b/patches/u-boot/2015.01/003-nand_large_file_download.patch
similarity index 100%
copy from patches/u-boot/2014.04/350-nand_large_file_download.patch
copy to patches/u-boot/2015.01/003-nand_large_file_download.patch
diff --git a/patches/u-boot/2015.01/004-i2c-mxc-fix-mx51-i2c-declaration.patch b/patches/u-boot/2015.01/004-i2c-mxc-fix-mx51-i2c-declaration.patch
new file mode 100644
index 0000000..04f72f5
--- /dev/null
+++ b/patches/u-boot/2015.01/004-i2c-mxc-fix-mx51-i2c-declaration.patch
@@ -0,0 +1,40 @@
+From 8cc45b2a0332154b9ef2deaa3085da90f4397da7 Mon Sep 17 00:00:00 2001
+From: Eric Jarrige <eri...@ar...>
+Date: Tue, 13 May 2014 14:22:51 +0200
+Subject: [PATCH 1/1] i2c: mxc: fix mx51 i2c declaration
+
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+ drivers/i2c/mxc_i2c.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
+index 595019b..a4280b4 100644
+--- a/drivers/i2c/mxc_i2c.c
++++ b/drivers/i2c/mxc_i2c.c
+@@ -410,8 +410,11 @@ static void * const i2c_bases[] = {
+ #elif defined(CONFIG_MX27)
+ (void *)IMX_I2C1_BASE,
+ (void *)IMX_I2C2_BASE
++#elif defined(CONFIG_MX51)
++ (void *)I2C1_BASE_ADDR,
++ (void *)I2C2_BASE_ADDR,
+ #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
+- defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
++ defined(CONFIG_MX53) || \
+ defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
+ (void *)I2C1_BASE_ADDR,
+ (void *)I2C2_BASE_ADDR,
+@@ -544,7 +547,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
+ CONFIG_SYS_MXC_I2C2_SPEED,
+ CONFIG_SYS_MXC_I2C2_SLAVE, 1)
+ #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
+- defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
++ defined(CONFIG_MX53) ||\
+ defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
+ U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
+ mxc_i2c_read, mxc_i2c_write,
+--
+1.7.9.5
+
diff --git a/patches/u-boot/2015.01/100-apf9328-Kconfig.patch b/patches/u-boot/2015.01/100-apf9328-Kconfig.patch
new file mode 100644
index 0000000..5db05c1
--- /dev/null
+++ b/patches/u-boot/2015.01/100-apf9328-Kconfig.patch
@@ -0,0 +1,26 @@
+apf9328: add apf9328 in Kconfig
+
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -260,6 +260,10 @@ config TARGET_APF27
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
++config TARGET_APF9328
++ bool "Support apf9328"
++ select CPU_ARM920T
++
+ config TARGET_IMX27LITE
+ bool "Support imx27lite"
+ select CPU_ARM926EJS
+@@ -852,6 +856,7 @@ source "board/Marvell/gplugd/Kconfig"
+ source "board/afeb9260/Kconfig"
+ source "board/altera/socfpga/Kconfig"
+ source "board/armadeus/apf27/Kconfig"
++source "board/armadeus/apf9328/Kconfig"
+ source "board/armltd/integrator/Kconfig"
+ source "board/armltd/vexpress/Kconfig"
+ source "board/armltd/vexpress64/Kconfig"
diff --git a/patches/u-boot/2014.04/111-mx1-timer.patch b/patches/u-boot/2015.01/101-mx1-timer.patch
similarity index 100%
copy from patches/u-boot/2014.04/111-mx1-timer.patch
copy to patches/u-boot/2015.01/101-mx1-timer.patch
diff --git a/patches/u-boot/2013.04/102-mx1-i2c.patch b/patches/u-boot/2015.01/102-mx1-i2c.patch
similarity index 100%
copy from patches/u-boot/2013.04/102-mx1-i2c.patch
copy to patches/u-boot/2015.01/102-mx1-i2c.patch
diff --git a/patches/u-boot/2015.01/103-apf9328.patch b/patches/u-boot/2015.01/103-apf9328.patch
new file mode 100644
index 0000000..0f9bdac
--- /dev/null
+++ b/patches/u-boot/2015.01/103-apf9328.patch
@@ -0,0 +1,1185 @@
+apf9328: Add Armadeus Project board APF9328
+
+Add Armadeus Project board APF9328
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Nicolas Colombain <nic...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Nicolas Colombain <nic...@ar...>
+---
+ board/armadeus/apf9328/Makefile | 51 ++++
+ board/armadeus/apf9328/apf9328.c | 106 +++++++
+ board/armadeus/apf9328/apf9328fpga.c | 100 +++++++
+ board/armadeus/apf9328/apf9328fpga.h | 31 ++
+ board/armadeus/apf9328/eeprom.c | 88 ++++++
+ board/armadeus/apf9328/fpga.c | 121 ++++++++
+ board/armadeus/apf9328/fpga.h | 30 ++
+ board/armadeus/apf9328/i2c.c | 276 +++++++++++++++++++
+ board/armadeus/apf9328/lowlevel_init.S | 469 ++++++++++++++++++++++++++++++++
+ 9 files changed, 1272 insertions(+), 0 deletions(-)
+ create mode 100644 board/armadeus/apf9328/Makefile
+ create mode 100644 board/armadeus/apf9328/apf9328.c
+ create mode 100644 board/armadeus/apf9328/apf9328fpga.c
+ create mode 100644 board/armadeus/apf9328/apf9328fpga.h
+ create mode 100644 board/armadeus/apf9328/eeprom.c
+ create mode 100644 board/armadeus/apf9328/fpga.c
+ create mode 100644 board/armadeus/apf9328/fpga.h
+ create mode 100644 board/armadeus/apf9328/i2c.c
+ create mode 100644 board/armadeus/apf9328/lowlevel_init.S
+
+diff --git a/board/armadeus/apf9328/Makefile b/board/armadeus/apf9328/Makefile
+new file mode 100644
+index 0000000..0f097cd
+--- /dev/null
++++ b/board/armadeus/apf9328/Makefile
+@@ -0,0 +1,10 @@
++#
++# (C) Copyright 2000-2004
++# Wolfgang Denk, DENX Software Engineering, wd...@de....
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y := apf9328.o i2c.o eeprom.o
++obj-y += lowlevel_init.o
++obj-$(CONFIG_FPGA) += apf9328fpga.o fpga.o
+diff --git a/board/armadeus/apf9328/apf9328.c b/board/armadeus/apf9328/apf9328.c
+new file mode 100644
+index 0000000..280f749
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328.c
+@@ -0,0 +1,61 @@
++/*
++ * Copyright (C) 2005-2015
++ * Nicolas Colombain <nic...@ar...>
++ * Eric Jarrige <eri...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/arch/imx-regs.h>
++#include <flash.h>
++#include <netdev.h>
++#include "apf9328fpga.h"
++
++extern void imx_gpio_mode(int gpio_mode);
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int board_init(void)
++{
++
++ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
++
++#ifdef CONFIG_DRIVER_DM9000
++ imx_gpio_mode(GPIO_PORTB | GPIO_DR | GPIO_IN | 14);
++#endif
++
++#ifdef CONFIG_FPGA
++ apf9328_init_fpga();
++#endif
++
++ return 0;
++}
++
++int dram_init(void)
++{
++ /* dram_init must store complete ramsize in gd->ram_size */
++ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
++ PHYS_SDRAM_1_SIZE);
++ return 0;
++}
++
++void enable_caches(void)
++{
++#ifndef CONFIG_SYS_DCACHE_OFF
++ /* Enable D-cache. I-cache is already enabled in start.S */
++ dcache_enable();
++#endif
++}
++
++void show_boot_progress(int status)
++{
++ return;
++}
++
++#ifdef CONFIG_DRIVER_DM9000
++int board_eth_init(bd_t *bis)
++{
++ return dm9000_initialize(bis);
++}
++#endif
+diff --git a/board/armadeus/apf9328/apf9328fpga.c b/board/armadeus/apf9328/apf9328fpga.c
+new file mode 100644
+index 0000000..9782115
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328fpga.c
+@@ -0,0 +1,65 @@
++/*
++ * Copyright (C) 2005-2015
++ * Nicolas Colombain <nic...@ar...>
++ * Eric Jarrige <eri...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/*
++ * Spartan 3 FPGA configuration support for the APF9328 daughter board
++ */
++
++#include <common.h>
++#include <spartan3.h>
++#include <command.h>
++#include <jffs2/jffs2.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include "apf9328fpga.h"
++
++#ifdef CONFIG_FPGA
++DECLARE_GLOBAL_DATA_PTR;
++/* Note that these are pointers to code that is in Flash. They will be
++ * relocated at runtime.
++ * Spartan3 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++xilinx_spartan3_slave_serial_fns fpga_fns = {
++ fpga_pre_fn,
++ fpga_pgm_fn,
++ fpga_clk_fn,
++ fpga_init_fn,
++ fpga_done_fn,
++ fpga_wr_fn,
++ fpga_post_fn,
++ NULL,
++ fpga_abort_fn,
++};
++
++xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
++ {xilinx_spartan3,
++ slave_serial,
++ XILINX_XC3S400_SIZE,
++ (void *)&fpga_fns,
++ 0,
++ &spartan3_op }
++};
++
++/*
++ * Initialize the fpga. Return 1 on success, 0 on failure.
++ */
++int apf9328_init_fpga(void)
++{
++ int i;
++
++ fpga_init();
++
++ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
++ fpga_add(fpga_xilinx, &fpga[i]);
++ }
++
++ return 0;
++}
++
++#endif /* CONFIG_FPGA */
+diff --git a/board/armadeus/apf9328/apf9328fpga.h b/board/armadeus/apf9328/apf9328fpga.h
+new file mode 100644
+index 0000000..2a15443
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328fpga.h
+@@ -0,0 +1,10 @@
++/*
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/*
++ * Spartan 3 FPGA configuration support for the APF9328 daughter board
++ */
++
++#include "fpga.h"
++extern int apf9328_init_fpga(void);
+diff --git a/board/armadeus/apf9328/eeprom.c b/board/armadeus/apf9328/eeprom.c
+new file mode 100644
+index 0000000..c8165ea
+--- /dev/null
++++ b/board/armadeus/apf9328/eeprom.c
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (C) 2008-2015 Armadeus Project
++ * Copyright (C) 2007
++ * Stefano Babic, DENX Software Engineering, sb...@de....
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <command.h>
++#include <dm9000.h>
++
++static int do_read_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
++ char * const argv[])
++{
++ unsigned int i;
++ u8 data[2];
++
++ for (i = 0; i < 0x40; i++) {
++ if (!(i % 0x10))
++ printf("\n%08x:", i);
++ dm9000_read_srom_word(i, data);
++ printf(" %02x%02x", data[1], data[0]);
++ }
++ printf("\n");
++ return 0;
++}
++
++static int do_write_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
++ char * const argv[])
++{
++ unsigned long offset, value;
++
++ if (argc < 4) {
++ cmd_usage(cmdtp);
++ return 1;
++ }
++
++ strict_strtoul(argv[2], 16, &offset);
++ strict_strtoul(argv[3], 16, &value);
++ if (offset > 0x40) {
++ printf("Wrong offset : 0x%lx\n", offset);
++ cmd_usage(cmdtp);
++ return 1;
++ }
++ dm9000_write_srom_word(offset, value);
++ return 0;
++}
++
++int do_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++{
++ if (argc < 2) {
++ cmd_usage(cmdtp);
++ return 1;
++ }
++
++ if (strcmp(argv[1], "read") == 0) {
++ return do_read_dm9000_eeprom(cmdtp, flag, argc, argv);
++ } else if (strcmp(argv[1], "write") == 0) {
++ return do_write_dm9000_eeprom(cmdtp, flag, argc, argv);
++ } else {
++ cmd_usage(cmdtp);
++ return 1;
++ }
++}
++
++U_BOOT_CMD(dm9000ee, 4, 1, do_dm9000_eeprom,
++ "Read/Write eeprom connected to Ethernet Controller",
++ "\ndm9000ee write <word offset> <value>\n"
++ "\tdm9000ee read\n"
++ "\tword:\t\t00-02 : MAC Address\n"
++ "\t\t\t03-07 : DM9000 Configuration\n" "\t\t\t08-63 : User data");
+diff --git a/board/armadeus/apf9328/fpga.c b/board/armadeus/apf9328/fpga.c
+new file mode 100644
+index 0000000..f3d4f03
+--- /dev/null
++++ b/board/armadeus/apf9328/fpga.c
+@@ -0,0 +1,116 @@
++/*
++ * Copyright (C) 2007
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++#include <common.h>
++
++#ifdef CONFIG_FPGA
++
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include <config.h>
++
++extern void imx_gpio_mode(int gpio_mode);
++
++#define GPIO_PORT(x) ((x >> 5) & 3)
++#define GPIO_SET(x) (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
++#define GPIO_CLEAR(x) (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
++#define GPIO_WRITE(x, y) (y ? GPIO_SET(x) : GPIO_CLEAR(x))
++#define GPIO_READ(x) ((SSR(GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK))))
++
++/*
++ * Port bit numbers for the serial slave controls
++ */
++#define FPGA_INIT CONFIG_SYS_FPGA_INIT
++#define FPGA_DONE CONFIG_SYS_FPGA_DONE
++#define FPGA_DIN CONFIG_SYS_FPGA_DATA
++#define FPGA_PROGRAM CONFIG_SYS_FPGA_PRG
++#define FPGA_CLOCK CONFIG_SYS_FPGA_CLK
++
++/* Note that these are pointers to code that is in Flash. They will be
++ * relocated at runtime.
++ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++
++/*
++ * nitialize GPIO port B before download
++ */
++int fpga_pre_fn(int cookie)
++{
++ debug("%s:%d: FPGA PRE ", __func__, __LINE__);
++
++ /* Initialize GPIO pins */
++ imx_gpio_mode(FPGA_INIT | GPIO_DR | GPIO_IN);
++ imx_gpio_mode(FPGA_DONE | GPIO_DR | GPIO_IN);
++ imx_gpio_mode(FPGA_DIN | GPIO_DR | GPIO_OUT);
++ imx_gpio_mode(FPGA_PROGRAM | GPIO_DR | GPIO_OUT);
++ imx_gpio_mode(FPGA_CLOCK | GPIO_DR | GPIO_OUT);
++ return cookie;
++}
++
++/*
++ * Set the FPGA's active-low program line to the specified level
++ */
++int fpga_pgm_fn(int assert, int flush, int cookie)
++{
++ debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
++ assert ? "high" : "low");
++ GPIO_WRITE(FPGA_PROGRAM, !assert);
++ return assert;
++}
++
++/*
++ * Set the FPGA's active-high clock line to the specified level
++ */
++int fpga_clk_fn(int assert_clk, int flush, int cookie)
++{
++ debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
++ assert_clk ? "high" : "low");
++ GPIO_WRITE(FPGA_CLOCK, assert_clk);
++ return assert_clk;
++}
++
++/*
++ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
++ * asserted (low).
++ */
++int fpga_init_fn(int cookie)
++{
++ debug("%s:%d: INIT check... ", __func__, __LINE__);
++ return !GPIO_READ(FPGA_INIT);
++}
++
++/*
++ * Test the state of the active-high FPGA DONE pin
++ */
++int fpga_done_fn(int cookie)
++{
++ debug("%s:%d: DONE check... ", __func__, __LINE__);
++ return GPIO_READ(FPGA_DONE);
++}
++
++/*
++ * Set the FPGA's data line to the specified level
++ */
++int fpga_wr_fn(int assert_write, int flush, int cookie)
++{
++ debug("%s:%d: DATA write... ", __func__, __LINE__);
++ GPIO_WRITE(FPGA_DIN, assert_write);
++ return assert_write;
++}
++
++int fpga_post_fn(int cookie)
++{
++ return cookie;
++}
++
++int fpga_abort_fn(int cookie)
++{
++ return fpga_post_fn(cookie);
++}
++
++#endif /* CONFIG_FPGA */
+diff --git a/board/armadeus/apf9328/fpga.h b/board/armadeus/apf9328/fpga.h
+new file mode 100644
+index 0000000..3b226d7
+--- /dev/null
++++ b/board/armadeus/apf9328/fpga.h
+@@ -0,0 +1,15 @@
++/*
++ * Copyright (C) 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++extern int fpga_pre_fn(int cookie);
++extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
++extern int fpga_init_fn(int cookie);
++extern int fpga_done_fn(int cookie);
++extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
++extern int fpga_wr_fn(int assert_write, int flush, int cookie);
++extern int fpga_post_fn(int cookie);
++extern int fpga_abort_fn(int cookie);
+diff --git a/board/armadeus/apf9328/i2c.c b/board/armadeus/apf9328/i2c.c
+new file mode 100644
+index 0000000..0ba0a8d
+--- /dev/null
++++ b/board/armadeus/apf9328/i2c.c
+@@ -0,0 +1,260 @@
++/*
++ * Copyright (C) 2005-2015 Eric Jarrige <eri...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++
++#ifdef CONFIG_HARD_I2C
++
++#include <asm/io.h>
++#include <asm/arch/imx-regs.h>
++#include <i2c.h>
++
++extern void imx_gpio_mode(int gpio_mode);
++
++/*-----------------------------------------------------------------------
++ * Definitions
++ */
++
++#define I2C_ACK 0 /* level to ack a byte */
++#define I2C_NOACK 1 /* level to noack a byte */
++
++/*-----------------------------------------------------------------------
++ * Local functions
++ */
++
++/*-----------------------------------------------------------------------
++ * START: High -> Low on SDA while SCL is High
++ * after check for a bus free
++ */
++static void imxi2c_send_start(void)
++{
++ while (I2SR & I2SR_IBB)
++ udelay(1);
++
++ I2CR |= I2CR_MSTA;
++ I2SR &= ~I2SR_IIF;
++}
++
++/*-----------------------------------------------------------------------
++ * STOP: Low -> High on SDA while SCL is High
++ * after the end of previous transfer
++ */
++static void imxi2c_send_stop(void)
++{
++ while (!(I2SR & I2SR_ICF))
++ udelay(1);
++
++ I2CR &= ~I2CR_MSTA;
++}
++
++/*-----------------------------------------------------------------------
++ * Send 8 bits and look for an acknowledgement.
++ */
++static int imxi2c_write_byte(uchar data)
++{
++ while (!(I2SR & I2SR_ICF)) /* Wait end of transfer */
++ udelay(1);
++
++ I2CR |= I2CR_MTX;
++ I2SR &= ~I2SR_IIF;
++ I2DR = data;
++
++ while (!(I2SR & I2SR_IIF)) /* checking IIF before ICF: FIXME */
++ udelay(1);
++
++ I2SR &= ~I2SR_IIF;
++
++ while (!(I2SR & I2SR_ICF)) /* Wait end of transfer */
++ udelay(1);
++
++ return I2SR & I2SR_RXAK; /* not a nack is an ack */
++}
++
++/*-----------------------------------------------------------------------
++ * if ack == I2C_ACK, ACK the byte so can continue reading, else
++ * send I2C_NOACK to end the read.
++ */
++static uchar imxi2c_read_byte(int ack)
++{
++ int data;
++
++ while (!(I2SR & I2SR_ICF))
++ udelay(1);
++
++ I2CR &= ~I2CR_MTX;
++
++ if (ack)
++ I2CR |= I2CR_TXAK;
++ else
++ I2CR &= ~I2CR_TXAK;
++
++ data = I2DR;
++ return data;
++}
++
++/* ------------------------------------------------------------------------
++ * API Functions
++ * ------------------------------------------------------------------------
++ */
++
++/*-----------------------------------------------------------------------
++ * i2c_init compute the i2c divider to reach the requested speed
++ * see mxl reference manual
++ */
++void i2c_init(int speed, int slaveaddr)
++{
++ int hclk_dividers[] = {
++ 30, 32, 36, 42, 48, 52, 60, 72,
++ 80, 88, 104, 128, 144, 160, 192, 240,
++ 288, 320, 384, 480, 576, 640, 768, 960,
++ 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840,
++ 22, 24, 26, 26, 32, 36, 40, 44,
++ 48, 56, 64, 72, 80, 96, 112, 128,
++ 160, 192, 224, 256, 320, 384, 448, 512,
++ 640, 768, 896, 1024, 1280, 1536, 1792, 2048
++ };
++ int refDiv = get_HCLK() / speed;
++ int i, tmpIC;
++
++ imx_gpio_mode(PA15_PF_I2C_SDA);
++ imx_gpio_mode(PA16_PF_I2C_SCL);
++
++ tmpIC = (sizeof(hclk_dividers) / sizeof(int)) - 1;
++ for (i = tmpIC; i >= 0; i--) {
++ if ((hclk_dividers[i] >= refDiv)
++ && (hclk_dividers[i] < hclk_dividers[tmpIC])) {
++ tmpIC = i;
++ }
++ }
++
++ IFDR = tmpIC;
++ IADR = slaveaddr << 1;
++
++ if (I2SR & I2SR_IBB)
++ imxi2c_send_stop();
++
++ I2CR |= I2CR_IEN;
++}
++
++/*-----------------------------------------------------------------------
++ * Probe to see if a chip is present. Also good for checking for the
++ * completion of EEPROM writes since the chip stops responding until
++ * the write completes (typically 10mSec).
++ * probe sends a read command to probe a an address
++ */
++int i2c_probe(uchar addr)
++{
++ int rc;
++
++ imxi2c_send_start();
++ rc = imxi2c_write_byte((addr << 1) | 0);
++ imxi2c_send_stop();
++
++ return rc ? 1 : 0;
++}
++
++/*-----------------------------------------------------------------------
++ * Read bytes
++ */
++int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
++{
++ int shift;
++ debug("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
++ chip, addr, alen, buffer, len);
++
++#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
++ /*
++ * EEPROM chips that implement "address overflow" are ones
++ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
++ * address and the extra bits end up in the "chip address"
++ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
++ * four 256 byte chips.
++ *
++ * Note that we consider the length of the address field to
++ * still be one byte because the extra address bits are
++ * hidden in the chip address.
++ */
++ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
++
++ debug("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
++ chip, addr);
++#endif
++
++ /*
++ * Do the addressing portion of a write cycle to set the
++ * chip's address pointer. If the address length is zero,
++ * don't do the normal write cycle to set the address pointer,
++ * there is no address pointer in this chip.
++ */
++ imxi2c_send_start();
++ if (alen > 0) {
++ if (imxi2c_write_byte(chip << 1)) { /* write cycle */
++ imxi2c_send_stop();
++ debug("i2c_read, no chip responded %02X\n", chip);
++ return 1;
++ }
++ shift = (alen - 1) * 8;
++ while (alen-- > 0) {
++ if (imxi2c_write_byte(addr >> shift)) {
++ debug("i2c_read, address not <ACK>ed\n");
++ return 1;
++ }
++ shift -= 8;
++ }
++
++ /* reportedly some chips need a full stop */
++ imxi2c_send_stop();
++ imxi2c_send_start();
++ }
++ /*
++ * Send the chip address again, this time for a read cycle.
++ * Then read the data. On the last byte, we do a NACK instead
++ * of an ACK(len == 0) to terminate the read.
++ */
++ imxi2c_write_byte((chip << 1) | 1); /* read cycle */
++ imxi2c_read_byte(len <= 2);
++ while (len-- > 1)
++ *buffer++ = imxi2c_read_byte(len == 1);
++
++ imxi2c_send_stop();
++ *buffer++ = imxi2c_read_byte(0);
++ return 0;
++}
++
++/*-----------------------------------------------------------------------
++ * Write bytes
++ */
++int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
++{
++ int shift, failures = 0;
++
++ debug("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
++ chip, addr, alen, buffer, len);
++
++ imxi2c_send_start();
++ if (imxi2c_write_byte(chip << 1)) { /* write cycle */
++ imxi2c_send_stop();
++ debug("i2c_write, no chip responded %02X\n", chip);
++ return 1;
++ }
++ shift = (alen - 1) * 8;
++ while (alen-- > 0) {
++ if (imxi2c_write_byte(addr >> shift)) {
++ debug("i2c_write, address not <ACK>ed\n");
++ return 1;
++ }
++ shift -= 8;
++ }
++
++ while (len-- > 0) {
++ if (imxi2c_write_byte(*buffer++))
++ failures++;
++ }
++ imxi2c_send_stop();
++ return failures;
++}
++
++#endif /* CONFIG_HARD_I2C */
+diff --git a/board/armadeus/apf9328/lowlevel_init.S b/board/armadeus/apf9328/lowlevel_init.S
+new file mode 100644
+index 0000000..f080423
+--- /dev/null
++++ b/board/armadeus/apf9328/lowlevel_init.S
+@@ -0,0 +1,458 @@
++/*
++ * Copyright (C) 2005-2015 Eric Jarrige <eri...@ar...>
++ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <config.h>
++#include <version.h>
++#include <asm/arch/imx-regs.h>
++
++.globl lowlevel_init
++lowlevel_init:
++/* Change PERCLK1DIV to 14 ie 14+1 */
++ ldr r0, =PCDR
++ ldr r1, =CONFIG_SYS_PCDR_VAL
++ str r1, [r0]
++
++/* set MCU PLL Control Register 0 */
++
++ ldr r0, =MPCTL0
++ ldr r1, =CONFIG_SYS_MPCTL0_VAL
++ str r1, [r0]
++
++/* set MCU PLL Control Register 1 */
++
++ ldr r0, =MPCTL1
++ ldr r1, =CONFIG_SYS_MPCTL1_VAL
++ str r1, [r0]
++
++/* set mpll restart bit */
++ ldr r0, =CSCR
++ ldr r1, [r0]
++ orr r1,r1,#(1<<21)
++ str r1, [r0]
++
++ mov r2,#0x10
++1:
++ mov r3,#0x2000
++2:
++ subs r3,r3,#1
++ bne 2b
++
++ subs r2,r2,#1
++ bne 1b
++
++/* set System PLL Control Register 0 */
++
++ ldr r0, =SPCTL0
++ ldr r1, =CONFIG_SYS_SPCTL0_VAL
++ str r1, [r0]
++
++/* set System PLL Control Register 1 */
++
++ ldr r0, =SPCTL1
++ ldr r1, =CONFIG_SYS_SPCTL1_VAL
++ str r1, [r0]
++
++/* set spll restart bit */
++ ldr r0, =CSCR
++ ldr r1, [r0]
++ orr r1,r1,#(1<<22)
++ str r1, [r0]
++
++ mov r2,#0x10
++1:
++ mov r3,#0x2000
++2:
++ subs r3,r3,#1
++ bne 2b
++
++ subs r2,r2,#1
++ bne 1b
++
++ ldr r0, =CSCR
++ ldr r1, =CONFIG_SYS_CSCR_VAL
++ str r1, [r0]
++
++ ldr r0, =GPCR
++ ldr r1, =CONFIG_SYS_GPCR_VAL
++ str r1, [r0]
++
++/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
++ *this.....
++ *
++ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
++ * register 1, this stops it using the output of the PLL and thus runs at the
++ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
++ * use the value set in the CM_OSC registers...regardless of what you set it
++ * too! Thus, although i thought i was running at 140MHz, i'm actually running
++ * at 40!..
++
++ * Slapping this into my bootloader does the trick...
++
++ * MRC p15,0,r0,c1,c0,0 ; read core configuration register
++ * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
++ * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
++ * register
++ */
++ MRC p15,0,r0,c1,c0,0
++ ORR r0,r0,#0xC0000000
++ MCR p15,0,r0,c1,c0,0
++
++/* ldr r0, =GPR(0)
++ ldr r1, =CONFIG_SYS_GPR_A_VAL
++ str r1, [r0]
++*/
++
++ ldr r0, =DR(0)
++ ldr r1, =CONFIG_SYS_DR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(0)
++ ldr r1, =CONFIG_SYS_OCR1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(0)
++ ldr r1, =CONFIG_SYS_OCR2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(0)
++ ldr r1, =CONFIG_SYS_ICFA1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(0)
++ ldr r1, =CONFIG_SYS_ICFA2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(0)
++ ldr r1, =CONFIG_SYS_ICFB1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(0)
++ ldr r1, =CONFIG_SYS_ICFB2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(0)
++ ldr r1, =CONFIG_SYS_ICR1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(0)
++ ldr r1, =CONFIG_SYS_ICR2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(0)
++ ldr r1, =CONFIG_SYS_IMR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(0)
++ ldr r1, =CONFIG_SYS_DDIR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(0)
++ ldr r1, =CONFIG_SYS_GPR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(0)
++ ldr r1, =CONFIG_SYS_PUEN_A_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(0)
++ ldr r1, =CONFIG_SYS_GIUS_A_VAL
++ str r1, [r0]
++
++ ldr r0, =DR(1)
++ ldr r1, =CONFIG_SYS_DR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(1)
++ ldr r1, =CONFIG_SYS_OCR1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(1)
++ ldr r1, =CONFIG_SYS_OCR2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(1)
++ ldr r1, =CONFIG_SYS_ICFA1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(1)
++ ldr r1, =CONFIG_SYS_ICFA2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(1)
++ ldr r1, =CONFIG_SYS_ICFB1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(1)
++ ldr r1, =CONFIG_SYS_ICFB2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(1)
++ ldr r1, =CONFIG_SYS_ICR1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(1)
++ ldr r1, =CONFIG_SYS_ICR2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(1)
++ ldr r1, =CONFIG_SYS_IMR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(1)
++ ldr r1, =CONFIG_SYS_DDIR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(1)
++ ldr r1, =CONFIG_SYS_GPR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(1)
++ ldr r1, =CONFIG_SYS_PUEN_B_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(1)
++ ldr r1, =CONFIG_SYS_GIUS_B_VAL
++ str r1, [r0]
++
++ ldr r0, =DR(2)
++ ldr r1, =CONFIG_SYS_DR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(2)
++ ldr r1, =CONFIG_SYS_OCR1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(2)
++ ldr r1, =CONFIG_SYS_OCR2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(2)
++ ldr r1, =CONFIG_SYS_ICFA1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(2)
++ ldr r1, =CONFIG_SYS_ICFA2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(2)
++ ldr r1, =CONFIG_SYS_ICFB1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(2)
++ ldr r1, =CONFIG_SYS_ICFB2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(2)
++ ldr r1, =CONFIG_SYS_ICR1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(2)
++ ldr r1, =CONFIG_SYS_ICR2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(2)
++ ldr r1, =CONFIG_SYS_IMR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(2)
++ ldr r1, =CONFIG_SYS_DDIR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(2)
++ ldr r1, =CONFIG_SYS_GPR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(2)
++ ldr r1, =CONFIG_SYS_PUEN_C_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(2)
++ ldr r1, =CONFIG_SYS_GIUS_C_VAL
++ str r1, [r0]
++
++ ldr r0, =DR(3)
++ ldr r1, =CONFIG_SYS_DR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(3)
++ ldr r1, =CONFIG_SYS_OCR1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(3)
++ ldr r1, =CONFIG_SYS_OCR2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(3)
++ ldr r1, =CONFIG_SYS_ICFA1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(3)
++ ldr r1, =CONFIG_SYS_ICFA2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(3)
++ ldr r1, =CONFIG_SYS_ICFB1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(3)
++ ldr r1, =CONFIG_SYS_ICFB2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(3)
++ ldr r1, =CONFIG_SYS_ICR1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(3)
++ ldr r1, =CONFIG_SYS_ICR2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(3)
++ ldr r1, =CONFIG_SYS_IMR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(3)
++ ldr r1, =CONFIG_SYS_DDIR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(3)
++ ldr r1, =CONFIG_SYS_GPR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(3)
++ ldr r1, =CONFIG_SYS_PUEN_D_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(3)
++ ldr r1, =CONFIG_SYS_GIUS_D_VAL
++ str r1, [r0]
++
++/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
++
++ ldr r0, =FMCR
++ ldr r1, =CONFIG_SYS_FMCR_VAL
++ str r1, [r0]
++
++ ldr r0, =CS0U
++ ldr r1, =CONFIG_SYS_CS0U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS0L
++ ldr r1, =CONFIG_SYS_CS0L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS1U
++ ldr r1, =CONFIG_SYS_CS1U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS1L
++ ldr r1, =CONFIG_SYS_CS1L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS2U
++ ldr r1, =CONFIG_SYS_CS2U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS2L
++ ldr r1, =CONFIG_SYS_CS2L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS3U
++ ldr r1, =CONFIG_SYS_CS3U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS3L
++ ldr r1, =CONFIG_SYS_CS3L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS4U
++ ldr r1, =CONFIG_SYS_CS4U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS4L
++ ldr r1, =CONFIG_SYS_CS4L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS5U
++ ldr r1, =CONFIG_SYS_CS5U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS5L
++ ldr r1, =CONFIG_SYS_CS5L_VAL
++ str r1, [r0]
++
++ adr r0, sdramsetup /* r0 <- current position of code */
++ /* test if we run from flash or RAM */
++ ldr r1, =PHYS_SDRAM_1
++ cmp r1, r0 /* don't reloc during debug*/
++ bhi sdramsetup
++ /* test if we run from flash or RAM */
++ ldr r1, =CONFIG_SYS_FLASH_BASE
++ cmp r0, r1 /* don't reloc during debug */
++ bmi copy2ram
++
++/* SDRAM Setup */
++sdramsetup:
++ ldr r0, =SDCTL0
++ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
++ str r1, [r0]
++
++ ldr r1, =PHYS_SDRAM_1 \
++ +CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldr r2, [r1]
++
++ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
++ str r1, [r0]
++
++ ldr r1, =PHYS_SDRAM_1
++ ldr r2, [r1] /* Issue AutoRefresh Command */
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++
++ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
++ str r1, [r0]
++
++ ldr r1, =PHYS_SDRAM_1 \
++ +CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ str r2, [r1]
++
++ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
++ str r1, [r0]
++/* make U-Boot runnable form "almost" anywhere */
++/* but SYS_TEXT_BASE should be in RAM */
++copy2ram: /* populate _TEXT_BASE with U-Boot from load addr */
++ ldr r0, _start_adr
++ ldr r1, _copy2ram
++ sub r1, r1, r0
++ adr r0, copy2ram
++ sub r0, r0, r1
++ ldr r1, =CONFIG_SYS_TEXT_BASE
++ cmp r0, r1
++ beq end_of_copy2ram /* skip U-Boot copy */
++ ldr r2, =CONFIG_SYS_MONITOR_LEN
++ add r2, r2, r0 /* r2 <- source end address */
++
++copy_loop:
++ ldmia r0!, {r9-r10} /* copy from source address [r0] */
++ stmia r1!, {r9-r10} /* copy to target address [r1] */
++ cmp r0, r2 /* until source end address [r2] */
++ blo copy_loop
++ ldr pc, =CONFIG_SYS_TEXT_BASE /* reboot from RAM */
++ nop
++ nop
++
++end_of_copy2ram:
++ mov pc,lr
++
++_copy2ram:
++ .word copy2ram
++_start_adr:
++ .word _start
+--- /dev/null
++++ b/configs/apf9328_defconfig
+@@ -0,0 +1,2 @@
++CONFIG_ARM=y
++CONFIG_TARGET_APF9328=y
+--- /dev/null
++++ b/board/armadeus/apf9328/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_APF9328
++
++config SYS_BOARD
++ default "apf9328"
++
++config SYS_VENDOR
++ default "armadeus"
++
++config SYS_SOC
++ default "imx"
++
++config SYS_CONFIG_NAME
++ default "apf9328"
++
++endif
+--- /dev/null
++++ b/board/armadeus/apf9328/MAINTAINERS
+@@ -0,0 +1,6 @@
++APF9328 BOARD
++M: Eric Jarrige <eri...@ar...>
++S: Maintained
++F: board/armadeus/apf9328/
++F: include/configs/apf9328.h
++F: configs/apf9328_defconfig
+--
+1.7.2.5
+
diff --git a/patches/u-boot/2014.04/106-mx1-pllclk.patch b/patches/u-boot/2015.01/106-mx1-pllclk.patch
similarity index 100%
copy from patches/u-boot/2014.04/106-mx1-pllclk.patch
copy to patches/u-boot/2015.01/106-mx1-pllclk.patch
diff --git a/patches/u-boot/2014.04/107-mx1-pllclk-debug.patch b/patches/u-boot/2015.01/107-mx1-pllclk-debug.patch
similarity index 100%
copy from patches/u-boot/2014.04/107-mx1-pllclk-debug.patch
copy to patches/u-boot/2015.01/107-mx1-pllclk-debug.patch
diff --git a/patches/u-boot/2014.04/108-DM9000.patch b/patches/u-boot/2015.01/108-DM9000.patch
similarity index 100%
copy from patches/u-boot/2014.04/108-DM9000.patch
copy to patches/u-boot/2015.01/108-DM9000.patch
diff --git a/patches/u-boot/2014.07/300-imx27-fix_dcache_boot_issue.patch b/patches/u-boot/2015.01/300-imx27-fix_dcache_boot_issue.patch
similarity index 100%
copy from patches/u-boot/2014.07/300-imx27-fix_dcache_boot_issue.patch
copy to patches/u-boot/2015.01/300-imx27-fix_dcache_boot_issue.patch
diff --git a/patches/u-boot/2015.01/301-apf27-support-boot-from-RAM.patch b/patches/u-boot/2015.01/301-apf27-support-boot-from-RAM.patch
new file mode 100644
index 0000000..a8da017
--- /dev/null
+++ b/patches/u-boot/2015.01/301-apf27-support-boot-from-RAM.patch
@@ -0,0 +1,27 @@
+apf27: Support boot from RAM
+This patch adds capabilites to start U-Boot directly from RAM
+to test a new version of U-Boot before being programmed in FLASH.
+here are two typical use cases:
+- Load and test U-Boot SPL from RAM to launch U-Boot from FLASH.
+ run download_uboot ; go a0000000
+- Load and run U-Boot from RAM
+ run download_uboot ; go a0000800
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+--- a/board/armadeus/apf27/lowlevel_init.S
++++ b/board/armadeus/apf27/lowlevel_init.S
+@@ -162,6 +162,13 @@ lowlevel_init:
+ init_aipi
+ init_clock
+ #ifdef CONFIG_SPL_BUILD
++ /* skip sdram initialization if we run from RAM */
++ cmp pc, #PHYS_SDRAM_1
++ bls 1f
++ cmp pc, #(PHYS_SDRAM_2+PHYS_SDRAM_2_SIZE)
++ bhi 1f
++ mov pc, lr
++1:
+ init_ddr
+ #endif
+
diff --git a/patches/u-boot/2015.01/302-imx-nand-lock-unlock.patch b/patches/u-boot/2015.01/302-imx-nand-lock-unlock.patch
new file mode 100644
index 0000000..101016e
--- /dev/null
+++ b/patches/u-boot/2015.01/302-imx-nand-lock-unlock.patch
@@ -0,0 +1,98 @@
+mxc_nand.c: Support nand lock/unlock
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+--
+ drivers/mtd/nand/mxc_nand.c | 66 +++++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 66 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
+index d0ded48..2bbc1fd 100644
+--- a/drivers/mtd/nand/mxc_nand.c
++++ b/drivers/mtd/nand/mxc_nand.c
+@@ -47,6 +47,28 @@ static struct mxc_nand_host *host = &mxc_host;
+ #define MAIN_SINGLEBIT_ERROR 0x4
+ #define SPARE_SINGLEBIT_ERROR 0x1
+
++#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
++/******************************************************************************
++ * Support for locking / unlocking feature of imx NFC controller
++ *****************************************************************************/
++
++#define NAND_CMD_LOCK 0x2a
++#define NAND_CMD_LOCK_TIGHT 0x2c
++#define NAND_CMD_UNLOCK1 0x23
++#define NAND_CMD_UNLOCK2 0x24
++#define NAND_CMD_LOCK_STATUS 0x7a
++
++/* NFC_WRPROT Control Register Bit Fields */
++#define NFC_WRPROT_UNLOCKBLK (4<<0) /* unlock block according to given address range */
++#define NFC_WRPROT_LOCKALL (2<<0) /* lock all */
++#define NFC_WRPROT_LOCKTIGHT (1<<0) /* lock-tight locked blocks */
++/* NFC_WRPR_STAT Status Register Bit Fields */
++#define NFC_WRPR_US (1<<2) /* Unlocked status */
++#define NFC_WRPR_LS (1<<1) /* Locked status */
++#define NFC_WRPR_LTS (1<<0) /* Lock-tight Status */
++
++#endif
++
+ /* OOB placement block for use with hardware ecc generation */
+ #if defined(MXC_NFC_V1)
+ #ifndef CONFIG_SYS_NAND_LARGEPAGE
+@@ -1083,6 +1095,53 @@ void mxc_nand_command(struct mtd_info *mtd, unsigned command,
+ }
+
+ break;
++#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
++ case NAND_CMD_LOCK:
++ /* Blocks to be unlocked */
++ writew(-1, &host->regs->unlockstart_blkaddr);
++ writew(-1, &host->regs->unlockend_blkaddr);
++
++ /* Lock Block Command for given address range */
++ writew(NFC_WRPROT_LOCKALL, &host->regs->wrprot);
++ return;
++ case NAND_CMD_LOCK_TIGHT:
++ /* Blocks to be unlocked */
++ writew(-1, &host->regs->unlockstart_blkaddr);
++ writew(-1, &host->regs->unlockend_blkaddr);
++
++ /* Lock Block Command for given address range */
++ writew(NFC_WRPROT_LOCKTIGHT, &host->regs->wrprot);
++ return;
++ case NAND_CMD_UNLOCK1:
++ writew(page_addr>>6, &host->regs->unlockstart_blkaddr);
++ return;
++ case NAND_CMD_UNLOCK2:
++ writew(page_addr>>6, &host->regs->unlockend_blkaddr);
++
++ /* Lock Block Command for given address range */
++ writew(NFC_WRPROT_UNLOCKBLK, &host->regs->wrprot);
++ return;
++ case NAND_CMD_LOCK_STATUS:
++ host->col_addr = 0;
++ host->spare_only = false;
++
++ MTDDEBUG(MTD_DEBUG_LEVEL3,"get_lock_status %x\n", readw(&host->regs->nf_wrprst));
++
++ if ((readw(&host->regs->nf_wrprst) & NFC_WRPR_US)
++ && !(readw(&host->regs->nf_wrprst) & NFC_WRPR_LTS)
++ && ((readw(&host->regs->unlockend_blkaddr) >= page_addr>>6)
++ && (readw(&host->regs->unlockstart_blkaddr) <= page_addr>>6))) {
++ void __iomem *main_buf = host->regs->main_area[0];
++ writew(NFC_WRPR_US, main_buf);
++ } else if (readw(&host->regs->nf_wrprst) & NFC_WRPR_LTS) {
++ void __iomem *main_buf = host->regs->main_area[0];
++ writew(readw(&host->regs->nf_wrprst), main_buf);
++ } else {
++ void __iomem *main_buf = host->regs->main_area[0];
++ writew(readw(&host->regs->nf_wrprst) & ~NFC_WRPR_US, main_buf);
++ }
++ return;
++#endif
+ }
+
+ /* Write out the command to the device. */
+--
+1.7.2.5
+
diff --git a/patches/u-boot/2014.07/320-spartan.patch b/patches/u-boot/2015.01/303-spartan.patch
similarity index 100%
copy from patches/u-boot/2014.07/320-spartan.patch
copy to patches/u-boot/2015.01/303-spartan.patch
diff --git a/patches/u-boot/2014.04/340-apf27-misc-commands.patch b/patches/u-boot/2015.01/304-apf27-misc-commands.patch
similarity index 100%
copy from patches/u-boot/2014.04/340-apf27-misc-commands.patch
copy to patches/u-boot/2015.01/304-apf27-misc-commands.patch
diff --git a/patches/u-boot/2015.01/400-imx51.patch b/patches/u-boot/2015.01/400-imx51.patch
new file mode 100644
index 0000000..dc6fb93
--- /dev/null
+++ b/patches/u-boot/2015.01/400-imx51.patch
@@ -0,0 +1,522 @@
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ arch/arm/cpu/armv7/cpu.c
+ arch/arm/cpu/armv7/mx5/lowlevel_init.S
+ arch/arm/include/asm/arch-mx5/imx-regs.h
+ arch/arm/include/asm/arch-mx5/iomux-mx51.h
+ arch/arm/include/asm/arch-mx5/regs_esdctl.h
+
+diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
+index 39a8023..c8c2293 100644
+--- a/arch/arm/cpu/armv7/cpu.c
++++ b/arch/arm/cpu/armv7/cpu.c
+@@ -66,5 +66,9 @@ int cleanup_before_linux(void)
+ */
+ cpu_cache_initialization();
+
++#ifndef CONFIG_L2_OFF
++/* v7_outer_cache_enable();*/
++#endif
++
+ return 0;
+ }
+diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+index a40b84f..1ca9b22 100644
+--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
++++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+@@ -11,6 +11,34 @@
+ #include <generated/asm-offsets.h>
+ #include <linux/linkage.h>
+
++#ifndef CONFIG_SYS_PLL_DP_CTL
++/* use internal oscillator */
++#define CONFIG_SYS_PLL_DP_CTL 0x00001232
++#endif
++
++#ifndef CONFIG_SYS_CLKCTL_CCSR
++/* use internal oscillator */
++#define CONFIG_SYS_CLKCTL_CCSR 0x00000000
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCDR
++#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCMR
++/* Use lp_apm (24MHz) source for perclk */
++#define CONFIG_SYS_CLKTL_CBCMR 0x000020C2
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CSCDR1
++#define CONFIG_SYS_CLKTL_CSCDR1 0x00C30321
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCMR1
++/* Use PLL 2 for UART's, get 66.5MHz from it */
++#define CONFIG_SYS_CLKTL_CBCMR1 0xA5A2A020
++#endif
++
+ .section ".text.init", "x"
+
+ .macro init_arm_erratum
+@@ -107,7 +135,7 @@
+ #define W_DP_MFN 8
+
+ setup_pll_func:
+- ldr r1, =0x00001232
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+@@ -124,7 +152,7 @@
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+- ldr r1, =0x00001232
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL
+ str r1, [r0, #PLL_DP_CTL]
+ 1: ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+@@ -136,7 +164,7 @@
+ .macro setup_pll_errata pll, freq
+ ldr r2, =\pll
+ str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+- ldr r1, =0x00001236
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL | 0x04
+ str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
+ 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
+ ands r1, r1, #0x1
+@@ -165,6 +193,16 @@
+ #if defined (CONFIG_MX51)
+ ldr r0, =CCM_BASE_ADDR
+
++#ifdef CONFIG_SYS_CLKCTL_CCMR
++ ldr r1, =CONFIG_SYS_CLKCTL_CCMR
++ str r1, [r0, #CLKCTL_CCMR]
++
++ /* make sure clocks are ready */
++1: ldr r1, [r0, #CLKCTL_CSR]
++ cmp r1, #CONFIG_SYS_CLKCTL_CSR
++ bne 1b
++#endif
++
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+@@ -192,7 +230,7 @@
+ bne 1b
+
+ /* Switch ARM to step clock */
+- mov r1, #0x4
++ mov r1, #CONFIG_SYS_CLKCTL_CCSR | 0x04
+ str r1, [r0, #CLKCTL_CCSR]
+
+ #if defined(CONFIG_MX51_PLL_ERRATA)
+@@ -237,13 +275,14 @@
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1 */
++ mov r1, #CONFIG_SYS_CLKCTL_CCSR
+- str r4, [r0, #CLKCTL_CCSR]
++ str r1, [r0, #CLKCTL_CCSR]
+
+ /* setup the rest */
+- /* Use lp_apm (24MHz) source for perclk */
+- ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
++ /* select source for perclk */
++ ldr r1, =CONFIG_SYS_CLKTL_CBCMR | CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+- /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
++ /* ddr clock from PLL 1 */
+ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+ str r1, [r0, #CLKCTL_CBCDR]
+
+@@ -258,9 +297,9 @@
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+- ldr r1, =0xA5A2A020
++ ldr r1, =CONFIG_SYS_CLKTL_CBCMR1
+ str r1, [r0, #CLKCTL_CSCMR1]
+- ldr r1, =0x00C30321
++ ldr r1, =CONFIG_SYS_CLKTL_CSCDR1
+ str r1, [r0, #CLKCTL_CSCDR1]
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
+index 46017f4..520bf98 100644
+--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
+@@ -250,6 +250,7 @@
+ #define M4IF_GENP_WEIM_MM_MASK 0x00000001
+ #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
+
++#ifndef DP_OP_800
+ /* Assuming 24MHz input clock with doubler ON */
+ /* MFI PDF */
+ #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
+@@ -288,6 +289,7 @@
+ #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+ #define DP_MFD_216 (4 - 1)
+ #define DP_MFN_216 3
++#endif /* DP_OP_800 */
+
+ #define CHIP_REV_1_0 0x10
+ #define CHIP_REV_1_1 0x11
+diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
++++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+@@ -60,9 +60,17 @@ enum {
+ MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
++ MX51_PAD_EIM_D24__I2C2_SDA = IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL),
+ MX51_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D25__UART2_CTS = IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_EIM_D26__UART3_TXD = IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D26__UART2_RTS = IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D27__I2C2_SCL = IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL),
+ MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_D28__AUD6_TXD = IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D29__AUD6_RXD = IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D30__AUD6_TXC = IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D31__AUD6_TXFS = IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+@@ -73,16 +81,22 @@ enum {
+ MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
+- MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_EB2__AUD5_RXFS = IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_EB3__GPIO2_23 = IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_EB3__AUD5_RXC = IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS2__GPIO2_27 = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS2__AUD5_TXD = IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS3__AUD5_RXD = IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS4__AUD5_TXC = IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS5__AUD5_TXFS = IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL),
+ MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDWE__DRAM_SDWE = IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+@@ -99,18 +113,31 @@ enum {
+ MX51_PAD_DRAM_DQM1__DRAM_DQM1 = IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM2__DRAM_DQM2 = IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM3__DRAM_DQM3 = IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_WE_B__NANDF_WE_B = IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RE_B__NANDF_RE_B = IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_ALE__NANDF_ALE = IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_CLE__NANDF_CLE = IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_WP_B__NANDF_WP_B = IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RB0__NANDF_RB0 = IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RB1__ECSPI2_RDY = IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_NANDF_RB2__ECSPI2_SCLK = IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_NANDF_RB3__ECSPI2_MISO = IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_SDBA2__EIM_SDBA2 = IOMUX_PAD(0x508, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_SDODT1__EIM_SDODT1 = IOMUX_PAD(0x50C, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_SDODT0__EIM_SDODT0 = IOMUX_PAD(0x510, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_CS0__NANDF_CS0 = IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
+@@ -123,13 +150,17 @@ enum {
+ MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
+- MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+- MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_NANDF_D15__ECSPI2_MOSI = IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+- MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_NANDF_D14__ECSPI2_SS3 = IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D13__ECSPI2_SS2 = IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0...
[truncated message content] |
|
From: Fabien M <fa...@us...> - 2015-02-04 16:44:39
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via ddaf6ce5fb03c550abd86d5959f833343653a826 (commit)
from 3a7d49312fc14e5a1362343e70bd5c3ff148e1e2 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ddaf6ce5fb03c550abd86d5959f833343653a826
Author: Fabien Marteau <fab...@ar...>
Date: Wed Feb 4 17:42:07 2015 +0100
[DEBUG] Adding pci_debug commands tool to access PCIe BARx memory from linux userspace
-----------------------------------------------------------------------
Summary of changes:
buildroot/package/armadeus/Config.in | 1 +
buildroot/package/armadeus/pci_debug/Config.in | 9 +
buildroot/package/armadeus/pci_debug/pci_debug.mk | 23 +
target/linux/debug/pci_debug/Makefile | 12 +
target/linux/debug/pci_debug/pci_debug.c | 752 +++++++++++++++++++++
5 files changed, 797 insertions(+), 0 deletions(-)
create mode 100644 buildroot/package/armadeus/pci_debug/Config.in
create mode 100644 buildroot/package/armadeus/pci_debug/pci_debug.mk
create mode 100644 target/linux/debug/pci_debug/Makefile
create mode 100644 target/linux/debug/pci_debug/pci_debug.c
diff --git a/buildroot/package/armadeus/Config.in b/buildroot/package/armadeus/Config.in
index 2dedd75..6bb0638 100644
--- a/buildroot/package/armadeus/Config.in
+++ b/buildroot/package/armadeus/Config.in
@@ -4,6 +4,7 @@ source package/armadeus/anybus-tools/Config.in
source package/armadeus/as_devices/Config.in
source package/armadeus/demos/Config.in
source package/armadeus/fpgaregs/Config.in
+source package/armadeus/pci_debug/Config.in
source package/armadeus/fpga_firmware/Config.in
source package/armadeus/imx28-usb-downloader/Config.in
source package/armadeus/imxregs/Config.in
diff --git a/buildroot/package/armadeus/pci_debug/Config.in b/buildroot/package/armadeus/pci_debug/Config.in
new file mode 100644
index 0000000..310a0ca
--- /dev/null
+++ b/buildroot/package/armadeus/pci_debug/Config.in
@@ -0,0 +1,9 @@
+config BR2_PACKAGE_PCI_DEBUG
+ bool "pcidebug"
+ depends on BR2_PACKAGE_READLINE
+ default n
+ help
+ This debug tool allows you to access the PCIe BARx registers
+ directly from Linux userspace.
+ Wrote by D. W. Hawkins :
+ http://www.ovro.caltech.edu/%7Edwh/correlator/pdf/altera_pcie.zip
diff --git a/buildroot/package/armadeus/pci_debug/pci_debug.mk b/buildroot/package/armadeus/pci_debug/pci_debug.mk
new file mode 100644
index 0000000..5eca129
--- /dev/null
+++ b/buildroot/package/armadeus/pci_debug/pci_debug.mk
@@ -0,0 +1,23 @@
+#############################################################
+#
+# pci_debug debug tool
+#
+#############################################################
+
+PCI_DEBUG_VERSION = 2015.02
+PCI_DEBUG_SITE = $(TOPDIR)/../target/linux/debug/pci_debug/
+PCI_DEBUG_SITE_METHOD = local
+PCI_DEBUG_LICENSE = GPLv2+
+
+PCI_DEBUG_BINARY=pci_debug
+PCI_DEBUG_TARGET_BINARY:=usr/bin/$(PCI_DEBUG_BINARY)
+
+define PCI_DEBUG_BUILD_CMDS
+ $(TARGET_CONFIGURE_OPTS) $(MAKE) CC="$(TARGET_CC)" -C $(@D)
+endef
+
+define PCI_DEBUG_INSTALL_TARGET_CMDS
+ $(INSTALL) -m 755 $(@D)/$(PCI_DEBUG_BINARY) $(TARGET_DIR)/$(PCI_DEBUG_TARGET_BINARY)
+endef
+
+$(eval $(generic-package))
diff --git a/target/linux/debug/pci_debug/Makefile b/target/linux/debug/pci_debug/Makefile
new file mode 100644
index 0000000..b8db211
--- /dev/null
+++ b/target/linux/debug/pci_debug/Makefile
@@ -0,0 +1,12 @@
+ARMADEUS_BASE_DIR=../../../..
+-include $(ARMADEUS_BASE_DIR)/Makefile.in
+
+CC:=$(ARMADEUS_TOOLCHAIN_PATH)/$(ARMADEUS_TOOLCHAIN_PREFIX)gcc
+CFLAGS = -Wall
+LDFLAGS += -lreadline -lcurses
+INSTALL_DIR = $(ARMADEUS_ROOTFS_DIR)/usr/bin/
+
+default: pci_debug
+
+pci_debug: pci_debug.c
+
diff --git a/target/linux/debug/pci_debug/pci_debug.c b/target/linux/debug/pci_debug/pci_debug.c
new file mode 100644
index 0000000..f746840
--- /dev/null
+++ b/target/linux/debug/pci_debug/pci_debug.c
@@ -0,0 +1,752 @@
+/* pci_debug.c
+ *
+ * 6/21/2010 D. W. Hawkins
+ *
+ * PCI debug registers interface.
+ *
+ * This tool provides a debug interface for reading and writing
+ * to PCI registers via the device base address registers (BARs).
+ * The tool uses the PCI resource nodes automatically created
+ * by recently Linux kernels.
+ *
+ * The readline library is used for the command line interface
+ * so that up-arrow command recall works. Command-line history
+ * is not implemented. Use -lreadline -lcurses when building.
+ *
+ * ----------------------------------------------------------------
+ */
+#include <stdio.h>
+#include <errno.h>
+#include <string.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+#include <signal.h>
+#include <sys/mman.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <byteswap.h>
+
+/* Readline support */
+#include <readline/readline.h>
+#include <readline/history.h>
+
+/* PCI device */
+typedef struct {
+ /* Base address region */
+ unsigned int bar;
+
+ /* Slot info */
+ unsigned int domain;
+ unsigned int bus;
+ unsigned int slot;
+ unsigned int function;
+
+ /* Resource filename */
+ char filename[100];
+
+ /* File descriptor of the resource */
+ int fd;
+
+ /* Memory mapped resource */
+ unsigned char *maddr;
+ unsigned int size;
+ unsigned int offset;
+
+ /* PCI physical address */
+ unsigned int phys;
+
+ /* Address to pass to read/write (includes offset) */
+ unsigned char *addr;
+} device_t;
+
+void display_help(device_t *dev);
+void parse_command(device_t *dev);
+int process_command(device_t *dev, char *cmd);
+int change_mem(device_t *dev, char *cmd);
+int fill_mem(device_t *dev, char *cmd);
+int display_mem(device_t *dev, char *cmd);
+int change_endian(device_t *dev, char *cmd);
+
+/* Endian read/write mode */
+static int big_endian = 0;
+
+/* Low-level access functions */
+static void
+write_8(
+ device_t *dev,
+ unsigned int addr,
+ unsigned char data);
+
+static unsigned char
+read_8(
+ device_t *dev,
+ unsigned int addr);
+
+static void
+write_le16(
+ device_t *dev,
+ unsigned int addr,
+ unsigned short int data);
+
+static unsigned short int
+read_le16(
+ device_t *dev,
+ unsigned int addr);
+
+static void
+write_be16(
+ device_t *dev,
+ unsigned int addr,
+ unsigned short int data);
+
+static unsigned short int
+read_be16(
+ device_t *dev,
+ unsigned int addr);
+
+static void
+write_le32(
+ device_t *dev,
+ unsigned int addr,
+ unsigned int data);
+
+static unsigned int
+read_le32(
+ device_t *dev,
+ unsigned int addr);
+
+static void
+write_be32(
+ device_t *dev,
+ unsigned int addr,
+ unsigned int data);
+
+static unsigned int
+read_be32(
+ device_t *dev,
+ unsigned int addr);
+
+/* Usage */
+static void show_usage()
+{
+ printf("\nUsage: pci_debug -s <device>\n"\
+ " -h Help (this message)\n"\
+ " -s <device> Slot/device (as per lspci)\n" \
+ " -b <BAR> Base address region (BAR) to access, eg. 0 for BAR0\n\n");
+}
+
+int main(int argc, char *argv[])
+{
+ int opt;
+ char *slot = 0;
+ int status;
+ struct stat statbuf;
+ device_t device;
+ device_t *dev = &device;
+
+ /* Clear the structure fields */
+ memset(dev, 0, sizeof(device_t));
+
+ while ((opt = getopt(argc, argv, "b:hs:")) != -1) {
+ switch (opt) {
+ case 'b':
+ /* Defaults to BAR0 if not provided */
+ dev->bar = atoi(optarg);
+ break;
+ case 'h':
+ show_usage();
+ return -1;
+ case 's':
+ slot = optarg;
+ break;
+ default:
+ show_usage();
+ return -1;
+ }
+ }
+ if (slot == 0) {
+ show_usage();
+ return -1;
+ }
+
+ /* ------------------------------------------------------------
+ * Open and map the PCI region
+ * ------------------------------------------------------------
+ */
+
+ /* Extract the PCI parameters from the slot string */
+ status = sscanf(slot, "%2x:%2x.%1x",
+ &dev->bus, &dev->slot, &dev->function);
+ if (status != 3) {
+ printf("Error parsing slot information!\n");
+ show_usage();
+ return -1;
+ }
+
+ /* Convert to a sysfs resource filename and open the resource */
+ snprintf(dev->filename, 99, "/sys/bus/pci/devices/%04x:%02x:%02x.%1x/resource%d",
+ dev->domain, dev->bus, dev->slot, dev->function, dev->bar);
+ dev->fd = open(dev->filename, O_RDWR | O_SYNC);
+ if (dev->fd < 0) {
+ printf("Open failed for file '%s': errno %d, %s\n",
+ dev->filename, errno, strerror(errno));
+ return -1;
+ }
+
+ /* PCI memory size */
+ status = fstat(dev->fd, &statbuf);
+ if (status < 0) {
+ printf("fstat() failed: errno %d, %s\n",
+ errno, strerror(errno));
+ return -1;
+ }
+ dev->size = statbuf.st_size;
+
+ /* Map */
+ dev->maddr = (unsigned char *)mmap(
+ NULL,
+ (size_t)(dev->size),
+ PROT_READ|PROT_WRITE,
+ MAP_SHARED,
+ dev->fd,
+ 0);
+ if (dev->maddr == (unsigned char *)MAP_FAILED) {
+// printf("failed (mmap returned MAP_FAILED)\n");
+ printf("BARs that are I/O ports are not supported by this tool\n");
+ dev->maddr = 0;
+ close(dev->fd);
+ return -1;
+ }
+
+ /* Device regions smaller than a 4k page in size can be offset
+ * relative to the mapped base address. The offset is
+ * the physical address modulo 4k
+ */
+ {
+ char configname[100];
+ int fd;
+
+ snprintf(configname, 99, "/sys/bus/pci/devices/%04x:%02x:%02x.%1x/config",
+ dev->domain, dev->bus, dev->slot, dev->function);
+ fd = open(configname, O_RDWR | O_SYNC);
+ if (dev->fd < 0) {
+ printf("Open failed for file '%s': errno %d, %s\n",
+ configname, errno, strerror(errno));
+ return -1;
+ }
+
+ status = lseek(fd, 0x10 + 4*dev->bar, SEEK_SET);
+ if (status < 0) {
+ printf("Error: configuration space lseek failed\n");
+ close(fd);
+ return -1;
+ }
+ status = read(fd, &dev->phys, 4);
+ if (status < 0) {
+ printf("Error: configuration space read failed\n");
+ close(fd);
+ return -1;
+ }
+ dev->offset = ((dev->phys & 0xFFFFFFF0) % 0x1000);
+ dev->addr = dev->maddr + dev->offset;
+ close(fd);
+ }
+
+
+ /* ------------------------------------------------------------
+ * Tests
+ * ------------------------------------------------------------
+ */
+
+ printf("\n");
+ printf("PCI debug\n");
+ printf("---------\n\n");
+ printf(" - accessing BAR%d\n", dev->bar);
+ printf(" - region size is %d-bytes\n", dev->size);
+ printf(" - offset into region is %d-bytes\n", dev->offset);
+
+ /* Display help */
+ display_help(dev);
+
+ /* Process commands */
+ parse_command(dev);
+
+ /* Cleanly shutdown */
+ munmap(dev->maddr, dev->size);
+ close(dev->fd);
+ return 0;
+}
+
+void
+parse_command(
+ device_t *dev)
+{
+ char *line;
+ int len;
+ int status;
+
+ while(1) {
+ line = readline("PCI> ");
+ /* Ctrl-D check */
+ if (line == NULL) {
+ printf("\n");
+ continue;
+ }
+ /* Empty line check */
+ len = strlen(line);
+ if (len == 0) {
+ continue;
+ }
+ /* Process the line */
+ status = process_command(dev, line);
+ if (status < 0) {
+ break;
+ }
+
+ /* Add it to the history */
+ add_history(line);
+ free(line);
+ }
+ return;
+}
+
+/*--------------------------------------------------------------------
+ * User interface
+ *--------------------------------------------------------------------
+ */
+void
+display_help(
+ device_t *dev)
+{
+ printf("\n");
+ printf(" ? Help\n");
+ printf(" d[width] addr len Display memory starting from addr\n");
+ printf(" [width]\n");
+ printf(" 8 - 8-bit access\n");
+ printf(" 16 - 16-bit access\n");
+ printf(" 32 - 32-bit access (default)\n");
+ printf(" c[width] addr val Change memory at addr to val\n");
+ printf(" e Print the endian access mode\n");
+ printf(" e[mode] Change the endian access mode\n");
+ printf(" [mode]\n");
+ printf(" b - big-endian (default)\n");
+ printf(" l - little-endian\n");
+ printf(" f[width] addr val len inc Fill memory\n");
+ printf(" addr - start address\n");
+ printf(" val - start value\n");
+ printf(" len - length (in bytes)\n");
+ printf(" inc - increment (defaults to 1)\n");
+ printf(" q Quit\n");
+ printf("\n Notes:\n");
+ printf(" 1. addr, len, and val are interpreted as hex values\n");
+ printf(" addresses are always byte based\n");
+ printf("\n");
+}
+
+int process_command(device_t *dev, char *cmd)
+{
+ if (cmd[0] == '\0') {
+ return 0;
+ }
+ switch (cmd[0]) {
+ case '?':
+ display_help(dev);
+ break;
+ case 'c':
+ case 'C':
+ return change_mem(dev, cmd);
+ case 'd':
+ case 'D':
+ return display_mem(dev, cmd);
+ case 'e':
+ case 'E':
+ return change_endian(dev, cmd);
+ case 'f':
+ case 'F':
+ return fill_mem(dev, cmd);
+ case 'q':
+ case 'Q':
+ return -1;
+ default:
+ break;
+ }
+ return 0;
+}
+
+int display_mem(device_t *dev, char *cmd)
+{
+ int width = 32;
+ int addr = 0;
+ int len = 0;
+ int status;
+ int i;
+ unsigned char d8;
+ unsigned short d16;
+ unsigned int d32;
+
+ /* d, d8, d16, d32 */
+ if (cmd[1] == ' ') {
+ status = sscanf(cmd, "%*c %x %x", &addr, &len);
+ if (status != 2) {
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ return 0;
+ }
+ } else {
+ status = sscanf(cmd, "%*c%d %x %x", &width, &addr, &len);
+ if (status != 3) {
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ return 0;
+ }
+ }
+ if (addr > dev->size) {
+ printf("Error: invalid address (maximum allowed is %.8X\n", dev->size);
+ return 0;
+ }
+ /* Length is in bytes */
+ if ((addr + len) > dev->size) {
+ /* Truncate */
+ len = dev->size;
+ }
+ switch (width) {
+ case 8:
+ for (i = 0; i < len; i++) {
+ if ((i%16) == 0) {
+ printf("\n%.8X: ", addr+i);
+ }
+ d8 = read_8(dev, addr+i);
+ printf("%.2X ", d8);
+ }
+ printf("\n");
+ break;
+ case 16:
+ for (i = 0; i < len; i+=2) {
+ if ((i%16) == 0) {
+ printf("\n%.8X: ", addr+i);
+ }
+ if (big_endian == 0) {
+ d16 = read_le16(dev, addr+i);
+ } else {
+ d16 = read_be16(dev, addr+i);
+ }
+ printf("%.4X ", d16);
+ }
+ printf("\n");
+ break;
+ case 32:
+ for (i = 0; i < len; i+=4) {
+ if ((i%16) == 0) {
+ printf("\n%.8X: ", addr+i);
+ }
+ if (big_endian == 0) {
+ d32 = read_le32(dev, addr+i);
+ } else {
+ d32 = read_be32(dev, addr+i);
+ }
+ printf("%.8X ", d32);
+ }
+ printf("\n");
+ break;
+ default:
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ break;
+ }
+ printf("\n");
+ return 0;
+}
+
+int change_mem(device_t *dev, char *cmd)
+{
+ int width = 32;
+ int addr = 0;
+ int status;
+ unsigned char d8;
+ unsigned short d16;
+ unsigned int d32;
+
+ /* c, c8, c16, c32 */
+ if (cmd[1] == ' ') {
+ status = sscanf(cmd, "%*c %x %x", &addr, &d32);
+ if (status != 2) {
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ return 0;
+ }
+ } else {
+ status = sscanf(cmd, "%*c%d %x %x", &width, &addr, &d32);
+ if (status != 3) {
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ return 0;
+ }
+ }
+ if (addr > dev->size) {
+ printf("Error: invalid address (maximum allowed is %.8X\n", dev->size);
+ return 0;
+ }
+ switch (width) {
+ case 8:
+ d8 = (unsigned char)d32;
+ write_8(dev, addr, d8);
+ break;
+ case 16:
+ d16 = (unsigned short)d32;
+ if (big_endian == 0) {
+ write_le16(dev, addr, d16);
+ } else {
+ write_be16(dev, addr, d16);
+ }
+ break;
+ case 32:
+ if (big_endian == 0) {
+ write_le32(dev, addr, d32);
+ } else {
+ write_be32(dev, addr, d32);
+ }
+ break;
+ default:
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ break;
+ }
+ return 0;
+}
+
+int fill_mem(device_t *dev, char *cmd)
+{
+ int width = 32;
+ int addr = 0;
+ int len = 0;
+ int inc = 0;
+ int status;
+ int i;
+ unsigned char d8;
+ unsigned short d16;
+ unsigned int d32;
+
+ /* c, c8, c16, c32 */
+ if (cmd[1] == ' ') {
+ status = sscanf(cmd, "%*c %x %x %x %x", &addr, &d32, &len, &inc);
+ if ((status != 3) && (status != 4)) {
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ return 0;
+ }
+ if (status == 3) {
+ inc = 1;
+ }
+ } else {
+ status = sscanf(cmd, "%*c%d %x %x %x %x", &width, &addr, &d32, &len, &inc);
+ if ((status != 3) && (status != 4)) {
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ return 0;
+ }
+ if (status == 4) {
+ inc = 1;
+ }
+ }
+ if (addr > dev->size) {
+ printf("Error: invalid address (maximum allowed is %.8X\n", dev->size);
+ return 0;
+ }
+ /* Length is in bytes */
+ if ((addr + len) > dev->size) {
+ /* Truncate */
+ len = dev->size;
+ }
+ switch (width) {
+ case 8:
+ for (i = 0; i < len; i++) {
+ d8 = (unsigned char)(d32 + i*inc);
+ write_8(dev, addr+i, d8);
+ }
+ break;
+ case 16:
+ for (i = 0; i < len/2; i++) {
+ d16 = (unsigned short)(d32 + i*inc);
+ if (big_endian == 0) {
+ write_le16(dev, addr+2*i, d16);
+ } else {
+ write_be16(dev, addr+2*i, d16);
+ }
+ }
+ break;
+ case 32:
+ for (i = 0; i < len/4; i++) {
+ if (big_endian == 0) {
+ write_le32(dev, addr+4*i, d32 + i*inc);
+ } else {
+ write_be32(dev, addr+4*i, d32 + i*inc);
+ }
+ }
+ break;
+ default:
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ break;
+ }
+ return 0;
+}
+
+int change_endian(device_t *dev, char *cmd)
+{
+ char endian = 0;
+ int status;
+
+ /* e, el, eb */
+ status = sscanf(cmd, "%*c%c", &endian);
+ if (status < 0) {
+ /* Display the current setting */
+ if (big_endian == 0) {
+ printf("Endian mode: little-endian\n");
+ } else {
+ printf("Endian mode: big-endian\n");
+ }
+ return 0;
+ } else if (status == 1) {
+ switch (endian) {
+ case 'b':
+ big_endian = 1;
+ break;
+ case 'l':
+ big_endian = 0;
+ break;
+ default:
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ break;
+ }
+ } else {
+ printf("Syntax error (use ? for help)\n");
+ /* Don't break out of command processing loop */
+ }
+ return 0;
+}
+
+/* ----------------------------------------------------------------
+ * Raw pointer read/write access
+ * ----------------------------------------------------------------
+ */
+static void
+write_8(
+ device_t *dev,
+ unsigned int addr,
+ unsigned char data)
+{
+ *(volatile unsigned char *)(dev->addr + addr) = data;
+ msync((void *)(dev->addr + addr), 1, MS_SYNC | MS_INVALIDATE);
+}
+
+static unsigned char
+read_8(
+ device_t *dev,
+ unsigned int addr)
+{
+ return *(volatile unsigned char *)(dev->addr + addr);
+}
+
+static void
+write_le16(
+ device_t *dev,
+ unsigned int addr,
+ unsigned short int data)
+{
+ if (__BYTE_ORDER != __LITTLE_ENDIAN) {
+ data = bswap_16(data);
+ }
+ *(volatile unsigned short int *)(dev->addr + addr) = data;
+ msync((void *)(dev->addr + addr), 2, MS_SYNC | MS_INVALIDATE);
+}
+
+static unsigned short int
+read_le16(
+ device_t *dev,
+ unsigned int addr)
+{
+ unsigned int data = *(volatile unsigned short int *)(dev->addr + addr);
+ if (__BYTE_ORDER != __LITTLE_ENDIAN) {
+ data = bswap_16(data);
+ }
+ return data;
+}
+
+static void
+write_be16(
+ device_t *dev,
+ unsigned int addr,
+ unsigned short int data)
+{
+ if (__BYTE_ORDER == __LITTLE_ENDIAN) {
+ data = bswap_16(data);
+ }
+ *(volatile unsigned short int *)(dev->addr + addr) = data;
+ msync((void *)(dev->addr + addr), 2, MS_SYNC | MS_INVALIDATE);
+}
+
+static unsigned short int
+read_be16(
+ device_t *dev,
+ unsigned int addr)
+{
+ unsigned int data = *(volatile unsigned short int *)(dev->addr + addr);
+ if (__BYTE_ORDER == __LITTLE_ENDIAN) {
+ data = bswap_16(data);
+ }
+ return data;
+}
+
+static void
+write_le32(
+ device_t *dev,
+ unsigned int addr,
+ unsigned int data)
+{
+ if (__BYTE_ORDER != __LITTLE_ENDIAN) {
+ data = bswap_32(data);
+ }
+ *(volatile unsigned int *)(dev->addr + addr) = data;
+ msync((void *)(dev->addr + addr), 4, MS_SYNC | MS_INVALIDATE);
+}
+
+static unsigned int
+read_le32(
+ device_t *dev,
+ unsigned int addr)
+{
+ unsigned int data = *(volatile unsigned int *)(dev->addr + addr);
+ if (__BYTE_ORDER != __LITTLE_ENDIAN) {
+ data = bswap_32(data);
+ }
+ return data;
+}
+
+static void
+write_be32(
+ device_t *dev,
+ unsigned int addr,
+ unsigned int data)
+{
+ if (__BYTE_ORDER == __LITTLE_ENDIAN) {
+ data = bswap_32(data);
+ }
+ *(volatile unsigned int *)(dev->addr + addr) = data;
+ msync((void *)(dev->addr + addr), 4, MS_SYNC | MS_INVALIDATE);
+}
+
+static unsigned int
+read_be32(
+ device_t *dev,
+ unsigned int addr)
+{
+ unsigned int data = *(volatile unsigned int *)(dev->addr + addr);
+ if (__BYTE_ORDER == __LITTLE_ENDIAN) {
+ data = bswap_32(data);
+ }
+ return data;
+}
+
hooks/post-receive
--
armadeus
|
|
From: Julien B a. A. <ar...@us...> - 2015-01-30 11:18:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 3a7d49312fc14e5a1362343e70bd5c3ff148e1e2 (commit)
from bd2171f86246b8348a2568263e263db8c098823c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3a7d49312fc14e5a1362343e70bd5c3ff148e1e2
Author: Julien Boibessot <jul...@ar...>
Date: Fri Jan 30 12:18:15 2015 +0100
[U-BOOT] 2014.07: APF6: add CONFIG_ZERO_BOOTDELAY_CHECK, officialize update_rootfs and cleanup a little the default config
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf6/apf6-u-boot-2014.07.h | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/buildroot/target/device/armadeus/apf6/apf6-u-boot-2014.07.h b/buildroot/target/device/armadeus/apf6/apf6-u-boot-2014.07.h
index 2fbd45c..4d0aabc 100644
--- a/buildroot/target/device/armadeus/apf6/apf6-u-boot-2014.07.h
+++ b/buildroot/target/device/armadeus/apf6/apf6-u-boot-2014.07.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2013 Armadeus Systems
+ * Copyright (C) 2013-2015 Armadeus Systems
*
* Configuration settings for the APF6.
*
@@ -16,7 +16,7 @@
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION 4
+#define CONFIG_ENV_VERSION 5
#define CONFIG_BOARD_NAME apf6
/* SPL */
@@ -79,6 +79,7 @@
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_BOOTDELAY 5
+#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
@@ -137,17 +138,16 @@
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_MASS_STORAGE
-#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_USBDOWNLOAD_GADGET
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
-#define CONFIG_G_DNL_MANUFACTURER "Armadeus Systems"
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525
+#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
+#define CONFIG_G_DNL_MANUFACTURER "Armadeus Systems"
/* PCIE */
#define CONFIG_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCIE_IMX
-#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(6, 2)
/* FPGA */
#define CONFIG_FPGA_COUNT 1
@@ -249,7 +249,7 @@
"fi; " \
"fi;\0" \
"update_rootfs=run download_rootfs flash_rootfs\0" \
- "update_all=run update_kernel update_dtb update_uboot\0" \
+ "update_all=run update_kernel update_rootfs update_dtb update_uboot\0" \
"loadzimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${board_name}-linux.bin\0" \
"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \
"addipargs=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
hooks/post-receive
--
armadeus
|
|
From: Julien B a. A. <ar...@us...> - 2015-01-28 11:38:18
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via bd2171f86246b8348a2568263e263db8c098823c (commit)
via f7cda8966a8f57544a27a65c2db1f262959788ca (commit)
via c2c14ace1a8491c15b3b73e276f990c55ff8fbf1 (commit)
from 16339cfb2fad63503d443a72f18475ff2d36cc7a (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit bd2171f86246b8348a2568263e263db8c098823c
Author: Philippe Reynes <tr...@gm...>
Date: Sat Jan 24 22:34:43 2015 +0100
[LINUX] 3.14: apf27/28/51/6: move to 3.14.29
commit f7cda8966a8f57544a27a65c2db1f262959788ca
Author: Philippe Reynes <tr...@gm...>
Date: Sat Jan 24 22:34:42 2015 +0100
3.12: move to 3.12.36
commit c2c14ace1a8491c15b3b73e276f990c55ff8fbf1
Author: Philippe Reynes <tr...@gm...>
Date: Sat Jan 24 22:34:41 2015 +0100
3.10: move to 3.10.65
-----------------------------------------------------------------------
Summary of changes:
...x-3.10.64.config => apf27-linux-3.10.65.config} | 0
...x-3.12.35.config => apf27-linux-3.12.36.config} | 0
...x-3.14.28.config => apf27-linux-3.14.29.config} | 0
...x-3.10.64.config => apf28-linux-3.10.65.config} | 0
...x-3.12.35.config => apf28-linux-3.12.36.config} | 0
...x-3.14.28.config => apf28-linux-3.14.29.config} | 0
...x-3.10.64.config => apf51-linux-3.10.65.config} | 0
...x-3.12.35.config => apf51-linux-3.12.36.config} | 0
...x-3.14.28.config => apf51-linux-3.14.29.config} | 0
...ux-3.14.28.config => apf6-linux-3.14.29.config} | 0
patches/linux/{3.10.64 => 3.10.65} | 0
patches/linux/{3.12.35 => 3.12.36} | 0
patches/linux/{3.14.28 => 3.14.29} | 0
13 files changed, 0 insertions(+), 0 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.10.64.config => apf27-linux-3.10.65.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.12.35.config => apf27-linux-3.12.36.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.14.28.config => apf27-linux-3.14.29.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.10.64.config => apf28-linux-3.10.65.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.12.35.config => apf28-linux-3.12.36.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.14.28.config => apf28-linux-3.14.29.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.10.64.config => apf51-linux-3.10.65.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.12.35.config => apf51-linux-3.12.36.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.14.28.config => apf51-linux-3.14.29.config} (100%)
rename buildroot/target/device/armadeus/apf6/{apf6-linux-3.14.28.config => apf6-linux-3.14.29.config} (100%)
rename patches/linux/{3.10.64 => 3.10.65} (100%)
rename patches/linux/{3.12.35 => 3.12.36} (100%)
rename patches/linux/{3.14.28 => 3.14.29} (100%)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.64.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.65.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.10.64.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.10.65.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.12.35.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.12.36.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.12.35.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.12.36.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.14.28.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.14.29.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.14.28.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.14.29.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.64.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.65.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.10.64.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.10.65.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.12.35.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.12.36.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.12.35.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.12.36.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.14.28.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.14.29.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.14.28.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.14.29.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.64.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.65.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.10.64.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.10.65.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.12.35.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.12.36.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.12.35.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.12.36.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.14.28.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.14.29.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.14.28.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.14.29.config
diff --git a/buildroot/target/device/armadeus/apf6/apf6-linux-3.14.28.config b/buildroot/target/device/armadeus/apf6/apf6-linux-3.14.29.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf6/apf6-linux-3.14.28.config
rename to buildroot/target/device/armadeus/apf6/apf6-linux-3.14.29.config
diff --git a/patches/linux/3.10.64 b/patches/linux/3.10.65
similarity index 100%
rename from patches/linux/3.10.64
rename to patches/linux/3.10.65
diff --git a/patches/linux/3.12.35 b/patches/linux/3.12.36
similarity index 100%
rename from patches/linux/3.12.35
rename to patches/linux/3.12.36
diff --git a/patches/linux/3.14.28 b/patches/linux/3.14.29
similarity index 100%
rename from patches/linux/3.14.28
rename to patches/linux/3.14.29
hooks/post-receive
--
armadeus
|
|
From: Julien B a. A. <ar...@us...> - 2015-01-28 10:27:07
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 16339cfb2fad63503d443a72f18475ff2d36cc7a (commit)
from e70adcd6e47c5cd7bb5c89ada2ac341ea3abaea8 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 16339cfb2fad63503d443a72f18475ff2d36cc7a
Author: Julien Boibessot <jul...@ar...>
Date: Wed Jan 28 11:26:32 2015 +0100
[LINUX] 2.6.29: Fixes division by zero when lots of processes are created
-----------------------------------------------------------------------
Summary of changes:
.../2.6.29/443-armadeus-fixes-div-by-zero.patch | 41 ++++++++++++++++++++
1 files changed, 41 insertions(+), 0 deletions(-)
create mode 100644 patches/linux/2.6.29/443-armadeus-fixes-div-by-zero.patch
diff --git a/patches/linux/2.6.29/443-armadeus-fixes-div-by-zero.patch b/patches/linux/2.6.29/443-armadeus-fixes-div-by-zero.patch
new file mode 100644
index 0000000..71e1951
--- /dev/null
+++ b/patches/linux/2.6.29/443-armadeus-fixes-div-by-zero.patch
@@ -0,0 +1,41 @@
+Fixes kernel oops (division by zero), under certain circumstances (lot of
+processes created).
+
+To test it:
+ #/bin/sh
+
+ while true; do
+ usleep 10000
+ toto=$(date)
+ toto=`date`
+ echo $toto > /dev/null
+ done
+
+Signed-off-by: Julien Boibessot <jul...@ar...>
+
+Index: linux-2.6.29.6/kernel/sched.c
+===================================================================
+--- linux-2.6.29.6.orig/kernel/sched.c 2009-07-03 01:41:20.000000000 +0200
++++ linux-2.6.29.6/kernel/sched.c 2015-01-22 10:24:43.078805869 +0100
+@@ -1288,13 +1288,19 @@
+ struct load_weight *lw)
+ {
+ u64 tmp;
++ unsigned long tmp2;
+
+ if (!lw->inv_weight) {
+ if (BITS_PER_LONG > 32 && unlikely(lw->weight >= WMULT_CONST))
+ lw->inv_weight = 1;
+- else
++ else {
++ if (lw->weight+1 == 0) /* u32 overflow */
++ tmp2 = lw->weight;
++ else
++ tmp2 = lw->weight+1;
+ lw->inv_weight = 1 + (WMULT_CONST-lw->weight/2)
+- / (lw->weight+1);
++ / tmp2;
++ }
+ }
+
+ tmp = (u64)delta_exec * weight;
hooks/post-receive
--
armadeus
|
|
From: Julien B a. A. <ar...@us...> - 2015-01-23 16:01:06
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via e70adcd6e47c5cd7bb5c89ada2ac341ea3abaea8 (commit)
via e9822bba58d8a11715e92b7550a6f69241663a21 (commit)
via 600db8d81a42eaf7f94c37228cb6cafdbb92014e (commit)
from b0f81dfe42d0c1abcce9c0fd288174ec3780873f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit e70adcd6e47c5cd7bb5c89ada2ac341ea3abaea8
Author: Philippe Reynes <tr...@gm...>
Date: Thu Jan 22 19:47:37 2015 +0100
[LINUX] apf27/28/51: 3.17: move to 3.17.8
commit e9822bba58d8a11715e92b7550a6f69241663a21
Author: Philippe Reynes <tr...@gm...>
Date: Thu Jan 22 19:47:36 2015 +0100
[LINUX] apf6/51/27/28: 3.14: move to 3.14.28
commit 600db8d81a42eaf7f94c37228cb6cafdbb92014e
Author: Philippe Reynes <tr...@gm...>
Date: Mon Jan 12 21:22:57 2015 +0100
[LINUX] apf27/28/51: 3.10: move to 3.10.64
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf6failsafe_defconfig | 2 +-
...x-3.10.63.config => apf27-linux-3.10.64.config} | 0
...x-3.14.27.config => apf27-linux-3.14.28.config} | 0
...nux-3.17.7.config => apf27-linux-3.17.8.config} | 0
...x-3.10.63.config => apf28-linux-3.10.64.config} | 0
...x-3.14.27.config => apf28-linux-3.14.28.config} | 0
...nux-3.17.7.config => apf28-linux-3.17.8.config} | 0
...x-3.10.63.config => apf51-linux-3.10.64.config} | 0
...x-3.14.27.config => apf51-linux-3.14.28.config} | 0
...nux-3.17.7.config => apf51-linux-3.17.8.config} | 0
...ux-3.14.27.config => apf6-linux-3.14.28.config} | 0
patches/linux/{3.10.63 => 3.10.64} | 0
patches/linux/{3.14.27 => 3.14.28} | 0
patches/linux/{3.17.7 => 3.17.8} | 0
14 files changed, 1 insertions(+), 1 deletions(-)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.10.63.config => apf27-linux-3.10.64.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.14.27.config => apf27-linux-3.14.28.config} (100%)
rename buildroot/target/device/armadeus/apf27/{apf27-linux-3.17.7.config => apf27-linux-3.17.8.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.10.63.config => apf28-linux-3.10.64.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.14.27.config => apf28-linux-3.14.28.config} (100%)
rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.17.7.config => apf28-linux-3.17.8.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.10.63.config => apf51-linux-3.10.64.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.14.27.config => apf51-linux-3.14.28.config} (100%)
rename buildroot/target/device/armadeus/apf51/{apf51-linux-3.17.7.config => apf51-linux-3.17.8.config} (100%)
rename buildroot/target/device/armadeus/apf6/{apf6-linux-3.14.27.config => apf6-linux-3.14.28.config} (100%)
rename patches/linux/{3.10.63 => 3.10.64} (100%)
rename patches/linux/{3.14.27 => 3.14.28} (100%)
rename patches/linux/{3.17.7 => 3.17.8} (100%)
diff --git a/buildroot/configs/apf6failsafe_defconfig b/buildroot/configs/apf6failsafe_defconfig
index bd13c00..c0a172e 100644
--- a/buildroot/configs/apf6failsafe_defconfig
+++ b/buildroot/configs/apf6failsafe_defconfig
@@ -11,7 +11,7 @@ BR2_TARGET_ARMADEUS_NR_SDRAM="2"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="512"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_VERSION=y
-BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.27"
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.14.28"
BR2_LINUX_KERNEL_PATCH="../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)failsafe-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.63.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.10.64.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.10.63.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.10.64.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.14.27.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.14.28.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.14.27.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.14.28.config
diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-3.17.7.config b/buildroot/target/device/armadeus/apf27/apf27-linux-3.17.8.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf27/apf27-linux-3.17.7.config
rename to buildroot/target/device/armadeus/apf27/apf27-linux-3.17.8.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.63.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.10.64.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.10.63.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.10.64.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.14.27.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.14.28.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.14.27.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.14.28.config
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.17.7.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.17.8.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.17.7.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.17.8.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.63.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.10.64.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.10.63.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.10.64.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.14.27.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.14.28.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.14.27.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.14.28.config
diff --git a/buildroot/target/device/armadeus/apf51/apf51-linux-3.17.7.config b/buildroot/target/device/armadeus/apf51/apf51-linux-3.17.8.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf51/apf51-linux-3.17.7.config
rename to buildroot/target/device/armadeus/apf51/apf51-linux-3.17.8.config
diff --git a/buildroot/target/device/armadeus/apf6/apf6-linux-3.14.27.config b/buildroot/target/device/armadeus/apf6/apf6-linux-3.14.28.config
similarity index 100%
rename from buildroot/target/device/armadeus/apf6/apf6-linux-3.14.27.config
rename to buildroot/target/device/armadeus/apf6/apf6-linux-3.14.28.config
diff --git a/patches/linux/3.10.63 b/patches/linux/3.10.64
similarity index 100%
rename from patches/linux/3.10.63
rename to patches/linux/3.10.64
diff --git a/patches/linux/3.14.27 b/patches/linux/3.14.28
similarity index 100%
rename from patches/linux/3.14.27
rename to patches/linux/3.14.28
diff --git a/patches/linux/3.17.7 b/patches/linux/3.17.8
similarity index 100%
rename from patches/linux/3.17.7
rename to patches/linux/3.17.8
hooks/post-receive
--
armadeus
|
|
From: Sébastien S. <ss...@us...> - 2015-01-21 08:01:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via b0f81dfe42d0c1abcce9c0fd288174ec3780873f (commit)
from ef2dcf842181edb678f6d05ba09a4419e735a9b7 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit b0f81dfe42d0c1abcce9c0fd288174ec3780873f
Author: Sébastien Szymanski <seb...@ar...>
Date: Wed Jan 21 09:05:22 2015 +0100
[AS_DEVICES] as_led: Fix comment and Armadeus name
-----------------------------------------------------------------------
Summary of changes:
target/packages/as_devices/c/as_led.c | 4 ++--
target/packages/as_devices/c/as_led.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/packages/as_devices/c/as_led.c b/target/packages/as_devices/c/as_led.c
index e22ab11..3af6fce 100644
--- a/target/packages/as_devices/c/as_led.c
+++ b/target/packages/as_devices/c/as_led.c
@@ -1,7 +1,7 @@
/*
- ** C wrapper for GPIOs usage.
+ ** C wrapper for LEDs usage.
**
- ** Copyright (C) 2013 The Armadeus Project - ARMadeus Systems
+ ** Copyright (C) 2013 The Armadeus Project - Armadeus Systems
** Sébastien Royen <seb...@ar...>
**
** This library is free software; you can redistribute it and/or
diff --git a/target/packages/as_devices/c/as_led.h b/target/packages/as_devices/c/as_led.h
index e21226a..789981a 100644
--- a/target/packages/as_devices/c/as_led.h
+++ b/target/packages/as_devices/c/as_led.h
@@ -1,5 +1,5 @@
/*
-** The ARMadeus Project
+** The Armadeus Project
**
** Copyright (C) 2013 The armadeus systems team
** Sébastien Royen <seb...@ar...>
hooks/post-receive
--
armadeus
|
|
From: Sébastien S. <ss...@us...> - 2015-01-19 13:29:11
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via ef2dcf842181edb678f6d05ba09a4419e735a9b7 (commit)
from 805805ea1f7e79f08b40aabd89cc69db3b45ffe5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ef2dcf842181edb678f6d05ba09a4419e735a9b7
Author: Sébastien Szymanski <seb...@ar...>
Date: Mon Jan 19 14:31:35 2015 +0100
[SCRIPT] quiltify.sh: do not try to delete or remove target dir if
it does not exist.
Does it properly this time... :)
-----------------------------------------------------------------------
Summary of changes:
scripts/quiltify.sh | 24 +++++++++++++-----------
1 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/scripts/quiltify.sh b/scripts/quiltify.sh
index aab7b69..5329d1f 100755
--- a/scripts/quiltify.sh
+++ b/scripts/quiltify.sh
@@ -143,17 +143,19 @@ if [ "$answer" == "y" ] || [ "$answer" == "yes" ]; then
fi
# Move or delete current XXX dir
-if [ "$QUILT_TARGET_NAME" != "Buildroot" ] && [ -e "$QUILT_TARGET_DIR" ]; then
- ask_user "Rename or delete the current $QUILT_TARGET_NAME directory: $QUILT_TARGET_DIR \n?? (R/d)"
- EXT=`date +%Y_%m_%d_%Hh%M`
- if [ "$answer" == "d" ]; then
- echo -n "Deleting current $QUILT_TARGET_NAME dir..."
- rm -rf $QUILT_TARGET_DIR
- echo "done"
- else
- echo "Renaming $QUILT_TARGET_DIR"
- echo " to " "$QUILT_TARGET_DIR"."$EXT"
- mv $QUILT_TARGET_DIR "$QUILT_TARGET_DIR"."$EXT"
+if [ "$QUILT_TARGET_NAME" != "Buildroot" ]; then
+ if [ -d "$QUILT_TARGET_DIR" ]; then
+ ask_user "Rename or delete the current $QUILT_TARGET_NAME directory: $QUILT_TARGET_DIR \n?? (R/d)"
+ EXT=`date +%Y_%m_%d_%Hh%M`
+ if [ "$answer" == "d" ]; then
+ echo -n "Deleting current $QUILT_TARGET_NAME dir..."
+ rm -rf $QUILT_TARGET_DIR
+ echo "done"
+ else
+ echo "Renaming $QUILT_TARGET_DIR"
+ echo " to " "$QUILT_TARGET_DIR"."$EXT"
+ mv $QUILT_TARGET_DIR "$QUILT_TARGET_DIR"."$EXT"
+ fi
fi
else # For Buildroot
rm -f $QUILT_TARGET_DIR/.patched
hooks/post-receive
--
armadeus
|