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From: <ca...@us...> - 2008-05-15 14:53:28
|
Revision: 806
http://armadeus.svn.sourceforge.net/armadeus/?rev=806&view=rev
Author: carbure
Date: 2008-05-15 07:53:02 -0700 (Thu, 15 May 2008)
Log Message:
-----------
[BUILDROOT PACKAGE] Adding an usefull frame buffer grabber package (fbgrab)
Added Paths:
-----------
trunk/patches/041-buildroot-fbgrab.diff
Added: trunk/patches/041-buildroot-fbgrab.diff
===================================================================
--- trunk/patches/041-buildroot-fbgrab.diff (rev 0)
+++ trunk/patches/041-buildroot-fbgrab.diff 2008-05-15 14:53:02 UTC (rev 806)
@@ -0,0 +1,10 @@
+--- buildroot/package/Config.org 2008-05-15 16:01:44.000000000 +0200
++++ buildroot/package/Config.in 2008-05-15 16:02:59.000000000 +0200
+@@ -316,6 +316,7 @@ comment "busybox graphic applications"
+ comment "--> (May be broken in busybox)"
+ source "package/fbv/Config.in"
+ source "package/fbset/Config.in"
++source "package/fbgrab/Config.in"
+
+ comment "other GUIs"
+ source "package/qte/Config.in"
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <ca...@us...> - 2008-05-15 14:19:35
|
Revision: 805
http://armadeus.svn.sourceforge.net/armadeus/?rev=805&view=rev
Author: carbure
Date: 2008-05-15 07:19:32 -0700 (Thu, 15 May 2008)
Log Message:
-----------
[BUILDROOT PACKAGE] Adding an usefull frame buffer grabber package (fbgrab)
Added Paths:
-----------
trunk/buildroot/package/fbgrab/
trunk/buildroot/package/fbgrab/Config.in
trunk/buildroot/package/fbgrab/fbgrab-1.0.patch
trunk/buildroot/package/fbgrab/fbgrab.mk
Added: trunk/buildroot/package/fbgrab/Config.in
===================================================================
--- trunk/buildroot/package/fbgrab/Config.in (rev 0)
+++ trunk/buildroot/package/fbgrab/Config.in 2008-05-15 14:19:32 UTC (rev 805)
@@ -0,0 +1,10 @@
+config BR2_PACKAGE_FBGRAB
+ bool "fbgrab"
+ default n
+ help
+ FBGrab is a framebuffer screenshot program,
+ capturing the linux frambuffer and converting
+ it to a png-picture.
+
+ http://hem.bredband.net/gmogmo/fbgrab/
+
Added: trunk/buildroot/package/fbgrab/fbgrab-1.0.patch
===================================================================
--- trunk/buildroot/package/fbgrab/fbgrab-1.0.patch (rev 0)
+++ trunk/buildroot/package/fbgrab/fbgrab-1.0.patch 2008-05-15 14:19:32 UTC (rev 805)
@@ -0,0 +1,20 @@
+--- fbgrab-1.0.org/Makefile 2008-05-15 14:30:23.000000000 +0200
++++ fbgrab-1.0/Makefile 2008-05-15 14:31:25.000000000 +0200
+@@ -4,13 +4,8 @@
+ ###
+
+ fbgrab: fbgrab.c
+- splint +posixlib fbgrab.c
+- gcc -g -Wall fbgrab.c -lpng -lz -o fbgrab
+-
+-install:
+- strip fbgrab
+- install fbgrab /usr/bin/fbgrab
+- install fbgrab.1.man /usr/man/man1/fbgrab.1
++ $(CC) -c $(CFLAGS) $(INCLUDES) -o fbgrab fbgrab.c
+
+ clean:
+- rm -f fbgrab *~ \#*\#
+\ No newline at end of file
++ rm -f fbgrab *~ \#*\#
++
Added: trunk/buildroot/package/fbgrab/fbgrab.mk
===================================================================
--- trunk/buildroot/package/fbgrab/fbgrab.mk (rev 0)
+++ trunk/buildroot/package/fbgrab/fbgrab.mk 2008-05-15 14:19:32 UTC (rev 805)
@@ -0,0 +1,48 @@
+#############################################################
+#
+# FBGRAB
+#
+#############################################################
+FBGRAB_VERSION:=1.0
+FBGRAB_SOURCE:=fbgrab-$(FBGRAB_VERSION).tar.gz
+FBGRAB_SITE:=http://hem.bredband.net/gmogmo/fbgrab/
+FBGRAB_DIR:=$(BUILD_DIR)/fbgrab-$(FBGRAB_VERSION)
+FBGRAB_CAT:=$(ZCAT)
+FBGRAB_BINARY:=fbgrab
+FBGRAB_TARGET_BINARY:=usr/bin/$(FBGRAB_BINARY)
+
+$(DL_DIR)/$(FBGRAB_SOURCE):
+ $(WGET) -P $(DL_DIR) $(FBGRAB_SITE)/$(FBGRAB_SOURCE)
+
+$(FBGRAB_DIR)/.unpacked: $(DL_DIR)/$(FBGRAB_SOURCE)
+ $(FBGRAB_CAT) $(DL_DIR)/$(FBGRAB_SOURCE) | tar -C $(BUILD_DIR) $(TAR_OPTIONS) -
+ toolchain/patch-kernel.sh $(FBGRAB_DIR) package/fbgrab/ fbgrab-$(FBGRAB_VERSION)\*.patch\*
+ touch $@
+
+$(FBGRAB_DIR)/$(FBGRAB_BINARY): $(FBGRAB_DIR)/.unpacked
+ $(MAKE) $(TARGET_CONFIGURE_OPTS) -C $(FBGRAB_DIR)
+ touch -c $@
+
+$(TARGET_DIR)/$(FBGRAB_TARGET_BINARY): $(FBGRAB_DIR)/$(FBGRAB_BINARY)
+ $(INSTALL) -m 755 $(FBGRAB_DIR)/$(FBGRAB_BINARY) $(TARGET_DIR)/$(FBGRAB_TARGET_BINARY)
+ -$(STRIPCMD) $(STRIP_STRIP_UNNEEDED) $(TARGET_DIR)/$(FBGRAB_TARGET_BINARY)
+ touch -c $@
+
+fbgrab: uclibc libpng $(TARGET_DIR)/$(FBGRAB_TARGET_BINARY)
+
+fbgrab-clean:
+ rm -f $(TARGET_DIR)/$(FBGRAB_TARGET_BINARY)
+ -$(MAKE) -C $(FBGRAB_DIR) clean
+
+fbgrab-dirclean:
+ rm -rf $(FBGRAB_DIR)
+
+#############################################################
+#
+# Toplevel Makefile options
+#
+#############################################################
+ifeq ($(strip $(BR2_PACKAGE_FBGRAB)),y)
+TARGETS+=fbgrab
+endif
+
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <th...@us...> - 2008-05-08 12:56:53
|
Revision: 804
http://armadeus.svn.sourceforge.net/armadeus/?rev=804&view=rev
Author: thom25
Date: 2008-05-08 05:56:44 -0700 (Thu, 08 May 2008)
Log Message:
-----------
allow 32bits access
Modified Paths:
--------------
trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c
trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c
Modified: trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c
===================================================================
--- trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c 2008-05-08 12:00:06 UTC (rev 803)
+++ trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c 2008-05-08 12:56:44 UTC (rev 804)
@@ -32,17 +32,20 @@
ssize_t fpgaaccess_read(struct file *fildes, char __user *buff,
size_t count, loff_t *offp){
struct fpgaaccess_dev *sdev = fildes->private_data;
- u16 data=0;
+ u32 data=0;
if(*offp >= FPGA_SIZE || ((*offp)%2 != 0)){ /* offset must be pair */
return 0;
}
- if(count != 2) /* only one word can be wrote (two bytes)*/
- count = 2;
+ if(count > 4) /* 32bits max*/
+ count = 4;
- data = ioread16(sdev->fpga_virtual_base_address + *offp);
-
+ if (count == 2)
+ data = ioread16(sdev->fpga_virtual_base_address + *offp);
+ else
+ data = ioread32(sdev->fpga_virtual_base_address + *offp);
+
/* return data for user */
if(copy_to_user(buff,&data,count)){
printk(KERN_WARNING "read : copy to user data error\n");
@@ -54,21 +57,24 @@
ssize_t fpgaaccess_write(struct file *fildes, const char __user *
buff,size_t count, loff_t *offp){
struct fpgaaccess_dev *sdev = fildes->private_data;
- u16 data=0;
+ u32 data=0;
if(*offp >= FPGA_SIZE || ((*offp)%2 != 0)){ /* offset must be pair */
return 0;
}
- if(count != 2) /* only one word can be wrote (two bytes)*/
- count = 2;
+ if(count > 4) /* 32 bits max)*/
+ count = 4;
if(copy_from_user(&data,buff,count)){
printk(KERN_WARNING "write : copy from user error\n");
return -EFAULT;
}
- iowrite16(data,sdev->fpga_virtual_base_address + *offp);
+ if (count == 2)
+ iowrite16(data,sdev->fpga_virtual_base_address + *offp);
+ else
+ iowrite32(data,sdev->fpga_virtual_base_address + *offp);
return count;
}
Modified: trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c
===================================================================
--- trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c 2008-05-08 12:00:06 UTC (rev 803)
+++ trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c 2008-05-08 12:56:44 UTC (rev 804)
@@ -1,5 +1,5 @@
/************************************************************************
- * a program to write/read values on fpga address map
+ * a program to write/read 16/32bits values on fpga address map
* 7 april 2008
* fpgaregs.c
*
@@ -42,50 +42,66 @@
#include <string.h>
+#define WORD_ACCESS (2)
+#define LONG_ACCESS (4)
+
+void displayResult(char* text, unsigned int accesstype, unsigned int value, unsigned int address)
+{
+ if( accesstype == WORD_ACCESS )
+ printf("%s %04x at %08x\n",text, (unsigned short)value,address);
+ else
+ printf("%s %08x at %08x\n",text, value,address);
+}
+
+
int main(int argc, char *argv[])
{
- unsigned int address;
- unsigned short value;
- int retval, error = 0;
- int ffpga;
-
- if((argc < 2) || (argc > 3)){
- perror("invalid arguments number\nfpgaregs fpga_reg_add [value].\n Ex: fpgaregs 0x10 0x0008");
+ unsigned short address;
+ unsigned int value ;
+ int retval, error = EXIT_SUCCESS;
+ int ffpga, accesstype = LONG_ACCESS;
+
+ if((argc < 3) || (argc > 4)){
+ printf("invalid arguments number\nfpgaregs [w,l] fpga_reg_add [value].\n\tw: word access, l: long access\n\
+\tEx: fpgaregs w 0x10 0x1234, fpgaregs l 0x10 0x12345678\n");
exit(EXIT_FAILURE);
}
ffpga=open("/dev/fpgaaccess",O_RDWR);
if(ffpga<0){
- perror("can't open file /dev/fpgaaccess\n");
+ printf("can't open file /dev/fpgaaccess\n");
exit(EXIT_FAILURE);
}
- address = (unsigned int)strtol(argv[1], (char **)NULL, 16);
+ address = (unsigned int)strtol(argv[2], (char **)NULL, 16);
- if(argc<2){
- perror("invalid command line");
+ if(argc<3){
+ printf("invalid command line");
}
- else {
+ else {
+ if( *(argv[1]) == 'w' )
+ accesstype = WORD_ACCESS;
+
/* write value at address */
- if(argc == 3){
- value = strtol(argv[2], (char **)NULL, 16);
- retval = pwrite(ffpga,(void *)&value,2,address);
+ if(argc == 4){
+ value = strtoul(argv[3], (char **)NULL, 16);
+ retval = pwrite(ffpga,(void *)&value,accesstype,address);
if(retval<0){
- perror("write error\n");
+ printf("write error\n");
error = EXIT_FAILURE;
}
else
- printf("Wrote %04x at %08x\n",value,address);
+ displayResult("Write", accesstype, value, address);
/* read address value */
- }else if(argc == 2){
- retval = pread(ffpga,(void *)&value,2,address);
+ }else if(argc == 3){
+ retval = pread(ffpga,(void *)&value,accesstype,address);
if(retval<0){
perror("Read error\n");
error = EXIT_FAILURE;
}
else
- printf("Read %04x at %08x\n",value,address);
+ displayResult("Read", accesstype, value, address);
}
}
close(ffpga);
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <th...@us...> - 2008-05-08 12:00:08
|
Revision: 803
http://armadeus.svn.sourceforge.net/armadeus/?rev=803&view=rev
Author: thom25
Date: 2008-05-08 05:00:06 -0700 (Thu, 08 May 2008)
Log Message:
-----------
fix bug when writing 16bits values in fpgaregs.c
fix hard coded path in Makefile
remove specific lines in Makefile
fix warning in fpgaaccess.c
Modified Paths:
--------------
trunk/target/linux/modules/fpga/fpgaaccess/Makefile
trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c
trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c
Modified: trunk/target/linux/modules/fpga/fpgaaccess/Makefile
===================================================================
--- trunk/target/linux/modules/fpga/fpgaaccess/Makefile 2008-05-04 12:12:52 UTC (rev 802)
+++ trunk/target/linux/modules/fpga/fpgaaccess/Makefile 2008-05-08 12:00:06 UTC (rev 803)
@@ -22,12 +22,9 @@
default:
$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
- -cp fpgaaccess.ko /tftpboot/
fpgaregs: fpgaregs.c
- ~/armadeus/buildroot/build_arm/staging_dir/bin/arm-linux-gcc -Wall fpgaregs.c -o fpgaregs
- chmod 755 fpgaregs
- cp fpgaregs /tftpboot/
+ $(BASE_DIR)build_arm/staging_dir/bin/arm-linux-gcc -Wall fpgaregs.c -o fpgaregs
clean:
rm -f *.*o \
Modified: trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c
===================================================================
--- trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c 2008-05-04 12:12:52 UTC (rev 802)
+++ trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c 2008-05-08 12:00:06 UTC (rev 803)
@@ -44,7 +44,7 @@
data = ioread16(sdev->fpga_virtual_base_address + *offp);
/* return data for user */
- if(copy_to_user(buff,&data,2)){
+ if(copy_to_user(buff,&data,count)){
printk(KERN_WARNING "read : copy to user data error\n");
return -EFAULT;
}
@@ -63,14 +63,14 @@
if(count != 2) /* only one word can be wrote (two bytes)*/
count = 2;
- if(copy_from_user(&data,buff,2)){
+ if(copy_from_user(&data,buff,count)){
printk(KERN_WARNING "write : copy from user error\n");
return -EFAULT;
}
iowrite16(data,sdev->fpga_virtual_base_address + *offp);
- return 2;
+ return count;
}
int fpgaaccess_open(struct inode *inode, struct file *filp){
@@ -92,7 +92,6 @@
static int __init fpgaaccess_init(void){
int result;
int fpgaaccess_major,fpgaaccess_minor;
- u16 data;
struct fpgaaccess_dev *sdev;
fpgaaccess_major = 250;
Modified: trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c
===================================================================
--- trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c 2008-05-04 12:12:52 UTC (rev 802)
+++ trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c 2008-05-08 12:00:06 UTC (rev 803)
@@ -41,18 +41,16 @@
/* converting string */
#include <string.h>
-int ffpga;
int main(int argc, char *argv[])
{
- unsigned short address;
+ unsigned int address;
unsigned short value;
- int retval;
+ int retval, error = 0;
+ int ffpga;
- printf( "Testing button driver\n" );
-
if((argc < 2) || (argc > 3)){
- perror("invalid arguments number\nfpgaregs fpga_reg_add [value]\n");
+ perror("invalid arguments number\nfpgaregs fpga_reg_add [value].\n Ex: fpgaregs 0x10 0x0008");
exit(EXIT_FAILURE);
}
@@ -62,33 +60,35 @@
exit(EXIT_FAILURE);
}
- address = (unsigned char )strtol(argv[1], (char **)NULL, 16);
+ address = (unsigned int)strtol(argv[1], (char **)NULL, 16);
- if(address%2!=0){
- perror("error address must be pair\n");
- exit(EXIT_FAILURE);
+ if(argc<2){
+ perror("invalid command line");
}
-
- /* write value at address */
- if(argc == 3){
- value = (unsigned char )strtol(argv[2], (char **)NULL, 16);
- retval = pwrite(ffpga,(void *)&value,2,address);
- if(retval<0){
- perror("write error\n");
- exit(EXIT_FAILURE);
+ else {
+ /* write value at address */
+ if(argc == 3){
+ value = strtol(argv[2], (char **)NULL, 16);
+ retval = pwrite(ffpga,(void *)&value,2,address);
+ if(retval<0){
+ perror("write error\n");
+ error = EXIT_FAILURE;
+ }
+ else
+ printf("Wrote %04x at %08x\n",value,address);
+
+ /* read address value */
+ }else if(argc == 2){
+ retval = pread(ffpga,(void *)&value,2,address);
+ if(retval<0){
+ perror("Read error\n");
+ error = EXIT_FAILURE;
+ }
+ else
+ printf("Read %04x at %08x\n",value,address);
+ }
}
- printf("Wrote %04x at %08x\n",value,address+0x12000000);
-
- /* read address value */
- }else{
- retval = pread(ffpga,(void *)&value,2,address);
- if(retval<0){
- perror("Read error\n");
- exit(EXIT_FAILURE);
- }
- printf("Read %04x at %08x\n",value,address+0x12000000);
- }
-
close(ffpga);
- exit(0);
+ exit(error);
}
+
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|
|
From: <ar...@us...> - 2008-05-04 12:12:58
|
Revision: 802
http://armadeus.svn.sourceforge.net/armadeus/?rev=802&view=rev
Author: artemys
Date: 2008-05-04 05:12:52 -0700 (Sun, 04 May 2008)
Log Message:
-----------
[LINUX] Correct false commentar in apf9328
Modified Paths:
--------------
trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.18.1/021-linux-2.6.18-apf9328.diff
trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff
Modified: trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.18.1/021-linux-2.6.18-apf9328.diff
===================================================================
--- trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.18.1/021-linux-2.6.18-apf9328.diff 2008-05-01 20:01:15 UTC (rev 801)
+++ trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.18.1/021-linux-2.6.18-apf9328.diff 2008-05-04 12:12:52 UTC (rev 802)
@@ -1080,7 +1080,7 @@
+static void tsc2102_init_gpio(void)
+{
+ // Activate SPI2 port ----
-+ // PortB 19 is used as chip select (in GPIO mode)
++ // PortB 17 is used as chip select (in GPIO mode)
+ DR(1) |= 1 << TSC2102_CS_GPIOB; // Initializes it High
+ imx_gpio_mode( GPIO_PORTB | TSC2102_CS_GPIOB | GPIO_OUT | GPIO_GIUS | GPIO_DR );
+ // Configure SPI2 outputs
Modified: trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff
===================================================================
--- trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff 2008-05-01 20:01:15 UTC (rev 801)
+++ trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff 2008-05-04 12:12:52 UTC (rev 802)
@@ -1082,7 +1082,7 @@
+static void tsc2102_init_gpio(void)
+{
+ // Activate SPI2 port ----
-+ // PortB 19 is used as chip select (in GPIO mode)
++ // PortB 17 is used as chip select (in GPIO mode)
+ DR(1) |= 1 << TSC2102_CS_GPIOB; // Initializes it High
+ imx_gpio_mode( GPIO_PORTB | TSC2102_CS_GPIOB | GPIO_OUT | GPIO_GIUS | GPIO_DR );
+ // Configure SPI2 outputs
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <jo...@us...> - 2008-05-01 20:01:12
|
Revision: 801
http://armadeus.svn.sourceforge.net/armadeus/?rev=801&view=rev
Author: jorasse
Date: 2008-05-01 13:01:15 -0700 (Thu, 01 May 2008)
Log Message:
-----------
[TOOLS/APF2] Added preliminary uboot_recover2 (Alpha dev)
Added Paths:
-----------
branches/apf2/software/uboot_recover/u-boot2.bin
branches/apf2/software/uboot_recover/uboot_recover2.py
Added: branches/apf2/software/uboot_recover/u-boot2.bin
===================================================================
(Binary files differ)
Property changes on: branches/apf2/software/uboot_recover/u-boot2.bin
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: branches/apf2/software/uboot_recover/uboot_recover2.py
===================================================================
--- branches/apf2/software/uboot_recover/uboot_recover2.py (rev 0)
+++ branches/apf2/software/uboot_recover/uboot_recover2.py 2008-05-01 20:01:15 UTC (rev 801)
@@ -0,0 +1,298 @@
+#
+# APF27 bootloader
+#
+# Copyright (2008) ARMADEUS
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# author: nic...@ar...
+#
+# Change History:
+# - (Jorasse) Added support for PCM038: init DDR RAM and u-boot upload
+#
+
+import sys
+import time
+from struct import *
+import os
+import serial
+
+
+
+class imxlBootloader:
+
+ statuscode = { 0x8D: 'data specified is out of bounds',
+ 0x55: 'error during assert verification',
+ 0x36: 'hash verification failed',
+ 0x33: 'certificate parsing failed or the certificate contained an unsupported key',
+ 0x35: 'signature verification failed',
+ 0x4B: 'CSF command sequence contains unsupported command identifier',
+ 0x4E: 'absence of expected CSF header',
+ 0x4D: 'CSF length is unsupported',
+ 0x2E: 'CSF TYPE does not match processor TYPE',
+ 0x2D: 'CSF UID does not match either processor UID or generic UID',
+ 0x3A: 'CSF customer/product code does not match processor customer/product code',
+ 0x87: 'key indexis either unsupported, or an attempt is made to overwrite the SRK from a CSF command',
+ 0xF0: 'successful operation completion',
+ 0x17: 'SCC unexpectedly not in secure state',
+ 0x1E: 'secureRAM secret key invalid',
+ 0x1D: 'secureRAM initialization failure',
+ 0x1B: 'secureRAM self test failure',
+ 0x2B: 'secureRAM internal failure',
+ 0x27: 'secureRAM secrect key unexpectedly in use',
+ 0x8B: 'an attempt is made to read a key from the list of subordinate public keys at a location where no key is installed',
+ 0x8E: 'algorithm type is either invalid or ortherwise unsupported',
+ 0x66: 'write operation to register failed',
+ 0x63: 'DCD invalid',
+ 0x6F: 'RAM application pointer is NULL or ERASED_FLASH',
+ 0x69: 'CSF missing when HAB TYPE is not HAB-disabled',
+ 0x6A: 'NANDFC boot buffer load failed',
+ 0x6C: 'Exception has occured',
+ 0x67: 'INT_BOOT fuse is blown but BOOT pins are set for external boot',
+ 0x88: 'Successful download completion' }
+
+
+
+ def __init__(self, serialport ):
+
+ self.port = serialport
+
+
+
+ def getstatus(self):
+ self.port.flushInput()
+
+ self.port.write( self.buildcmd("0505" ,"00000000","b","00000000","00","0" ))
+ result = self.port.read(4)
+ if len(result) > 0:
+ print self.statuscode[ord(result[0])]
+ for i in range(len(result)):
+ print '%02x' % ord(result[i]),
+ print '\n'
+ else:
+ print '\nread timeout'
+
+
+
+ def __displayProgress( self, text ):
+
+ sys.stdout.write(chr(13))
+
+ print text,
+
+
+
+
+
+# addr: address to read
+# count: number of bytes to read
+# mode: b, w, l for byte, word, long
+
+ def get( self, addr, count, mode ):
+
+ assert len(addr) <= 8, 'address too long'
+
+ assert int(count,16) > 0, 'zero length get'
+
+ assert int(count,16) < 0xffffffff, 'Too long get, should be < 31 bytes'
+
+
+ self.port.write( self.buildcmd("0101" ,addr,mode,count.zfill(9-len(count)),"00000000","0" ) )
+
+ nbbyte = 1
+ if mode == 'w':
+ nbbyte = 2
+ if mode == 'l':
+ nbbyte = 4
+
+ nbbyte = nbbyte * int(count)
+ result = self.port.read(nbbyte+4) # read n+4 char
+ if len(result) == 0:
+ print '\nread timeout'
+ return
+ print '\nread ACK:',
+ for i in range (4):
+ print '%02x' % ord(result[i]),
+
+ print '\nread data:',
+ for i in range (4,len(result)):
+ print '%02x' % ord(result[i]),
+ print '\n'
+ return result[4:]
+
+
+# addr: address where the data have to be written
+# data: data to write. must match the given mode
+
+# mode: b, w, l for byte, word, long
+
+ def put( self, addr, data, mode ):
+
+ assert len(data) > 0, 'zero length put'
+
+ assert len(addr) == 8, 'address too long'
+
+
+
+ self.port.write( self.buildcmd("0202" ,addr,mode,"00000000",data,"0" ))
+ result = self.port.read(4) #ack
+ if len(result) == 0:
+ print '\nread timeout'
+ return
+ print ' \nwrite ACK:',
+ for i in range (len(result)):
+ print '%02x' % ord(result[i]),
+
+ result = self.port.read(4)
+ if len(result) == 0:
+ print 'read timeout'
+ return
+
+ print '\nwrite success:',
+ for i in range (len(result)):
+ print '%02x' % ord(result[i]),
+ print
+
+ def download( self, addr, data, size, mode ):
+
+ assert size > 0, 'file empty'
+
+
+ f=open(data, 'rb')
+
+
+ self.port.write( self.buildcmd("0404" ,addr,mode, size, "00000000","AA" ))
+ result = self.port.read(4) #ack
+ if len(result) == 0:
+ print '\nread timeout'
+ return
+ print ' \nwrite ACK:',
+ for i in range (len(result)):
+ print '%02x' % ord(result[i]),
+
+ data = f.read(16)
+ count = 16
+ b = 0
+ while len(data):
+ n = len(data)
+ b = 16-n # ensure always 4 bytes
+ #tr = unpack('B'*n,data)
+ self.port.write(data)
+
+ count = count + 16
+ if (count % 1024) == 0:
+ self.__displayProgress( "%d octets" % count )
+ data = f.read(16)
+ self.__displayProgress( "%d octets" % count )
+
+ print ""
+
+ f.close()
+
+ self.getstatus()
+ print
+ return
+
+
+ def buildcmd( self, cmd, addr, ds, cnt, data, ft ):
+ if ds == 'b':
+
+ datatmp = ('%c' % int('00',16)) + ('%c' % int('00',16)) + ('%c' % int('00',16)) + ('%c' % int(data[0:2],16))
+ datasize = "08"
+ if ds == 'w':
+
+ datasize = "10"
+ datatmp = ('%c' % int('00',16)) + ('%c' % int('00',16)) + ('%c' % int(data[0:2],16)) + ('%c' % int(data[2:4],16))
+ if ds == 'l':
+ datasize = "20"
+ datatmp = ('%c' % int(data[0:2],16)) + ('%c' % int(data[2:4],16)) + ('%c' % int(data[4:6],16)) + ('%c' % int(data[6:8],16))
+ if ds == ' ':
+ datasize = "00"
+ datatmp = ('%c' % int(data[0:2],16)) + ('%c' % int(data[2:4],16)) + ('%c' % int(data[4:6],16)) + ('%c' % int(data[6:8],16))
+
+ result = ('%c' % int(cmd[0:2],16)) + ('%c' % int(cmd[2:4],16)) + \
+ ('%c' % int(addr[0:2],16)) + ('%c' % int(addr[2:4],16)) + ('%c' % int(addr[4:6],16)) + ('%c' % int(addr[6:8],16)) + \
+ ('%c' % int(datasize,16)) + \
+ ('%c' % int(cnt[0:2],16)) + ('%c' % int(cnt[2:4],16)) + ('%c' % int(cnt[4:6],16)) + ('%c' % int(cnt[6:8],16)) + \
+ datatmp + ('%c' % int(ft,16))
+
+ for i in range(len(result)):
+ print '%02x' % ord(result[i]),
+ print cnt
+ return result
+
+if __name__ == "__main__":
+
+ SPEED = 115200
+
+ ramSize = 16
+ port = "/dev/ttyS0"
+
+ print "APF2 Bootstrap Tool"
+
+ try:
+
+ ser = serial.Serial(port, SPEED, timeout=1)
+
+ except Exception, msg:
+
+ print "unable to open serial port %s" % port
+
+ print msg
+
+ sys.exit()
+
+ ser.flush()
+
+ apfBootloader = imxlBootloader(ser)
+
+ apfBootloader.getstatus()
+
+ apfBootloader.put("D8001010","00000008","l")
+ apfBootloader.put("10027828","55555555","l")
+ apfBootloader.put("10027830","55555555","l")
+ apfBootloader.put("10027834","55555555","l")
+ apfBootloader.put("10027838","00005005","l")
+ apfBootloader.put("1002783C","15555555","l")
+ apfBootloader.put("D8001010","00000004","l")
+ apfBootloader.put("D8001004","006ac73a","l")
+ apfBootloader.put("D8001000","92100000","l")
+ apfBootloader.put("A0000F00","00000000","l")
+ apfBootloader.put("D8001000","A2100000","l")
+ apfBootloader.put("A0000F00","00000000","l")
+ apfBootloader.put("A0000F00","00000000","l")
+ apfBootloader.put("A0000F00","00000000","l")
+ apfBootloader.put("A0000F00","00000000","l")
+ apfBootloader.put("D8001000","A2200000","l")
+ apfBootloader.put("A0000F00","00000000","l")
+ apfBootloader.put("A0000F00","00000000","l")
+ apfBootloader.put("A0000F00","00000000","l")
+ apfBootloader.put("A0000F00","00000000","l")
+ apfBootloader.put("D8001000","b2100000","l")
+ apfBootloader.put("A0000033","DA0000DA","b")
+ apfBootloader.put("A1000000","FF0000FF","b")
+ apfBootloader.put("D8001000","82226080","l")
+
+
+ result = apfBootloader.get("A0000000","8","b")
+ result = apfBootloader.get("C0000000","8","b")
+
+ fileName = 'u-boot2.bin'
+ fsize = "%08x" % os.path.getsize(fileName) #os.stat(filesize)[6]
+ print "starting download %s bytes" % fsize
+
+ apfBootloader.download("A0000000",fileName, fsize," ")
+
+ del ser
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|
|
From: <ar...@us...> - 2008-04-30 21:35:11
|
Revision: 800
http://armadeus.svn.sourceforge.net/armadeus/?rev=800&view=rev
Author: artemys
Date: 2008-04-30 14:35:11 -0700 (Wed, 30 Apr 2008)
Log Message:
-----------
[LINUX] Modify 2.6.23.1 default config to allow automatic build works again and put Sharp LQ043 as default LCD
Modified Paths:
--------------
trunk/buildroot/target/device/armadeus/apf9328/linux-2.6.23.1.config
Modified: trunk/buildroot/target/device/armadeus/apf9328/linux-2.6.23.1.config
===================================================================
--- trunk/buildroot/target/device/armadeus/apf9328/linux-2.6.23.1.config 2008-04-27 20:27:39 UTC (rev 799)
+++ trunk/buildroot/target/device/armadeus/apf9328/linux-2.6.23.1.config 2008-04-30 21:35:11 UTC (rev 800)
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.23.1
-# Wed Dec 12 22:36:50 2007
+# Mon Apr 14 23:01:28 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -744,8 +744,8 @@
# Frame buffer hardware drivers
#
CONFIG_FB_IMX=y
-# CONFIG_FB_IMX_SHARP_LQ043_TFT is not set
-CONFIG_FB_IMX_MICROTIPS_MTF_T035_TFT=y
+CONFIG_FB_IMX_SHARP_LQ043_TFT=y
+# CONFIG_FB_IMX_MICROTIPS_MTF_T035_TFT is not set
# CONFIG_FB_IMX_SHARP_LQ057_TFT is not set
# CONFIG_FB_IMX_OPTREX_F51900_CSTN is not set
# CONFIG_FB_IMX_MOTOROLA_A910_TFT is not set
@@ -835,11 +835,13 @@
#
# FPGA related
#
-CONFIG_ARMADEUS_FPGA_TOOL_DRIVER=m
-CONFIG_ARMADEUS_KEYPAD_DRIVER=m
-CONFIG_ARMADEUS_PS2KBD_DRIVER=m
#
+# FPGA Drivers
+#
+# CONFIG_ARMADEUS_FPGA_DRIVERS is not set
+
+#
# Handheld related
#
CONFIG_ARMADEUS_PWM_DRIVER=m
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <ar...@us...> - 2008-04-27 20:27:34
|
Revision: 799
http://armadeus.svn.sourceforge.net/armadeus/?rev=799&view=rev
Author: artemys
Date: 2008-04-27 13:27:39 -0700 (Sun, 27 Apr 2008)
Log Message:
-----------
[DEMOS] First version of SDL+Tslib backlight controller
Added Paths:
-----------
trunk/target/demos/backlight_control/
trunk/target/demos/backlight_control/Makefile
trunk/target/demos/backlight_control/README
trunk/target/demos/backlight_control/backlight.c
trunk/target/demos/backlight_control/backlight_sysctl.c
trunk/target/demos/backlight_control/backlight_sysctl.h
trunk/target/demos/backlight_control/cursor.bmp
trunk/target/demos/backlight_control/empty.bmp
trunk/target/demos/backlight_control/empty_end.bmp
trunk/target/demos/backlight_control/full.bmp
trunk/target/demos/backlight_control/full_end.bmp
Added: trunk/target/demos/backlight_control/Makefile
===================================================================
--- trunk/target/demos/backlight_control/Makefile (rev 0)
+++ trunk/target/demos/backlight_control/Makefile 2008-04-27 20:27:39 UTC (rev 799)
@@ -0,0 +1,48 @@
+
+ifeq ($(TARGET),)
+ BUILDROOT_DIR:=../../../buildroot/
+ BUILD_DIR_EXT:=$(shell ls $(BUILDROOT_DIR) | grep -e "^build_arm*")
+ BUILD_DIR:=$(BUILDROOT_DIR)/$(BUILD_DIR_EXT)
+
+ SDL_DIR:=$(BUILD_DIR)/SDL-1.2.11/
+ STAGING_DIR:=$(BUILD_DIR)/staging_dir/
+ ROOT_DIR:=$(BUILDROOT_DIR)/project_$(BUILD_DIR_EXT)/armadeus/root/
+ INSTALL_DIR:=$(ROOT_DIR)/usr/bin/
+
+ CC:=$(STAGING_DIR)/bin/arm-linux-gcc
+ DEFINES="TARGET"
+ CFLAGS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --cflags)
+ LIBS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --libs)
+else
+ INSTALL_DIR="./install"
+ CFLAGS=`/usr/bin/sdl-config --cflags`
+ LIBS=`/usr/bin/sdl-config --libs`
+ CC=gcc
+ DEFINES="HOST"
+endif
+
+CFLAGS+="-g"
+
+default: backlight
+
+all: backlight
+
+
+backlight.o: backlight.c
+ $(CC) $(CFLAGS) -c -o $@ $^
+
+backlight_sysctl.o: backlight_sysctl.c
+ $(CC) $(CFLAGS) -D$(DEFINES) -c -o $@ $^
+
+backlight: backlight.o backlight_sysctl.o
+ $(CC) $(LIBS) -o $@ $^
+
+install: backlight cursor.bmp empty.bmp empty_end.bmp full.bmp full_end.bmp
+ mkdir -p $(INSTALL_DIR)
+ cp $^ $(INSTALL_DIR)
+
+clean:
+ rm -rf backlight
+ rm -rf *.o
+ rm -rf active backlight.dat
+
Added: trunk/target/demos/backlight_control/README
===================================================================
--- trunk/target/demos/backlight_control/README (rev 0)
+++ trunk/target/demos/backlight_control/README 2008-04-27 20:27:39 UTC (rev 799)
@@ -0,0 +1,6 @@
+
+* ARM compiling:
+ $ make clean; make install
+* x86 compiling (SDL devt package should be installed on your system)
+ $ make TARGET=x86 clean; make TARGET=x86
+
Added: trunk/target/demos/backlight_control/backlight.c
===================================================================
--- trunk/target/demos/backlight_control/backlight.c (rev 0)
+++ trunk/target/demos/backlight_control/backlight.c 2008-04-27 20:27:39 UTC (rev 799)
@@ -0,0 +1,315 @@
+/*
+ *
+ * Small tool to demonstrate how to use (or not use ;-) ) Tslib + SDL library
+ * for the Armadeus project. www.armadeus.og
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h> // for sleep()
+
+#include "SDL.h"
+// To
+#include "backlight_sysctl.h"
+
+
+#define SCREEN_WIDTH 480
+#define SCREEN_HEIGHT 270
+#define BAR_MIN_XPOSITION (0+(SCREEN_WIDTH>>4))
+#define BAR_MAX_XPOSITION (SCREEN_WIDTH-(SCREEN_WIDTH>>4))
+#define BAR_YPOSITION (SCREEN_HEIGHT/2)
+#define BAR_WIDTH (BAR_MAX_XPOSITION-BAR_MIN_XPOSITION)
+
+#ifdef DEBUG
+#define debug( args...) printf( ## args )
+#else
+#define debug( args...) do {;} while(0);
+#endif
+
+#define bool unsigned int
+#define false 0
+#define true 1
+
+SDL_Surface *cursor;
+SDL_Surface *full_end;
+SDL_Surface *full;
+SDL_Surface *empty;
+SDL_Surface *empty_end;
+SDL_Surface *screen;
+
+const int NB_FRAMES_PER_SECOND = 50;
+
+
+//---- Private functions ----
+
+// Load all images needed by the tool (from .bmp files)
+static int loadImages()
+{
+ int result = 0;
+
+ full_end = SDL_LoadBMP("./full_end.bmp");
+ full = SDL_LoadBMP("./full.bmp");
+ cursor = SDL_LoadBMP("./cursor.bmp");
+ empty = SDL_LoadBMP("./empty.bmp");
+ empty_end = SDL_LoadBMP("./empty_end.bmp");
+
+ // Check if we got all images
+ if( full_end == NULL || full == NULL || cursor == NULL || empty == NULL || empty_end == NULL )
+ {
+ printf("Unable to load image files !\n");
+ result = -1;
+ } else {
+ //SDL_SetAlpha( image, 0/*SDL_SRCALPHA*/, SDL_ALPHA_TRANSPARENT );
+ if( SDL_SetColorKey( cursor, SDL_SRCCOLORKEY, SDL_MapRGB(cursor->format, 0xFF, 0xFF, 0xFF) ) )
+ {
+ printf("Error while setting transparent color\n");
+ }
+ }
+
+ return(result);
+}
+
+//
+static void freeRessources()
+{
+ SDL_FreeSurface( screen );
+ SDL_FreeSurface( full_end );
+ SDL_FreeSurface( full );
+ SDL_FreeSurface( cursor );
+ SDL_FreeSurface( empty );
+ SDL_FreeSurface( empty_end );
+}
+
+//
+void drawImage(SDL_Surface *img, int x, int y)
+{
+ SDL_Rect dest;
+ dest.x = x;
+ dest.y = y;
+ SDL_BlitSurface(img, NULL, screen, &dest);
+}
+
+//
+void drawBackground()
+{
+ SDL_Rect dest;
+ dest.x = 0; dest.y = 0; dest.w = SCREEN_WIDTH; dest.h = SCREEN_HEIGHT;
+ // Fill background
+ SDL_FillRect( screen, &dest, SDL_MapRGB( screen->format, 0xFF, 0xFF, 0xFF ) );
+}
+
+//
+static int paddXPos( int xpos )
+{
+ int x=0;
+
+ if( xpos <= BAR_MIN_XPOSITION ) {
+ x = BAR_MIN_XPOSITION;
+ } else if ( xpos >= BAR_MAX_XPOSITION ) {
+ x = BAR_MAX_XPOSITION;
+ } else {
+ x = xpos;
+ }
+
+ return( x );
+}
+
+//
+static void drawBar( int xpos )
+{
+ int i=BAR_MIN_XPOSITION;
+
+ if( xpos <= BAR_MIN_XPOSITION ) {
+ xpos = BAR_MIN_XPOSITION;
+ } else if ( xpos >= BAR_MAX_XPOSITION ) {
+ xpos = BAR_MAX_XPOSITION;
+ }
+
+ drawImage( full_end, i, BAR_YPOSITION );
+ i+=5;
+
+ for( ; i<=xpos; i+=5 ) {
+ drawImage( full, i, BAR_YPOSITION );
+ }
+
+ for( ; i<=BAR_MAX_XPOSITION; i+=5 ) {
+ drawImage( empty, i, BAR_YPOSITION );
+ }
+
+ drawImage( empty_end, i, BAR_YPOSITION );
+}
+
+//
+static unsigned char calculateBacklight( int xpos )
+{
+ int x = 0;
+ unsigned char backlight = 0; // 0-100 %
+
+ x = paddXPos( xpos );
+ backlight = (unsigned char) (((x - BAR_MIN_XPOSITION)*100) / BAR_WIDTH);
+
+ return( backlight );
+}
+
+//
+static void drawCursor( int xpos )
+{
+ int x=0;
+
+ x = paddXPos( xpos );
+ drawImage( cursor, x, BAR_YPOSITION-5);
+}
+
+//
+void updateCursor( int xpos )
+{
+ drawBackground();
+ drawBar( xpos );
+ drawCursor(xpos );
+ SDL_Flip( screen );
+}
+
+
+//---- Main ----
+
+#define MAX_BAR_SPEED 10
+int main(int argc, char *argv[])
+{
+ Uint8* keys;
+ int nbFrames = 0;
+ int cursorPos = 0;
+ //Timer fps, update;
+ //Sint8 xspeed = 1, yspeed =1;
+
+ // Initialize SDL
+ if( SDL_Init( SDL_INIT_VIDEO | SDL_INIT_TIMER /*| SDL_INIT_EVENTTHREAD |SDL_INIT_NOPARACHUTE*/) < 0 )
+ {
+ printf("Unable to init SDL: %s\n", SDL_GetError());
+ exit(1);
+ }
+ if (SDL_InitSubSystem(SDL_INIT_TIMER) == -1)
+ {
+ fprintf(stderr, "SDL timer failed to initialize! Error: %s\n", SDL_GetError());
+ exit(1);
+ }
+ else
+ {
+ fprintf(stdout, "SDL timer initialized properly!\n");
+ }
+ // Ask SDL to cleanup when exiting
+ atexit(SDL_Quit);
+
+ // Get a screen to display our game
+ screen=SDL_SetVideoMode( SCREEN_WIDTH, SCREEN_HEIGHT, 16, 0/*SDL_HWPALETTE*//*SDL_HWSURFACE|| SDL_DOUBLEBUF*/ );
+ if( screen == NULL )
+ {
+ printf("Unable to set %dx%dvideo mode: %s\n", SCREEN_WIDTH, SCREEN_HEIGHT, SDL_GetError());
+ exit(1);
+ }
+
+ // Load our graphics
+ if( loadImages() )
+ {
+ return(1);
+ }
+ drawBackground();
+
+ // Initialize Backlight control
+ if( initBacklightControl() )
+ {
+ printf("Unable to find Backlight control on your system -> won't be activated\n");
+ }
+ updateCursor( (getBacklight() * BAR_WIDTH / 100) + BAR_MIN_XPOSITION );
+ int done=0, move=0;
+
+ // Hide mouse
+ SDL_ShowCursor(0);
+
+ /* // Start timer for Frame Rate calculation
+ update.start();
+ fps.start();*/
+
+ // Main loop
+ while(done == 0)
+ {
+ SDL_Event event;
+ // Wait for SDL events
+ while ( SDL_PollEvent(&event) )
+ {
+ cursorPos = 0;
+ switch( event.type )
+ {
+ case SDL_QUIT: { done = 1; break; }
+ case SDL_KEYDOWN:
+ {
+ if ( event.key.keysym.sym == SDLK_ESCAPE ) { done = 1; }
+ break;
+ }
+ case SDL_MOUSEBUTTONDOWN:
+ {
+ move = 1;
+ cursorPos = event.motion.x;
+ break;
+ }
+
+ case SDL_MOUSEBUTTONUP: { move = 0; break; }
+
+ case SDL_MOUSEMOTION:
+ {
+ if( move == 1 ) {
+ debug("Current mouse position is: (%d, %d)\n", event.motion.x, event.motion.y);
+ cursorPos = event.motion.x;
+ }
+ break;
+ }
+ }
+ }
+
+ if( cursorPos != 0 && move == 1 ) {
+
+ //
+ setBacklight( calculateBacklight( cursorPos ) );
+
+ // Update screen
+ updateCursor( cursorPos );
+ nbFrames++;
+ }
+
+ // Calculate and stabilize Frame Rate
+/* if( update.getTicks() > 1000 )
+ {
+ printf("FPS: %f\n", (float)nbFrames );
+ update.start();
+ nbFrames = 0;
+ }
+ while( fps.getTicks() < (1000 / NB_FRAMES_PER_SECOND) )
+ {
+ ;
+ }
+ fps.start();
+*/
+ SDL_Delay(50);
+ }
+
+ // Cleanup what we used
+ releaseBacklightControl();
+ freeRessources();
+ SDL_QuitSubSystem( SDL_INIT_TIMER );
+ SDL_Quit();
+
+ return 0;
+}
Added: trunk/target/demos/backlight_control/backlight_sysctl.c
===================================================================
--- trunk/target/demos/backlight_control/backlight_sysctl.c (rev 0)
+++ trunk/target/demos/backlight_control/backlight_sysctl.c 2008-04-27 20:27:39 UTC (rev 799)
@@ -0,0 +1,89 @@
+#include "SDL.h"
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "backlight_sysctl.h"
+
+int playing, initialized = 0;
+FILE* fd;
+FILE* fda;
+unsigned char currentBacklight = 0;
+
+#ifdef TARGET
+#define FREQ_SYS_FILE "/sys/class/pwm/pwm0/frequency"
+#define ACTIVE_SYS_FILE "/sys/class/pwm/pwm0/active"
+#else
+#define FREQ_SYS_FILE "./backlight.dat"
+#define ACTIVE_SYS_FILE "./active"
+#endif // TARGET
+
+SDL_TimerID myTimerID;
+
+/*
+ * Initialize the system
+ *
+ */
+int initBacklightControl()
+{
+ int result = -1;
+
+ if( !initialized )
+ {
+ playing = 0;
+ fd = fopen( FREQ_SYS_FILE, "w+" );
+ fda = fopen( ACTIVE_SYS_FILE, "w" );
+
+ if( (fd != NULL) && (fda != NULL) )
+ {
+ result = 0;
+ initialized = 1;
+#ifdef TARGET
+
+#else
+ currentBacklight = 50; // %
+#endif // TARGET
+ } else
+ printf("Buzzer: can't open /sys interface\n");
+ }
+ return( result );
+}
+
+/*
+ * Free ressources allocated by the "library"
+ *
+ */
+void releaseBacklightControl()
+{
+ if( initialized )
+ {
+ fclose( fd );
+ fclose( fda );
+ initialized = 0;
+ }
+}
+
+/*
+ * 0-100 %
+ */
+void setBacklight( unsigned char aValue )
+{
+ if( initialized )
+ {
+ char value[4]; int nchar;
+
+ // Program PWM with given frequency
+ nchar = sprintf( value, "%d", aValue);
+ fwrite( value, 1, nchar, fd );
+ fflush( fd );
+ currentBacklight = aValue;
+ }
+}
+
+/*
+ * 0-100 %
+ */
+unsigned char getBacklight( void )
+{
+ return( currentBacklight );
+}
+
Added: trunk/target/demos/backlight_control/backlight_sysctl.h
===================================================================
--- trunk/target/demos/backlight_control/backlight_sysctl.h (rev 0)
+++ trunk/target/demos/backlight_control/backlight_sysctl.h 2008-04-27 20:27:39 UTC (rev 799)
@@ -0,0 +1,15 @@
+#ifndef H_BACKLIGHT_CONTROL_INCLUDE
+#define H_BACKLIGHT_CONTROL_INCLUDE
+
+
+// Initialize the Backlight control library
+int initBacklightControl( void );
+
+// Play a sound on buzzer at given frequency (Hz) and during given time (ms)
+void setBacklight( unsigned char aValue );
+
+// Free ressources allocated by the Backlight control library
+void releaseBacklightControl( void );
+
+
+#endif // H_BACKLIGHT_CONTROL_INCLUDE
Added: trunk/target/demos/backlight_control/cursor.bmp
===================================================================
(Binary files differ)
Property changes on: trunk/target/demos/backlight_control/cursor.bmp
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: trunk/target/demos/backlight_control/empty.bmp
===================================================================
(Binary files differ)
Property changes on: trunk/target/demos/backlight_control/empty.bmp
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: trunk/target/demos/backlight_control/empty_end.bmp
===================================================================
(Binary files differ)
Property changes on: trunk/target/demos/backlight_control/empty_end.bmp
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: trunk/target/demos/backlight_control/full.bmp
===================================================================
(Binary files differ)
Property changes on: trunk/target/demos/backlight_control/full.bmp
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: trunk/target/demos/backlight_control/full_end.bmp
===================================================================
(Binary files differ)
Property changes on: trunk/target/demos/backlight_control/full_end.bmp
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <jo...@us...> - 2008-04-26 19:33:29
|
Revision: 798
http://armadeus.svn.sourceforge.net/armadeus/?rev=798&view=rev
Author: jorasse
Date: 2008-04-26 12:24:26 -0700 (Sat, 26 Apr 2008)
Log Message:
-----------
[rootfs] added input devices to support keyboard and keypad
Modified Paths:
--------------
trunk/buildroot/target/device/armadeus/rootfs/device_table.txt
Modified: trunk/buildroot/target/device/armadeus/rootfs/device_table.txt
===================================================================
--- trunk/buildroot/target/device/armadeus/rootfs/device_table.txt 2008-04-26 16:33:14 UTC (rev 797)
+++ trunk/buildroot/target/device/armadeus/rootfs/device_table.txt 2008-04-26 19:24:26 UTC (rev 798)
@@ -76,6 +76,13 @@
/dev/psaux c 666 0 0 10 1 0 0 -
#/dev/ppp c 666 0 0 108 0 - - -
+# Input stuff
+/dev/input d 755 0 0 - - - - -
+/dev/input/mice c 640 0 0 13 63 0 0 -
+/dev/input/mouse c 660 0 0 13 32 0 1 4
+/dev/input/event c 660 0 0 13 64 0 1 4
+#/dev/input/js c 660 0 0 13 0 0 1 4
+
# MTD stuff
/dev/mtd c 640 0 0 90 0 0 2 8
/dev/mtdblock b 640 0 0 31 0 0 1 8
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|
|
From: <jo...@us...> - 2008-04-26 16:33:18
|
Revision: 797
http://armadeus.svn.sourceforge.net/armadeus/?rev=797&view=rev
Author: jorasse
Date: 2008-04-26 09:33:14 -0700 (Sat, 26 Apr 2008)
Log Message:
-----------
[buildroot] fixed "mkimage" broken link
Modified Paths:
--------------
branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk
Modified: branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk 2008-04-26 15:03:04 UTC (rev 796)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk 2008-04-26 16:33:14 UTC (rev 797)
@@ -117,7 +117,7 @@
###-----
u-boot: $(BINARIES_DIR)/u-boot.bin $(BINARIES_DIR)/u-boot.brec
- ln -fs $(U-BOOT_DIR)/tools/mkimage $(STAGING_DIR)/bin/mkimage
+ ln -fs $(U-BOOT_DIR)/scripts/mkimage $(STAGING_DIR)/bin/mkimage
###-----
u-boot-clean:
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|
|
From: <jo...@us...> - 2008-04-26 15:03:57
|
Revision: 796
http://armadeus.svn.sourceforge.net/armadeus/?rev=796&view=rev
Author: jorasse
Date: 2008-04-26 08:03:04 -0700 (Sat, 26 Apr 2008)
Log Message:
-----------
[uClibc] uClibc-0.9.29 pretends that spinclocks are available ?\194?\160("#define _POSIX_SPIN_LOCKS" in posix_opt.h)
whereas for ARM, this functionality is currently in development. As a consequence, ?\194?\160third party applications
looking for this define to internally enable spinlocking ?\194?\160may fail to compile. (As "clocktest" provided by Xenomai).
This patch inhibits the faulty define. Thanks Creber
Modified Paths:
--------------
trunk/ChangeLog
Added Paths:
-----------
trunk/buildroot/toolchain/uClibc/uClibc-0.9.29-fix-spin_locks.patch
Modified: trunk/ChangeLog
===================================================================
--- trunk/ChangeLog 2008-04-16 20:37:31 UTC (rev 795)
+++ trunk/ChangeLog 2008-04-26 15:03:04 UTC (rev 796)
@@ -1,6 +1,10 @@
ChangeLog file for Armadeus Project
+Changes to be released
+- [uClibc] undefine _POSIX_SPIN_LOCKS: still not yet implemented in uClibc 0.9.29
+ thanks to Creber
+
Changes in release 2.3 (11 February 2008)
- [BUILDROOT] Change FTP server for buildroot and fakeroot files
Added: trunk/buildroot/toolchain/uClibc/uClibc-0.9.29-fix-spin_locks.patch
===================================================================
--- trunk/buildroot/toolchain/uClibc/uClibc-0.9.29-fix-spin_locks.patch (rev 0)
+++ trunk/buildroot/toolchain/uClibc/uClibc-0.9.29-fix-spin_locks.patch 2008-04-26 15:03:04 UTC (rev 796)
@@ -0,0 +1,16 @@
+diff -purN uClibc-0.9.29.ori/libc/sysdeps/linux/common/bits/posix_opt.h uClibc-0.9.29/libc/sysdeps/linux/common/bits/posix_opt.h
+--- uClibc-0.9.29.ori/libc/sysdeps/linux/common/bits/posix_opt.h 2008-04-26 15:25:03.000000000 +0200
++++ uClibc-0.9.29/libc/sysdeps/linux/common/bits/posix_opt.h 2008-04-26 15:39:38.000000000 +0200
+@@ -124,8 +124,11 @@
+ /* We support the Timeouts option. */
+ #define _POSIX_TIMEOUTS 200112L
+
++/* Armadeus Patch: Spinlock is still not yet implemented in UcLibc for Arm */
++/* targets. However, Xenomai-2.4.3 use this flags to enable or not */
++/* spinlocking. If this define is set, Xenomai will fail to compile */
+ /* We support spinlocks. */
+-#define _POSIX_SPIN_LOCKS 200112L
++/* #define _POSIX_SPIN_LOCKS 200112L */
+
+ /* The `spawn' function family is supported. */
+ #define _POSIX_SPAWN 200112L
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|
|
From: <ar...@us...> - 2008-04-16 20:37:26
|
Revision: 795
http://armadeus.svn.sourceforge.net/armadeus/?rev=795&view=rev
Author: artemys
Date: 2008-04-16 13:37:31 -0700 (Wed, 16 Apr 2008)
Log Message:
-----------
[BUILDROOT] Deactivate ivtv ouput when configuring mplayer
Added Paths:
-----------
trunk/patches/040-buildroot-mplayer-remove-ivtv-output.diff
Added: trunk/patches/040-buildroot-mplayer-remove-ivtv-output.diff
===================================================================
--- trunk/patches/040-buildroot-mplayer-remove-ivtv-output.diff (rev 0)
+++ trunk/patches/040-buildroot-mplayer-remove-ivtv-output.diff 2008-04-16 20:37:31 UTC (rev 795)
@@ -0,0 +1,10 @@
+--- buildroot.org/package/mplayer/mplayer.mk 2008-04-01 17:17:27.000000000 +0200
++++ buildroot/package/mplayer/mplayer.mk 2008-04-13 21:29:14.000000000 +0200
+@@ -45,6 +45,7 @@
+ $(MPLAYER_ENDIAN) \
+ --disable-mpdvdkit \
+ --disable-tv \
++ --disable-ivtv \
+ --enable-dynamic-plugins \
+ )
+ touch $@
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|
|
From: <Fa...@us...> - 2008-04-08 13:21:06
|
Revision: 794
http://armadeus.svn.sourceforge.net/armadeus/?rev=794&view=rev
Author: FabM
Date: 2008-04-08 06:21:01 -0700 (Tue, 08 Apr 2008)
Log Message:
-----------
[kernel][module] new fpgaregs, to read/write in 16bits on fpga driver+binary
Modified Paths:
--------------
trunk/target/linux/modules/Makefile
trunk/target/linux/modules/backlight/Makefile
trunk/target/linux/modules/fpga/Kconfig
trunk/target/linux/modules/fpga/Wb_button/button.c
trunk/target/linux/modules/fpga/Wb_button/button_specific.h
trunk/target/linux/modules/fpga/Wb_button/testbutton.c
trunk/target/linux/modules/gpio/Makefile
Added Paths:
-----------
trunk/target/linux/modules/fpga/fpgaaccess/
trunk/target/linux/modules/fpga/fpgaaccess/Kconfig
trunk/target/linux/modules/fpga/fpgaaccess/Makefile
trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c
trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.h
trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c
trunk/target/linux/modules/fpga/i2ctest/
trunk/target/linux/modules/fpga/i2ctest/Kconfig
trunk/target/linux/modules/fpga/i2ctest/Makefile
trunk/target/linux/modules/fpga/i2ctest/README
trunk/target/linux/modules/fpga/i2ctest/i2ctest.c
trunk/target/linux/modules/fpga/i2ctest/i2ctest.h
Modified: trunk/target/linux/modules/Makefile
===================================================================
--- trunk/target/linux/modules/Makefile 2008-04-05 09:12:51 UTC (rev 793)
+++ trunk/target/linux/modules/Makefile 2008-04-08 13:21:01 UTC (rev 794)
@@ -8,7 +8,8 @@
ifneq ($(KERNELRELEASE),)
obj-$(CONFIG_ARMADEUS_DRIVERS) += gpio/ pwm/ backlight/ isp1761/ \
- fpga/ps2keyboard/ fpga/keypad/ fpga/fpga_devtools/ fpga/Wb_led/ fpga/Wb_button/
+ fpga/ps2keyboard/ fpga/keypad/ fpga/fpga_devtools/ fpga/Wb_led/ fpga/Wb_button/ \
+ fpga/i2ctest/ fpga/fpgaaccess/
# Part execute when called from standard make in this directory:
else
Modified: trunk/target/linux/modules/backlight/Makefile
===================================================================
--- trunk/target/linux/modules/backlight/Makefile 2008-04-05 09:12:51 UTC (rev 793)
+++ trunk/target/linux/modules/backlight/Makefile 2008-04-08 13:21:01 UTC (rev 794)
@@ -20,7 +20,7 @@
BASE_DIR="../../../../buildroot/"
REL=`grep "BR2_PACKAGE_LINUX_VERSION=" $(BASE_DIR).config | \
sed "s/BR2_PACKAGE_LINUX_VERSION=\\"//" | sed "s/\\"//"`
-ARMADEUS_KERNEL_DIR=$(BASE_DIR)build_arm_nofpu/linux-$(REL)
+ARMADEUS_KERNEL_DIR=$(BASE_DIR)build_arm/linux-$(REL)
KDIR := $(ARMADEUS_KERNEL_DIR)
PWD := $(shell pwd)
Modified: trunk/target/linux/modules/fpga/Kconfig
===================================================================
--- trunk/target/linux/modules/fpga/Kconfig 2008-04-05 09:12:51 UTC (rev 793)
+++ trunk/target/linux/modules/fpga/Kconfig 2008-04-08 13:21:01 UTC (rev 794)
@@ -21,5 +21,9 @@
source "drivers/armadeus/fpga/Wb_button/Kconfig"
+source "drivers/armadeus/fpga/i2ctest/Kconfig"
+
+source "drivers/armadeus/fpga/fpgaaccess/Kconfig"
+
endmenu
Modified: trunk/target/linux/modules/fpga/Wb_button/button.c
===================================================================
--- trunk/target/linux/modules/fpga/Wb_button/button.c 2008-04-05 09:12:51 UTC (rev 793)
+++ trunk/target/linux/modules/fpga/Wb_button/button.c 2008-04-08 13:21:01 UTC (rev 794)
@@ -52,16 +52,17 @@
u16 data;
button_fpga_read(ldev->fpga_virtual_base_address + FPGA_IRQ_PEND,&data,ldev);
+ PDEBUG("Interrupt raised %x\n",data);
if(data&WB_BUTTON_IRQ){
- /* wake up reading process */
- if(ldev->reading)up(&ldev->sem);
- /* acknowledge irq_mngr */
- button_fpga_write(ldev->fpga_virtual_base_address + FPGA_IRQ_ACK,&data,ldev);
- }
- PDEBUG("Interrupt raised %x\n",data);
+ /* wake up reading process */
+ if(ldev->reading)up(&ldev->sem);
+ /* acknowledge irq_mngr */
+ button_fpga_write(ldev->fpga_virtual_base_address + FPGA_IRQ_ACK,&data,ldev);
+ return IRQ_HANDLED;
+ }else
+ return IRQ_NONE;
- return IRQ_HANDLED;
}
/***********************************
@@ -168,7 +169,7 @@
sdev->fpga_virtual_base_address = (void*)IMX_CS1_VIRT;
/* irq unmask */
- data=1;
+ data=1 | ioread16(sdev->fpga_virtual_base_address + FPGA_IRQ_MASK);
if((result=button_fpga_write(sdev->fpga_virtual_base_address + FPGA_IRQ_MASK,&data,sdev))<0)
goto error;
@@ -179,7 +180,7 @@
/* irq registering */
printk(KERN_INFO "button: fpga irq shared gpioa 1\n");
- if(request_irq(IRQ_GPIOA(1),(irq_handler_t)fpga_interrupt,IRQF_SHARED,FPGA_IRQ_NAME,sdev)<0){
+ if(request_irq(IRQ_GPIOA(1),(irq_handler_t)fpga_interrupt,IRQF_SHARED,BUTTON_IRQ_NAME,sdev)<0){
printk(KERN_ERR "Can't request fpga irq\n");
goto error;
}
@@ -203,7 +204,7 @@
static void free_all(void){
struct button_dev *sdev = buttondev;
-
+
/* free irq*/
free_irq(IRQ_GPIOA(1),sdev);
Modified: trunk/target/linux/modules/fpga/Wb_button/button_specific.h
===================================================================
--- trunk/target/linux/modules/fpga/Wb_button/button_specific.h 2008-04-05 09:12:51 UTC (rev 793)
+++ trunk/target/linux/modules/fpga/Wb_button/button_specific.h 2008-04-08 13:21:01 UTC (rev 794)
@@ -7,7 +7,7 @@
/* Fpga base address for led */
#define FPGA_BASE_ADDR IMX_CS1_PHYS
#define FPGA_MEM_SIZE IMX_CS1_SIZE
-#define FPGA_IRQ_NAME "fpga"
+#define BUTTON_IRQ_NAME "button"
/* interrupt position in irq_mngr */
#define WB_BUTTON_IRQ 0x0001
Modified: trunk/target/linux/modules/fpga/Wb_button/testbutton.c
===================================================================
--- trunk/target/linux/modules/fpga/Wb_button/testbutton.c 2008-04-05 09:12:51 UTC (rev 793)
+++ trunk/target/linux/modules/fpga/Wb_button/testbutton.c 2008-04-08 13:21:01 UTC (rev 794)
@@ -1,8 +1,36 @@
-/* a little program to test button driver
+
+ * ***********************************************************************
+/* a program to write/read values on fpga address map
* Fabien Marteau <fab...@ar...>
- * 7 march 2008
+ * 7 april 2008
+ * fpgaaccess.h
+ *
+ * (c) Copyright 2008 Armadeus project
+ * Fabien Marteau <fab...@ar...>
+ *
+ * A simple driver for reading and writing on
+ * fpga throught a character file /dev/fpgaaccess
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
*/
+
+ *
+ */
+
#include <stdio.h>
#include <stdlib.h>
Added: trunk/target/linux/modules/fpga/fpgaaccess/Kconfig
===================================================================
--- trunk/target/linux/modules/fpga/fpgaaccess/Kconfig (rev 0)
+++ trunk/target/linux/modules/fpga/fpgaaccess/Kconfig 2008-04-08 13:21:01 UTC (rev 794)
@@ -0,0 +1,8 @@
+#
+#
+
+config ARMADEUS_FPGAACCESS_DRIVER
+ tristate "fpgaaccess driver"
+ default n
+ depends on ARMADEUS_FPGA_DRIVERS
+ ---help---
Added: trunk/target/linux/modules/fpga/fpgaaccess/Makefile
===================================================================
--- trunk/target/linux/modules/fpga/fpgaaccess/Makefile (rev 0)
+++ trunk/target/linux/modules/fpga/fpgaaccess/Makefile 2008-04-08 13:21:01 UTC (rev 794)
@@ -0,0 +1,37 @@
+#
+# Makefile for the Armadeus Wb_led drivers
+#
+
+BASE_DIR="../../../../../buildroot/"
+
+REL=`grep "BR2_PACKAGE_LINUX_VERSION=" $(BASE_DIR).config | \
+ sed "s/BR2_PACKAGE_LINUX_VERSION=\\"//" | sed "s/\\"//"`
+
+ARMADEUS_KERNEL_DIR=$(BASE_DIR)build_arm/linux-$(REL)
+
+ifneq ($(KERNELRELEASE),)
+
+obj-$(CONFIG_ARMADEUS_FPGAACCESS_DRIVER) += fpgaaccess.o
+
+# Part executed when called from standard make in this directory:
+# (preferably use Makefile in parent directory)
+
+else
+KDIR := $(ARMADEUS_KERNEL_DIR)
+PWD := $(shell pwd)
+
+default:
+ $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
+ -cp fpgaaccess.ko /tftpboot/
+
+fpgaregs: fpgaregs.c
+ ~/armadeus/buildroot/build_arm/staging_dir/bin/arm-linux-gcc -Wall fpgaregs.c -o fpgaregs
+ chmod 755 fpgaregs
+ cp fpgaregs /tftpboot/
+
+clean:
+ rm -f *.*o \
+ rm -f Module.symvers
+
+endif
+
Property changes on: trunk/target/linux/modules/fpga/fpgaaccess/Makefile
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c
===================================================================
--- trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c (rev 0)
+++ trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.c 2008-04-08 13:21:01 UTC (rev 794)
@@ -0,0 +1,173 @@
+/*
+ ***********************************************************************
+ * fpgaaccess.c
+ *
+ * (c) Copyright 2008 Armadeus project
+ * Fabien Marteau <fab...@ar...>
+ *
+ * A simple driver for reading and writing on
+ * fpga throught a character file /dev/fpgaaccess
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
+ */
+
+#include "fpgaaccess.h"
+
+/*************************************/
+/* to read write fpgaaccess register */
+/*************************************/
+ssize_t fpgaaccess_read(struct file *fildes, char __user *buff,
+ size_t count, loff_t *offp){
+ struct fpgaaccess_dev *sdev = fildes->private_data;
+ u16 data=0;
+
+ if(*offp >= FPGA_SIZE || ((*offp)%2 != 0)){ /* offset must be pair */
+ return 0;
+ }
+
+ if(count != 2) /* only one word can be wrote (two bytes)*/
+ count = 2;
+
+ data = ioread16(sdev->fpga_virtual_base_address + *offp);
+
+ /* return data for user */
+ if(copy_to_user(buff,&data,2)){
+ printk(KERN_WARNING "read : copy to user data error\n");
+ return -EFAULT;
+ }
+ return 0;
+}
+
+ssize_t fpgaaccess_write(struct file *fildes, const char __user *
+ buff,size_t count, loff_t *offp){
+ struct fpgaaccess_dev *sdev = fildes->private_data;
+ u16 data=0;
+
+ if(*offp >= FPGA_SIZE || ((*offp)%2 != 0)){ /* offset must be pair */
+ return 0;
+ }
+
+ if(count != 2) /* only one word can be wrote (two bytes)*/
+ count = 2;
+
+ if(copy_from_user(&data,buff,2)){
+ printk(KERN_WARNING "write : copy from user error\n");
+ return -EFAULT;
+ }
+
+ iowrite16(data,sdev->fpga_virtual_base_address + *offp);
+
+ return 2;
+}
+
+int fpgaaccess_open(struct inode *inode, struct file *filp){
+ filp->private_data=container_of(inode->i_cdev,struct fpgaaccess_dev,cdev);
+ return 0;
+}
+
+int fpgaaccess_release(struct inode *inode, struct file *filp){
+ filp->private_data=NULL;
+ return 0;
+}
+
+
+
+/********************************/
+/* init and release module */
+/********************************/
+
+static int __init fpgaaccess_init(void){
+ int result;
+ int fpgaaccess_major,fpgaaccess_minor;
+ u16 data;
+ struct fpgaaccess_dev *sdev;
+
+ fpgaaccess_major = 250;
+ fpgaaccess_minor = 0;
+
+ /* Allocate a private structure and reference it as driver's data */
+ PDEBUG("Allocate a private structure and reference it as driver s data\n");
+ sdev = (struct fpgaaccess_dev *)kmalloc(sizeof(struct fpgaaccess_dev),GFP_KERNEL);
+ if(sdev == NULL){
+ printk(KERN_WARNING "FPGAACCESS: unable to allocate private structure\n");
+ return -ENOMEM;
+ }
+
+ fpgaaccessdev = sdev;
+
+ /* Get the major and minor device numbers */
+ PDEBUG("Get the major and minor device numbers\n");
+ if(fpgaaccess_major){
+ devno = MKDEV(fpgaaccess_major,fpgaaccess_minor);
+ result = register_chrdev_region(devno, N_DEV,FPGAACCESS_NAME);
+ }else{
+ result = alloc_chrdev_region(&devno,fpgaaccess_minor,N_DEV,FPGAACCESS_NAME);
+ fpgaaccess_major = MAJOR(devno);
+ }
+ printk(KERN_INFO "fpgaaccess: MAJOR: %d MINOR: %d\n",MAJOR(devno),MINOR(devno));
+ if(result < 0){
+ printk(KERN_ERR "fpgaaccess: can't get major %d\n",fpgaaccess_major);
+ goto mkdev_error;
+ }
+
+ /* Init the cdev structure */
+ PDEBUG("Init the cdev structure\n");
+ cdev_init(&sdev->cdev,&fpgaaccess_fops);
+ sdev->cdev.owner = THIS_MODULE;
+
+ /* Add the device to the kernel, connecting cdev to major/minor number */
+ PDEBUG("Add the device to the kernel, connecting cdev to major/minor number \n");
+ result = cdev_add(&sdev->cdev,devno,1);
+ if(result < 0){
+ printk(KERN_WARNING "FPGAACCESS: can't add cdev\n");
+ goto cdevadd_error;
+ }
+
+ sdev->fpga_virtual_base_address = (void*)FPGA_BASE_ADDR;
+
+ /* ok module insered */
+ fpgaaccessdev=sdev;
+ printk(KERN_INFO "FPGAACCESS module insered\n");
+ return 0;
+
+cdevadd_error:
+ /* free major and minor number */
+ unregister_chrdev_region(devno,N_DEV);
+ printk(KERN_INFO "fpgaaccess module deleted\n");
+mkdev_error:
+ printk(KERN_ERR "%s: not insered\n",FPGAACCESS_NAME);
+ kfree(sdev);
+ return result;
+
+}
+
+static void __exit fpgaaccess_exit(void){
+ struct fpgaaccess_dev *sdev;
+
+ sdev = fpgaaccessdev;
+
+ /* delete the cdev structure */
+ cdev_del(&sdev->cdev);
+
+ /* free major and minor number */
+ unregister_chrdev_region(devno,N_DEV);
+ printk(KERN_INFO "fpgaaccess module deleted\n");
+
+ /* freed structure device */
+ kfree(sdev);
+}
+
+
Added: trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.h
===================================================================
--- trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.h (rev 0)
+++ trunk/target/linux/modules/fpga/fpgaaccess/fpgaaccess.h 2008-04-08 13:21:01 UTC (rev 794)
@@ -0,0 +1,121 @@
+/*
+ ***********************************************************************
+ * fpgaaccess.h
+ *
+ * (c) Copyright 2008 Armadeus project
+ * Fabien Marteau <fab...@ar...>
+ *
+ * A simple driver for reading and writing on
+ * fpga throught a character file /dev/fpgaaccess
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
+ */
+
+#ifndef __FPGAACCESS_H_
+#define __FPGAACCESS_H_
+
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
+#include <linux/config.h>
+#endif
+
+/* form module/drivers */
+#include <linux/init.h>
+#include <linux/module.h>
+
+/* for file operations */
+#include <linux/fs.h>
+#include <linux/cdev.h>
+
+/* copy_to_user function */
+#include <asm/uaccess.h>
+
+/* readw() writew() */
+#include <asm/io.h>
+
+/* hardware addresses */
+#include <asm/hardware.h>
+
+#endif
+
+/* for debugging messages*/
+#define FPGAACCESS_DEBUG
+
+#undef PDEBUG
+#ifdef FPGAACCESS
+# ifdef __KERNEL__
+ /* for kernel spage */
+# define PDEBUG(fmt,args...) printk(KERN_DEBUG "fpgaaccess : " fmt, ##args)
+# else
+ /* for user space */
+# define PDEBUG(fmt,args...) printk(stderr, fmt, ##args)
+# endif
+#else
+# define PDEBUG(fmt,args...) /* no debbuging message */
+#endif
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Fabien Marteau <fab...@ar...> - ARMadeus Systems");
+MODULE_DESCRIPTION("FPGA access device driver");
+
+/* some defines */
+
+#define FPGAACCESS_NAME "fpgaaccess"
+#define FPGA_BASE_ADDR IMX_CS1_VIRT
+#define FPGA_SIZE IMX_CS1_SIZE
+#define N_DEV 1
+
+
+/*************************/
+/* main device structures */
+/*************************/
+struct fpgaaccess_dev{
+ struct cdev cdev; /* Char device structure */
+ void * fpga_virtual_base_address; /* fpga register base address*/
+};
+
+static dev_t devno;
+struct fpgaaccess_dev *fpgaaccessdev;
+
+/*************************************/
+/* to read write fpgaaccess register */
+/*************************************/
+ssize_t fpgaaccess_read(struct file *fildes, char __user *buff,
+ size_t count, loff_t *offp);
+
+ssize_t fpgaaccess_write(struct file *fildes, const char __user *
+ buff,size_t count, loff_t *offp);
+int fpgaaccess_open(struct inode *inode, struct file *filp);
+
+int fpgaaccess_release(struct inode *, struct file *filp);
+
+struct file_operations fpgaaccess_fops = {
+ .owner = THIS_MODULE,
+ .read = fpgaaccess_read,
+ .write = fpgaaccess_write,
+ .open = fpgaaccess_open,
+ .release = fpgaaccess_release,
+};
+
+/********************************/
+/* init and release module */
+/********************************/
+
+static int __init fpgaaccess_init(void);
+static void __exit fpgaaccess_exit(void);
+
+module_init(fpgaaccess_init);
+module_exit(fpgaaccess_exit);
Added: trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c
===================================================================
--- trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c (rev 0)
+++ trunk/target/linux/modules/fpga/fpgaaccess/fpgaregs.c 2008-04-08 13:21:01 UTC (rev 794)
@@ -0,0 +1,94 @@
+/************************************************************************
+ * a program to write/read values on fpga address map
+ * 7 april 2008
+ * fpgaregs.c
+ *
+ * (c) Copyright 2008 Armadeus project
+ * Fabien Marteau <fab...@ar...>
+ *
+ * A simple driver for reading and writing on
+ * fpga throught a character file /dev/fpgaaccess
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+/* file management */
+#include <sys/stat.h>
+#include <fcntl.h>
+
+/* as name said */
+#include <signal.h>
+
+/* sleep, write(), read() */
+#include <unistd.h>
+
+/* converting string */
+#include <string.h>
+
+int ffpga;
+
+int main(int argc, char *argv[])
+{
+ unsigned short address;
+ unsigned short value;
+ int retval;
+
+ printf( "Testing button driver\n" );
+
+ if((argc < 2) || (argc > 3)){
+ perror("invalid arguments number\nfpgaregs fpga_reg_add [value]\n");
+ exit(EXIT_FAILURE);
+ }
+
+ ffpga=open("/dev/fpgaaccess",O_RDWR);
+ if(ffpga<0){
+ perror("can't open file /dev/fpgaaccess\n");
+ exit(EXIT_FAILURE);
+ }
+
+ address = (unsigned char )strtol(argv[1], (char **)NULL, 16);
+
+ if(address%2!=0){
+ perror("error address must be pair\n");
+ exit(EXIT_FAILURE);
+ }
+
+ /* write value at address */
+ if(argc == 3){
+ value = (unsigned char )strtol(argv[2], (char **)NULL, 16);
+ retval = pwrite(ffpga,(void *)&value,2,address);
+ if(retval<0){
+ perror("write error\n");
+ exit(EXIT_FAILURE);
+ }
+ printf("Wrote %04x at %08x\n",value,address+0x12000000);
+
+ /* read address value */
+ }else{
+ retval = pread(ffpga,(void *)&value,2,address);
+ if(retval<0){
+ perror("Read error\n");
+ exit(EXIT_FAILURE);
+ }
+ printf("Read %04x at %08x\n",value,address+0x12000000);
+ }
+
+ close(ffpga);
+ exit(0);
+}
Added: trunk/target/linux/modules/fpga/i2ctest/Kconfig
===================================================================
--- trunk/target/linux/modules/fpga/i2ctest/Kconfig (rev 0)
+++ trunk/target/linux/modules/fpga/i2ctest/Kconfig 2008-04-08 13:21:01 UTC (rev 794)
@@ -0,0 +1,8 @@
+#
+#
+
+config ARMADEUS_I2C_OCORE_IRQMNG
+ tristate "Driver for testing wishbone i2c-ocore-irq_mng"
+ default n
+ depends on ARMADEUS_FPGA_DRIVERS
+ ---help---
Added: trunk/target/linux/modules/fpga/i2ctest/Makefile
===================================================================
--- trunk/target/linux/modules/fpga/i2ctest/Makefile (rev 0)
+++ trunk/target/linux/modules/fpga/i2ctest/Makefile 2008-04-08 13:21:01 UTC (rev 794)
@@ -0,0 +1,37 @@
+#
+# Makefile for the Armadeus bus_i2ctest drivers
+#
+
+# Part executed when cali2ctest from kernel build system:
+ifneq ($(KERNELRELEASE),)
+
+obj-m += i2ctest.o
+
+i2ctest := i2ctest.o
+
+# Part executed when called from standard make in this directory:
+# (preferably use Makefile in parent directory)
+else
+
+BASE_DIR="../../../../../buildroot/"
+REL=`grep "BR2_PACKAGE_LINUX_VERSION=" $(BASE_DIR).config | \
+ sed "s/BR2_PACKAGE_LINUX_VERSION=\\"//" | sed "s/\\"//"`
+ARMADEUS_KERNEL_DIR=$(BASE_DIR)build_arm/linux-$(REL)
+KDIR := $(ARMADEUS_KERNEL_DIR)
+PWD := $(shell pwd)
+
+default:
+ $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
+ cp i2ctest.ko /tftpboot/
+
+test:
+ ~/armadeus/buildroot/build_arm/staging_dir/bin/arm-linux-gcc testi2ctest.c -o testi2ctest
+ chmod 755 testi2ctest
+ cp testi2ctest /tftpboot/
+
+clean:
+ rm -f *.*o \
+ rm -f Module.symvers
+
+endif
+
Property changes on: trunk/target/linux/modules/fpga/i2ctest/Makefile
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/target/linux/modules/fpga/i2ctest/README
===================================================================
--- trunk/target/linux/modules/fpga/i2ctest/README (rev 0)
+++ trunk/target/linux/modules/fpga/i2ctest/README 2008-04-08 13:21:01 UTC (rev 794)
@@ -0,0 +1,13 @@
+This is a really simple driver to test reading and writing
+a value on i2c bus throught ocore-irq_mng FPGA IP.
+
+To use it load i2ctest.ko module with insmod
+>insmod i2ctest.ko
+
+Then read /proc/i2c_test with cat
+> cat /proc/i2c_test
+
+This will send write command on component
+
+To read the value you wrote, read /proc/i2c_test2
+> cat /proc/i2c_test2
Added: trunk/target/linux/modules/fpga/i2ctest/i2ctest.c
===================================================================
--- trunk/target/linux/modules/fpga/i2ctest/i2ctest.c (rev 0)
+++ trunk/target/linux/modules/fpga/i2ctest/i2ctest.c 2008-04-08 13:21:01 UTC (rev 794)
@@ -0,0 +1,225 @@
+/* i2ctest.c
+ ***********************************************************************
+ *
+ * (c) Copyright 2008 Armadeus project
+ * Fabien Marteau <fab...@ar...>
+ * Driver for testing i2c IP ocore with irq_mngr
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
+ */
+
+#include "i2ctest.h"
+
+#define VALUE 0xbb
+#define ADDR 0x1D
+#define SUBADDR 0x16
+
+
+/***************************
+ * interrupt management
+ * *************************/
+
+static irqreturn_t fpga_interrupt(int irq,void *stuff,struct pt_regs *reg){
+ static int count = 0;
+ u16 data;
+
+ /**************/
+ /* write 0xbb */
+ /**************/
+ if(count == 0){
+ /*read RxACK bit from Status Register, should be 0 */
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
+ /* write to Transmit sub address, set WR bit acknowledge interrupt*/
+ iowrite16(SUBADDR<<8|I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+ /* acknowledge irq in irq manager*/
+ iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+ }else if(count == 1){
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
+ /* write to Transmit sub address, set WR bit acknowledge interrupt*/
+ iowrite16(VALUE<<8|I2C_STO|I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+ /* acknowledge irq in irq manager*/
+ iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count ++;
+ }else if(count == 2){
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
+ iowrite16(0x0000|I2C_IACK|I2C_STO,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+ /* acknowledge irq in irq manager*/
+ iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+
+ /***********************/
+ /* read the same value */
+ /***********************/
+ }else if(count == 3){
+ /*read RxACK bit from Status Register, should be 0 */
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
+ /* write 0x2C to Transmit sub address, set WR bit acknowledge interrupt*/
+ iowrite16(SUBADDR<<8|I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+ /* acknowledge irq in irq manager*/
+ iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+ }else if(count == 4){
+ ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
+ /* write adress on TXR and CTR register repeated start, acknowledge interrupt*/
+ iowrite16(ADDR<<9|I2C_ADD_READ|I2C_STA|I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+ /* acknowledge irq in irq manager*/
+ iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+ }else if(count == 5){
+ /* write on TXR and CTR register, set read bit,acknowledge interrupt*/
+ iowrite16(I2C_RD|I2C_ACK|I2C_IACK|I2C_STO,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+ /* acknowledge irq in irq manager*/
+ iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ count++;
+ }else if(count == 6){
+ data = ioread16(i2cdev->fpga_virtual_base_address + FPGA_I2C_RXT_SR);
+ /* write on TXR and CTR register, set read bit,acknowledge interrupt*/
+ iowrite16(I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+
+ /* acknowledge irq in irq manager*/
+ iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+
+ printk(KERN_INFO "read %04x\n",data);
+ count++;
+ }
+ return IRQ_HANDLED;
+}
+
+/****************************
+ * read proc
+ * **************************/
+
+static int read_proc(char *page,char **start,off_t offset,int count,int *eof,void *data){
+ /* if(down_interruptible(&i2cdev->sem))
+ return -ERESTARTSYS;*/
+
+ PDEBUG("Trying to write %04x on i2c slave\n",VALUE);
+
+ /* unmask interrupt for i2c in interrupt manager*/
+ iowrite16(0x0002,i2cdev->fpga_virtual_base_address + FPGA_IRQ_MASK);
+ /* set prescale for 400kHz*/
+ iowrite16(0x00BF,i2cdev->fpga_virtual_base_address + FPGA_I2C_PRESC);
+ PDEBUG("Write %04x at %04x\n",0x00BF,FPGA_I2C_PRESC);
+ /* set core enable and interrupt enable*/
+ iowrite16(I2C_EN|I2C_IEN,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_CTR);
+ PDEBUG("Write %04x at %04x\n",I2C_EN|I2C_IEN,FPGA_I2C_CTR);
+ /* write slave adresse on TXR and CTR register*/
+ iowrite16(ADDR<<9|I2C_STA|I2C_WR|I2C_IACK,i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+
+ PDEBUG("Write %04x at %04x\n",ADDR<<9|I2C_ADD_WRITE|I2C_STA|I2C_WR,FPGA_I2C_TXR_CR);
+
+ /* PDEBUG("Wrote ?\n");*/
+
+/* up(&i2cdev->sem);*/
+ return 0;
+}
+
+static int read_proc2(char *page,char **start,off_t offset,int count,int *eof,void *data){
+
+ PDEBUG("Trying to read on i2c slave\n");
+
+ /* write slave adresse on TXR and CTR register*/
+ iowrite16(ADDR<<9|I2C_ADD_WRITE|I2C_STA|I2C_WR|I2C_IACK,
+ i2cdev->fpga_virtual_base_address + FPGA_I2C_TXR_CR);
+ return 0;
+}
+
+/****************************
+* Module management
+* **************************/
+
+static int __init i2ctest_init(void){
+ int result;
+ u16 data;
+ result = 0;
+
+ mem = NULL;
+
+ /* Allocate a private structure and reference it as driver's data */
+ PDEBUG("Allocate a private structure and reference it as driver s data\n");
+ i2cdev = (struct i2ctest_dev *)kmalloc(sizeof(struct i2ctest_dev),GFP_KERNEL);
+ if(i2cdev == NULL){
+ printk(KERN_WARNING "I2CDEV: unable to allocate private structure\n");
+ return -ENOMEM;
+ }
+
+ /* Requested I/O memory */
+ if((i2cdev->fpga_virtual_base_address = ioremap(IMX_CS1_PHYS,IMX_CS1_SIZE))==NULL){
+ printk(KERN_ERR "ioremap error\n");
+ goto error;
+ }
+
+ /* irq registering */
+ if(request_irq(IRQ_GPIOA(1),(irq_handler_t)fpga_interrupt,IRQF_SHARED,"fpga",i2cdev)<0){
+ printk(KERN_ERR "Can't request fpga irq\n");
+ goto error;
+ }
+ //ioread16(i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK);
+ /* irq ack */
+ data=1;
+ if((result=iowrite16(data,i2cdev->fpga_virtual_base_address + FPGA_IRQ_ACK))<0)
+ goto error;
+
+ /* create proc entry */
+ create_proc_read_entry("i2c_test",0 /* default mode */,
+ NULL /* parent dir */, read_proc,
+ NULL /* client data */);
+
+ /* create proc entry */
+ create_proc_read_entry("i2c_test2",0 /* default mode */,
+ NULL /* parent dir */, read_proc2,
+ NULL /* client data */);
+
+ /* OK module inserted ! */
+ printk(KERN_INFO "i2ctest module insered\n");
+ return 0;
+
+error:
+ printk(KERN_ERR "%s: not inserted\n",DRIVER_NAME);
+ free_all();
+ return result;
+
+
+}
+
+static void __exit i2ctest_exit(void){
+ free_all();
+}
+
+static void free_all(void){
+
+ /* free irq*/
+ free_irq(IRQ_GPIOA(1),i2cdev);
+
+ /* Free the allocated memory */
+ kfree(i2cdev);
+
+ /* remove proc entry */
+ remove_proc_entry("i2c_test",0);
+
+ printk(KERN_INFO "i2ctest module deleted\n");
+}
+
+
Added: trunk/target/linux/modules/fpga/i2ctest/i2ctest.h
===================================================================
--- trunk/target/linux/modules/fpga/i2ctest/i2ctest.h (rev 0)
+++ trunk/target/linux/modules/fpga/i2ctest/i2ctest.h 2008-04-08 13:21:01 UTC (rev 794)
@@ -0,0 +1,127 @@
+/* i2ctest.h
+ ***********************************************************************
+ *
+ * (c) Copyright 2008 Armadeus project
+ * Fabien Marteau <fab...@ar...>
+ * module for testing i2c_master fpga IP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
+ --------------------------------------------
+ * 18 mars 2008
+ * initial version
+ */
+
+#ifndef __I2CTEST_H_
+#define __I2CTEST_H_
+
+#include <linux/version.h>
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
+#include <linux/config.h>
+#endif
+
+/* for module */
+#include <linux/init.h>
+#include <linux/module.h>
+
+/* proc entry */
+#include <linux/proc_fs.h>
+
+/* request_mem_region */
+#include <linux/ioport.h>
+
+/* readw() writew() */
+#include <asm/io.h>
+
+/* hardware addresses */
+#include <asm/hardware.h>
+
+/* interruptions */
+#include <linux/interrupt.h>
+#include <asm/irq.h>
+
+/* /proc */
+#include <linux/proc_fs.h>
+
+#endif
+
+/* for debugging messages*/
+//#define LED_DEBUG
+
+#undef PDEBUG
+#ifdef LED_DEBUG
+# ifdef __KERNEL__
+ /* for kernel spage */
+# define PDEBUG(fmt,args...) printk(KERN_DEBUG "i2ctest : " fmt, ##args)
+# else
+ /* for user space */
+# define PDEBUG(fmt,args...) printk(stderr, fmt, ##args)
+# endif
+#else
+# define PDEBUG(fmt,args...) /* no debbuging message */
+#endif
+
+#define FPGA_BUTTON 8
+#define FPGA_LED 4
+#define FPGA_IRQ_MASK 0
+#define FPGA_IRQ_PEND 2
+#define FPGA_IRQ_ACK 2
+
+#define FPGA_I2C_PRESC 0x10
+#define FPGA_I2C_CTR 0x12
+#define FPGA_I2C_TXR_CR 0x14
+#define FPGA_I2C_RXT_SR 0x16
+
+
+/* CTR register */
+#define I2C_EN 0x80
+#define I2C_IEN 0x40
+/* CR register */
+#define I2C_STA 0x80
+#define I2C_STO 0x40
+#define I2C_RD 0x20
+#define I2C_WR 0x10
+#define I2C_ACK 0x08
+#define I2C_IACK 0x01
+
+#define I2C_ADD_READ 0x0100
+#define I2C_ADD_WRITE 0
+
+#define DRIVER_NAME "i2ctest"
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Fabien Marteau <fab...@ar...> - ARMadeus Systems");
+MODULE_DESCRIPTION("I2C tester");
+
+struct i2ctest_dev {
+ struct semaphore sem;
+ void * fpga_virtual_base_address;
+};
+
+struct resource *mem; /* pointer to fpga led */
+
+struct i2ctest_dev *i2cdev;
+
+static int __init i2ctest_init(void);
+static void __exit i2ctest_exit(void);
+
+static int read_proc(char *page,char **start,off_t offset,int count,int *eof,void *data);
+static int read_proc2(char *page,char **start,off_t offset,int count,int *eof,void *data);
+static void free_all(void);
+
+static irqreturn_t fpga_interrupt(int irq,void *stuff,struct pt_regs *reg);
+
+module_init(i2ctest_init);
+module_exit(i2ctest_exit);
Modified: trunk/target/linux/modules/gpio/Makefile
===================================================================
--- trunk/target/linux/modules/gpio/Makefile 2008-04-05 09:12:51 UTC (rev 793)
+++ trunk/target/linux/modules/gpio/Makefile 2008-04-08 13:21:01 UTC (rev 794)
@@ -18,7 +18,7 @@
BASE_DIR="../../../../buildroot/"
REL=`grep "BR2_PACKAGE_LINUX_VERSION=" $(BASE_DIR).config | \
sed "s/BR2_PACKAGE_LINUX_VERSION=\\"//" | sed "s/\\"//"`
-ARMADEUS_KERNEL_DIR=$(BASE_DIR)build_arm_nofpu/linux-$(REL)
+ARMADEUS_KERNEL_DIR=$(BASE_DIR)build_arm/linux-$(REL)
KDIR := $(ARMADEUS_KERNEL_DIR)
PWD := $(shell pwd)
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <ar...@us...> - 2008-04-05 09:13:02
|
Revision: 793
http://armadeus.svn.sourceforge.net/armadeus/?rev=793&view=rev
Author: artemys
Date: 2008-04-05 02:12:51 -0700 (Sat, 05 Apr 2008)
Log Message:
-----------
[BUILDROOT][U-BOOT] Add support for U-Boot 2.0.0-rc3 (actual bootloader for APF27) in buildroot
Modified Paths:
--------------
branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/110-apx-tools.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk
Added Paths:
-----------
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/001-u-boot-2.0.0-rc3-flash-timings.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/002-u-boot-2.0.0-rc3-defaultenv-ipaddr.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/003-switch_to_fixed_ip_address.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/004-fix-some-compilation-problems.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/005-old-gcc-implement-muldiv3-for-arm.patch
Modified: branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in 2008-04-04 12:41:04 UTC (rev 792)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in 2008-04-05 09:12:51 UTC (rev 793)
@@ -1,5 +1,5 @@
-U-BOOT_TARGET_NAME=apx9328
+U-BOOT_TARGET_NAME=pcm038
LINUX_FORMAT=uImage
LINUX_KCONFIG=$(ARMADEUS_CONFIG_PATH)/linux-$(BR2_PACKAGE_LINUX_VERSION).config
Modified: branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/110-apx-tools.patch
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/110-apx-tools.patch 2008-04-04 12:41:04 UTC (rev 792)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/110-apx-tools.patch 2008-04-05 09:12:51 UTC (rev 793)
@@ -280,7 +280,7 @@
+ "\n"
+ " %s converts binary files (u-boot.bin) into so called \n"
+ " bootstrap records file (u-boot.brec) that are accepted by\n"
-+ " Motorola's MC9328MX1/L (a.k.a. DragaonBall i.MX) in \"Bootstrap Mode\" \n"
++ " Motorola's MC9328MX1/L (a.k.a. DragonBall i.MX) in \"Bootstrap Mode\" \n"
+ " add memory init commands and run command\n"
+ " at end of file\n"
+ " NOTE: \n"
Added: branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/001-u-boot-2.0.0-rc3-flash-timings.patch
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/001-u-boot-2.0.0-rc3-flash-timings.patch (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/001-u-boot-2.0.0-rc3-flash-timings.patch 2008-04-05 09:12:51 UTC (rev 793)
@@ -0,0 +1,29 @@
+Subject: pcm038: add flash timing initialization
+From: Robert Schwebel <r.s...@pe...>
+
+Add init code for the CS0 flash timing registers. These values are not
+optimized yet, they are more or less copied from the Windows CE
+installation.
+
+Signed-off-by: Robert Schwebel <r.s...@pe...>
+
+---
+ board/pcm038/lowlevel_init.S | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+Index: board/pcm038/lowlevel_init.S
+===================================================================
+--- u-boot/board/pcm038/lowlevel_init.S.orig
++++ u-boot/board/pcm038/lowlevel_init.S
+@@ -158,6 +158,11 @@ board_init_lowlevel:
+ writel(0x09030908, PCDR1) /* PERDIV1=08 @133 MHz */
+ /* PERDIV1=04 @266 MHz */
+
++ /* configure 16 bit nor flash on cs0 */
++ writel(0x0000CC03, 0xD8002000)
++ writel(0xa0330D01, 0xD8002004)
++ writel(0x00220800, 0xD8002008)
++
+ /* skip sdram initialization if we run from ram */
+ cmp pc, #0xa0000000
+ bls 1f
Added: branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/002-u-boot-2.0.0-rc3-defaultenv-ipaddr.patch
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/002-u-boot-2.0.0-rc3-defaultenv-ipaddr.patch (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/002-u-boot-2.0.0-rc3-defaultenv-ipaddr.patch 2008-04-05 09:12:51 UTC (rev 793)
@@ -0,0 +1,56 @@
+Subject: pcm038: fix default environment wrt. ip address
+From: Robert Schwebel <r.s...@pe...>
+
+The boot script doesn't honour the ip= parameter when booting from flash
+only.
+
+Signed-off-by: Robert Schwebel <r.s...@pe...>
+
+---
+ board/pcm038/env/bin/boot | 14 ++++++++------
+ board/pcm038/env/config | 3 ++-
+ 2 files changed, 10 insertions(+), 7 deletions(-)
+
+Index: board/pcm038/env/bin/boot
+===================================================================
+--- u-boot/board/pcm038/env/bin/boot.orig
++++ u-boot/board/pcm038/env/bin/boot
+@@ -12,14 +12,15 @@ if [ x$1 = xnet ]; then
+ kernel=net
+ fi
+
+-if [ $root = flash ]; then
++if [ x$ip = xdhcp ]; then
++ bootargs="$bootargs ip=dhcp"
++else
++ bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
++fi
++
++if [ x$root = xflash ]; then
+ bootargs="$bootargs root=$rootpart rootfstype=jffs2"
+ else
+- if [ x$ip = xdhcp ]; then
+- bootargs="$bootargs ip=dhcp"
+- else
+- bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
+- fi
+ bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
+ fi
+
+@@ -34,3 +35,4 @@ if [ $kernel = net ]; then
+ else
+ bootm /dev/nor0.kernel
+ fi
++
+Index: board/pcm038/env/config
+===================================================================
+--- u-boot/board/pcm038/env/config.orig
++++ u-boot/board/pcm038/env/config
+@@ -22,4 +22,5 @@ nfsroot="/ptx/work/octopus/rsc/svn/osela
+ bootargs="console=ttymxc0,115200"
+
+ mtdparts="128k(uboot)ro,128k(ubootenv),1536k(kernel),-(root)"
+-rootpart="/dev/mtdblock3"
+\ No newline at end of file
++rootpart="/dev/mtdblock3"
++
Added: branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/003-switch_to_fixed_ip_address.patch
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/003-switch_to_fixed_ip_address.patch (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/003-switch_to_fixed_ip_address.patch 2008-04-05 09:12:51 UTC (rev 793)
@@ -0,0 +1,38 @@
+Subject: pcm038: default environment should use fixed ip addresses
+From: Alexander Bauer <A....@ph...>
+
+To be conform with other documents, a static ip configuration should be used.
+And kernel and root filesystem should be loaded from flash as the default
+behaviour.
+
+Signed-off-by: Alexander Bauer <A....@ph...>
+Signed-off-by: Juergen Beisert <j.b...@pe...>
+
+Index: u-boot-2.0.0-rc3/board/pcm038/env/config
+===================================================================
+--- u-boot-2.0.0-rc3.orig/board/pcm038/env/config 2008-01-11 10:44:55.000000000 +0100
++++ u-boot-2.0.0-rc3/board/pcm038/env/config 2008-01-11 10:47:30.000000000 +0100
+@@ -1,16 +1,16 @@
+ #!/bin/sh
+
+ # can be either 'net' or 'flash'
+-kernel=net
+-root=net
++kernel=flash
++root=flash
+
+-# use 'dhcp' todo dhcp in uboot and in kernel
+-ip=dhcp
++# enable 'dhcp' todo dhcp in uboot and in kernel
++#ip=dhcp
+
+-eth0.ipaddr=192.168.23.164
++eth0.ipaddr=192.168.3.11
+ eth0.netmask=255.255.255.0
+-eth0.gateway=192.168.23.2
+-eth0.serverip=192.168.23.2
++eth0.gateway=
++eth0.serverip=192.168.3.10
+ eth0.ethaddr=00:50:c2:72:a7:4a
+
+ uimage=uImage-pcm038
Added: branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/004-fix-some-compilation-problems.patch
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/004-fix-some-compilation-problems.patch (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/004-fix-some-compilation-problems.patch 2008-04-05 09:12:51 UTC (rev 793)
@@ -0,0 +1,16 @@
+--- u-boot-2.0.0-rc3/arch/arm/Makefile 2007-11-29 13:56:46.000000000 +0100
++++ u-boot-2.0.0-rc3.mod/arch/arm/Makefile 2008-04-04 16:11:48.000000000 +0200
+@@ -19,7 +19,7 @@
+
+ TEXT_BASE = $(CONFIG_TEXT_BASE)
+
+-CPPFLAGS += -mabi=apcs-gnu -DTEXT_BASE=$(TEXT_BASE) -P
++CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -P
+ CFLAGS := -fno-common -msoft-float -Os
+
+ ifeq ($(incdir-y),)
+--- u-boot-2.0.0-rc3/scripts/mod/empty.c 2007-11-29 13:56:46.000000000 +0100
++++ u-boot-2.0.0-rc3.mod/scripts/mod/empty.c 2008-04-04 16:21:57.000000000 +0200
+@@ -1 +1,2 @@
+ /* empty file to figure out endianness / word size */
++static int toto=0;
Added: branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/005-old-gcc-implement-muldiv3-for-arm.patch
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/005-old-gcc-implement-muldiv3-for-arm.patch (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/patches/2.0.0-rc3/005-old-gcc-implement-muldiv3-for-arm.patch 2008-04-05 09:12:51 UTC (rev 793)
@@ -0,0 +1,59 @@
+--- u-boot-2.0.0-rc3/arch/arm/lib/Makefile 2007-11-29 13:56:46.000000000 +0100
++++ u-boot-2.0.0-rc3.mod/arch/arm/lib/Makefile 2008-04-04 17:11:48.000000000 +0200
+@@ -9,6 +9,7 @@
+ obj-y += _umodsi3.o
+ obj-y += _lshrdi3.o
+ obj-y += arm.o
++obj-y += _muldi3.o
+ obj-$(CONFIG_MODULES) += module.o
+ extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += u-boot.lds
+
+--- u-boot-2.0.0-rc3/arch/arm/lib/_muldi3.S 1970-01-01 01:00:00.000000000 +0100
++++ u-boot-2.0.0-rc3.mod/arch/arm/lib/_muldi3.S 2008-04-04 17:14:25.000000000 +0200
+@@ -0,0 +1,46 @@
++/*
++ * linux/arch/arm/lib/muldi3.S
++ *
++ * Author: Nicolas Pitre
++ * Created: Oct 19, 2005
++ * Copyright: Monta Vista Software, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/*#include <linux/linkage.h>*/
++
++#ifdef __ARMEB__
++#define xh r0
++#define xl r1
++#define yh r2
++#define yl r3
++#else
++#define xl r0
++#define xh r1
++#define yl r2
++#define yh r3
++#endif
++
++.globl __muldi3
++/*ENTRY(__aeabi_lmul)*/
++__muldi3:
++
++ mul xh, yl, xh
++ mla xh, xl, yh, xh
++ mov ip, xl, lsr #16
++ mov yh, yl, lsr #16
++ bic xl, xl, ip, lsl #16
++ bic yl, yl, yh, lsl #16
++ mla xh, yh, ip, xh
++ mul yh, xl, yh
++ mul xl, yl, xl
++ mul ip, yl, ip
++ adds xl, xl, yh, lsl #16
++ adc xh, xh, yh, lsr #16
++ adds xl, xl, ip, lsl #16
++ adc xh, xh, ip, lsr #16
++ mov pc, lr
++
Modified: branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk 2008-04-04 12:41:04 UTC (rev 792)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk 2008-04-05 09:12:51 UTC (rev 793)
@@ -3,20 +3,36 @@
# u-boot
#
#############################################################
+# On APF27:
+ifneq ($(BR2_TARGET_ARMADEUS_APF27),)
+U-BOOT_VERSION:=2.0.0-rc3
+U-BOOT_SOURCE:=u-boot-$(U-BOOT_VERSION).tar.gz
+U-BOOT_SITE:=http://www.pengutronix.de/software/u-boot/download
+U-BOOT_DIR:=$(BUILD_DIR)/u-boot-$(U-BOOT_VERSION)
+#U-BOOT_TARGET_NAME:=pcm038 # overloaded by ../apf27/Makefile.in
+U-BOOT_UNZIP:=zcat
+U-BOOT_GENERATED_BIN:=uboot.bin
+ADDITIONAL_MAKE_PARAMETERS:=CONFIG_NOSOFTFLOAT=1 ARCH=arm
+U-BOOT_TARGET_CONFIG=$(U-BOOT_TARGET_NAME)_defconfig
+else # APx9328:
U-BOOT_VERSION:=1.1.6
U-BOOT_SOURCE:=u-boot-$(U-BOOT_VERSION).tar.bz2
U-BOOT_SITE:=http://ovh.dl.sourceforge.net/sourceforge/u-boot
U-BOOT_DIR:=$(BUILD_DIR)/u-boot-$(U-BOOT_VERSION)
+#U-BOOT_TARGET_NAME:=apx9328 overloaded by ../apx9328/Makefile.in
+U-BOOT_UNZIP:=bzcat
+U-BOOT_GENERATED_BIN:=u-boot.bin
+U-BOOT_TARGET_CONFIG=$(U-BOOT_TARGET_NAME)_config
+endif
U-BOOT_PACKAGE_DIR:=$(ARMADEUS_PATH)/u-boot
-U-BOOT_TARGET_NAME:=apx9328
U-BOOT_TARGET_IPADDR:=$(strip $(subst ",, $(BR2_TARGET_UBOOT_IPADDR_ARMADEUS)))
U-BOOT_TARGET_SERVERIP:=$(strip $(subst ",, $(BR2_TARGET_UBOOT_SERVERIP_ARMADEUS)))
U-BOOT_TARGET_GATEWAY:=$(strip $(subst ",, $(BR2_TARGET_UBOOT_GATEWAY_ARMADEUS)))
U-BOOT_TARGET_NETMASK:=$(strip $(subst ",, $(BR2_TARGET_UBOOT_NETMASK_ARMADEUS)))
U-BOOT_TARGET_ETHADDR:=$(strip $(subst ",, $(BR2_TARGET_UBOOT_ETHADDR_ARMADEUS)))
-U-BOOT_TARGET_FILE:=$(U-BOOT_DIR)/include/configs/$(U-BOOT_TARGET_NAME).h
+U-BOOT_TARGET_FILE=$(U-BOOT_DIR)/include/configs/$(U-BOOT_TARGET_NAME).h
###-----
$(DL_DIR)/$(U-BOOT_SOURCE):
@@ -27,13 +43,17 @@
###-----
$(U-BOOT_DIR)/.unpacked: $(DL_DIR)/$(U-BOOT_SOURCE)
- bzcat $(DL_DIR)/$(U-BOOT_SOURCE) | tar -C $(BUILD_DIR) $(TAR_OPTIONS) -
+ $(U-BOOT_UNZIP) $(DL_DIR)/$(U-BOOT_SOURCE) | tar -C $(BUILD_DIR) $(TAR_OPTIONS) -
toolchain/patch-kernel.sh $(U-BOOT_DIR) $(U-BOOT_PACKAGE_DIR)/patches/$(U-BOOT_VERSION) *.patch
touch $(U-BOOT_DIR)/.unpacked
###-----
$(U-BOOT_DIR)/.configured: $(U-BOOT_DIR)/.unpacked
- make -C $(U-BOOT_DIR) CROSS_COMPILE=$(TARGET_CROSS) $(U-BOOT_TARGET_NAME)_config
+ make -C $(U-BOOT_DIR) CROSS_COMPILE=$(TARGET_CROSS) $(ADDITIONAL_MAKE_PARAMETERS) $(U-BOOT_TARGET_CONFIG)
+ifneq ($(BR2_TARGET_ARMADEUS_APF27),) # if APF27
+ echo "Additional U-Boot configuration"
+ touch $(U-BOOT_DIR)/u-boot.brec
+else # if APx9328
ifneq ($(BR2_TARGET_ARMADEUS_SDRAM_SIZE),)
$(SED) "s,^#define CFG_SDRAM_MBYTE_SYZE.*,#define CFG_SDRAM_MBYTE_SYZE $(BR2_TARGET_ARMADEUS_SDRAM_SIZE),g;"\
$(U-BOOT_TARGET_FILE)
@@ -60,44 +80,40 @@
ifneq ($(U-BOOT_TARGET_IPADDR),)
$(SED) 's,^#define CONFIG_IPADDR.*,#define CONFIG_IPADDR $(U-BOOT_TARGET_IPADDR),g' \
$(U-BOOT_TARGET_FILE)
- echo "#define CONFIG_IPADDR $(U-BOOT_TARGET_IPADDR)"
endif
ifneq ($(U-BOOT_TARGET_SERVERIP),)
$(SED) 's,^#define CONFIG_SERVERIP.*,#define CONFIG_SERVERIP $(U-BOOT_TARGET_SERVERIP),g' \
$(U-BOOT_TARGET_FILE)
- echo "#define CONFIG_SERVERIP $(U-BOOT_TARGET_SERVERIP)"
endif
ifneq ($(U-BOOT_TARGET_GATEWAY),)
$(SED) 's,^#define CONFIG_GATEWAYIP.*,#define CONFIG_GATEWAYIP $(U-BOOT_TARGET_GATEWAY),g' \
$(U-BOOT_TARGET_FILE)
- echo "#define CONFIG_GATEWAYIP $(U-BOOT_TARGET_GATEWAY)"
endif
ifneq ($(U-BOOT_TARGET_NETMASK),)
$(SED) 's,^#define CONFIG_NETMASK.*,#define CONFIG_NETMASK $(U-BOOT_TARGET_NETMASK),g' \
$(U-BOOT_TARGET_FILE)
- echo "#define CONFIG_NETMASK $(U-BOOT_TARGET_NETMASK)"
endif
ifneq ($(U-BOOT_TARGET_ETHADDR),)
$(SED) 's,^#define CONFIG_ETHADDR.*,#define CONFIG_ETHADDR $(U-BOOT_TARGET_ETHADDR),g' \
$(U-BOOT_TARGET_FILE)
- echo "#define CONFIG_ETHADDR $(U-BOOT_TARGET_ETHADDR)"
endif
+endif # BR2_TARGET_ARMADEUS_APF27
touch $(U-BOOT_DIR)/.configured
###-----
-$(U-BOOT_DIR)/u-boot.bin: $(U-BOOT_DIR)/.configured
- make -C $(U-BOOT_DIR) CROSS_COMPILE=$(TARGET_CROSS)
- touch -c $(U-BOOT_DIR)/u-boot.bin
+$(U-BOOT_DIR)/$(U-BOOT_GENERATED_BIN): $(U-BOOT_DIR)/.configured
+ make -C $(U-BOOT_DIR) CROSS_COMPILE=$(TARGET_CROSS) $(ADDITIONAL_MAKE_PARAMETERS)
+ touch -c $(U-BOOT_DIR)/$(U-BOOT_GENERATED_BIN)
###-----
$(BINARIES_DIR)/u-boot.brec: $(U-BOOT_DIR)/u-boot.brec
mkdir -p $(BINARIES_DIR)
- cp $(U-BOOT_DIR)/u-boot.brec $@
+ cp $^ $@
###-----
-$(BINARIES_DIR)/u-boot.bin: $(U-BOOT_DIR)/u-boot.bin
+$(BINARIES_DIR)/u-boot.bin: $(U-BOOT_DIR)/$(U-BOOT_GENERATED_BIN)
mkdir -p $(BINARIES_DIR)
- cp $(U-BOOT_DIR)/u-boot.bin $@
+ cp $^ $@
###-----
u-boot: $(BINARIES_DIR)/u-boot.bin $(BINARIES_DIR)/u-boot.brec
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <ar...@us...> - 2008-04-04 12:41:02
|
Revision: 792
http://armadeus.svn.sourceforge.net/armadeus/?rev=792&view=rev
Author: artemys
Date: 2008-04-04 05:41:04 -0700 (Fri, 04 Apr 2008)
Log Message:
-----------
[BUILDROOT] Now U-Boot patches are separated for each version and default network parameters may be changed in menuconfig
Modified Paths:
--------------
branches/apf2/buildroot/target/device/armadeus/Config.in
branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk
Added Paths:
-----------
branches/apf2/buildroot/target/device/armadeus/u-boot/Config.in
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/100-apx9328.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/101-u-boot-apx9328.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/110-apx-tools.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/120-apx-example.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/140-apx-dm9000.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/150-u-boot-imx.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.1.6/200-u-boot-spartan.patch
Removed Paths:
-------------
branches/apf2/buildroot/target/device/armadeus/u-boot/100-apx9328.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/101-u-boot-apx9328.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/110-apx-tools.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/120-apx-example.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/140-apx-dm9000.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/150-u-boot-imx.patch
branches/apf2/buildroot/target/device/armadeus/u-boot/200-u-boot-spartan.patch
Modified: branches/apf2/buildroot/target/device/armadeus/Config.in
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/Config.in 2008-04-03 17:08:58 UTC (rev 791)
+++ branches/apf2/buildroot/target/device/armadeus/Config.in 2008-04-04 12:41:04 UTC (rev 792)
@@ -94,12 +94,7 @@
default "2.6.24.3" if BR2_PACKAGE_LINUX_VERSION_2_6_24
default "2.6.25-rc7" if BR2_PACKAGE_LINUX_VERSION_2_6_25
-config BR2_TARGET_U-BOOT
- bool "U-Boot"
- default n
- depends BR2_arm && BR2_TARGET_ARMADEUS
- help
- The U-Boot universal bootloader for embedded systems.
+source "target/device/armadeus/u-boot/Config.in"
endif
Deleted: branches/apf2/buildroot/target/device/armadeus/u-boot/100-apx9328.patch
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/100-apx9328.patch 2008-04-03 17:08:58 UTC (rev 791)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/100-apx9328.patch 2008-04-04 12:41:04 UTC (rev 792)
@@ -1,2257 +0,0 @@
-diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/apx9328.c u-boot-1.1.6/board/apx9328/apx9328.c
---- ref/u-boot-1.1.6/board/apx9328/apx9328.c 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/board/apx9328/apx9328.c 2006-11-26 20:28:03.000000000 +0100
-@@ -0,0 +1,75 @@
-+/*
-+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+
-+#include <common.h>
-+#include <asm/arch/imx-regs.h>
-+#include "apx9328fpga.h"
-+
-+extern void imx_gpio_mode (int gpio_mode);
-+
-+int
-+board_init (void)
-+{
-+ DECLARE_GLOBAL_DATA_PTR;
-+
-+ gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
-+ gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
-+
-+ return 0;
-+}
-+
-+int
-+dram_init (void)
-+{
-+ DECLARE_GLOBAL_DATA_PTR;
-+
-+#if ( CONFIG_NR_DRAM_BANKS > 0 )
-+ gd->bd->bi_dram[0].start = CFG_SDRAM_1_BASE;
-+ gd->bd->bi_dram[0].size = CFG_SDRAM_1_SIZE;
-+#endif
-+#if ( CONFIG_NR_DRAM_BANKS > 1 )
-+ gd->bd->bi_dram[1].start = CFG_SDRAM_2_BASE;
-+ gd->bd->bi_dram[1].size = CFG_SDRAM_2_SIZE;
-+#endif
-+
-+ return 0;
-+}
-+
-+/*
-+ * Miscellaneous intialization
-+ */
-+int
-+misc_init_r (void)
-+{
-+#if (CONFIG_FPGA)
-+ APX9328_init_fpga ();
-+#endif
-+
-+#if (CONFIG_DRIVER_DM9000)
-+ imx_gpio_mode (GPIO_PORTB | GPIO_GPIO | GPIO_IN | 14);
-+#endif
-+ return 0;
-+}
-+
-+void
-+show_boot_progress (int status)
-+{
-+ return;
-+}
-diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/apx9328fpga.c u-boot-1.1.6/board/apx9328/apx9328fpga.c
---- ref/u-boot-1.1.6/board/apx9328/apx9328fpga.c 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/board/apx9328/apx9328fpga.c 2006-11-26 20:28:03.000000000 +0100
-@@ -0,0 +1,100 @@
-+/*
-+ * (C) Copyright 2005
-+ * Nicolas Colombin <th...@us...>
-+ * Eric Jarrige <jo...@us...>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+
-+/*
-+ * Spartan 3 FPGA configuration support for the APX9328 daughter board
-+ */
-+
-+#include <common.h>
-+#include <spartan3.h>
-+#include <command.h>
-+#include <asm/arch/imx-regs.h>
-+#include <asm/io.h>
-+#include "apx9328fpga.h"
-+
-+#if (CONFIG_FPGA)
-+#if 0
-+#define FPGA_DEBUG
-+#endif
-+
-+#ifdef FPGA_DEBUG
-+#define PRINTF(fmt,args...) printf (fmt ,##args)
-+#else
-+#define PRINTF(fmt,args...)
-+#endif
-+
-+/* Note that these are pointers to code that is in Flash. They will be
-+ * relocated at runtime.
-+ * Spartan3 code is used to download our Spartan 3 :) code is compatible.
-+ * Just take care about the file size
-+*/
-+Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
-+ fpga_pre_fn,
-+ fpga_pgm_fn,
-+ fpga_clk_fn,
-+ fpga_init_fn,
-+ fpga_done_fn,
-+ fpga_wr_fn,
-+};
-+
-+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-+ {Xilinx_Spartan3,
-+ slave_serial,
-+ XILINX_XC3S400_SIZE,
-+ (void *) &fpga_fns,
-+ 0}
-+};
-+
-+/*
-+ * Initialize the fpga. Return 1 on success, 0 on failure.
-+ */
-+int
-+APX9328_init_fpga (void)
-+{
-+ char *autoload = getenv ("firmware_autoload");
-+ DECLARE_GLOBAL_DATA_PTR;
-+
-+ int i,lout=1;
-+
-+ PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
-+ __FUNCTION__, __LINE__, gd->reloc_off);
-+ fpga_init (gd->reloc_off);
-+
-+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
-+ PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
-+ fpga_add (fpga_xilinx, &fpga[i]);
-+ }
-+
-+ if (( autoload ) && (0 == strcmp(autoload, "1"))) {
-+ if (FPGA_SUCCESS != fpga_load( 0, (void *)CONFIG_FIRMWARE_ADDR,
-+ (size_t) CONFIG_FIRMWARE_LEN )) {
-+ lout = 0;
-+ printf("Firmware not loaded!\n");
-+ }
-+ }
-+ return 1;
-+}
-+
-+#endif /* CONFIG_FPGA */
-diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/apx9328fpga.h u-boot-1.1.6/board/apx9328/apx9328fpga.h
---- ref/u-boot-1.1.6/board/apx9328/apx9328fpga.h 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/board/apx9328/apx9328fpga.h 2006-11-26 20:28:03.000000000 +0100
-@@ -0,0 +1,31 @@
-+/*
-+ * (C) Copyright 2002
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+
-+/*
-+ * Spartan 3 FPGA configuration support for the APX9328 daughter board
-+ */
-+
-+#include "fpga.h"
-+extern int APX9328_init_fpga (void);
-diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/config.mk u-boot-1.1.6/board/apx9328/config.mk
---- ref/u-boot-1.1.6/board/apx9328/config.mk 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/board/apx9328/config.mk 2006-11-26 20:28:03.000000000 +0100
-@@ -0,0 +1,10 @@
-+#
-+# This config file is used for compilation of armadeus sources
-+#
-+# You might change location of U-Boot in memory by setting right TEXT_BASE.
-+# This allows for example having one copy located at the end of ram and stored
-+# in flash device and later on while developing use other location to test
-+# the code in RAM device only.
-+#
-+
-+TEXT_BASE = 0x0BF80000
-diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/fpga.c u-boot-1.1.6/board/apx9328/fpga.c
---- ref/u-boot-1.1.6/board/apx9328/fpga.c 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/board/apx9328/fpga.c 2006-11-26 20:28:03.000000000 +0100
-@@ -0,0 +1,140 @@
-+/*
-+ * (C) Copyright 2002
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+#include <common.h>
-+
-+#if (CONFIG_FPGA)
-+
-+#include <asm/arch/imx-regs.h>
-+#include <asm/io.h>
-+#include <config.h>
-+
-+extern void imx_gpio_mode (int gpio_mode);
-+
-+
-+#define GPIO_PORT(x) ((x >> 5) & 3)
-+#define GPIO_SET(x) (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
-+#define GPIO_CLEAR(x) (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
-+#define GPIO_WRITE(x,y) ( y ? GPIO_SET(x) : GPIO_CLEAR(x) )
-+#define GPIO_READ(x) ((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK))))
-+
-+#if 0
-+#define FPGA_DEBUG
-+#endif
-+
-+#ifdef FPGA_DEBUG
-+#define PRINTF(fmt,args...) printf (fmt ,##args)
-+#else
-+#define PRINTF(fmt,args...)
-+#endif
-+
-+/*
-+ * Port bit numbers for the serial slave controls
-+ */
-+#define FPGA_INIT CFG_FPGA_INIT
-+#define FPGA_DONE CFG_FPGA_DONE
-+#define FPGA_DIN CFG_FPGA_DATA
-+#define FPGA_PROGRAM CFG_FPGA_PRG
-+#define FPGA_CLOCK CFG_FPGA_CLK
-+
-+/* Note that these are pointers to code that is in Flash. They will be
-+ * relocated at runtime.
-+ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
-+ * Just take care about the file size
-+*/
-+
-+/*
-+ * nitialize GPIO port B before download
-+ */
-+int
-+fpga_pre_fn (int cookie)
-+{
-+ PRINTF ("%s:%d: FPGA PRE ", __FUNCTION__, __LINE__);
-+
-+ // Initialize GPIO pins
-+ imx_gpio_mode (FPGA_INIT | GPIO_GPIO | GPIO_IN );
-+ imx_gpio_mode (FPGA_DONE | GPIO_GPIO | GPIO_IN );
-+ imx_gpio_mode (FPGA_DIN | GPIO_GPIO | GPIO_OUT );
-+ imx_gpio_mode (FPGA_PROGRAM | GPIO_GPIO | GPIO_OUT );
-+ imx_gpio_mode (FPGA_CLOCK | GPIO_GPIO | GPIO_OUT );
-+ return cookie;
-+}
-+
-+/*
-+ * Set the FPGA's active-low program line to the specified level
-+ */
-+int
-+fpga_pgm_fn (int assert, int flush, int cookie)
-+{
-+ PRINTF ("%s:%d: FPGA PROGRAM %s", __FUNCTION__, __LINE__,
-+ assert?"high":"low");
-+ GPIO_WRITE( FPGA_PROGRAM, !assert);
-+ return assert;
-+}
-+
-+/*
-+ * Set the FPGA's active-high clock line to the specified level
-+ */
-+int
-+fpga_clk_fn (int assert_clk, int flush, int cookie)
-+{
-+ PRINTF ("%s:%d: FPGA CLOCK %s", __FUNCTION__, __LINE__,
-+ assert_clk?"high":"low");
-+ GPIO_WRITE( FPGA_CLOCK, assert_clk);
-+ return assert_clk;
-+}
-+
-+/*
-+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
-+ * asserted (low).
-+ */
-+int
-+fpga_init_fn (int cookie)
-+{
-+ PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
-+ return(!GPIO_READ(FPGA_INIT));
-+}
-+
-+/*
-+ * Test the state of the active-high FPGA DONE pin
-+ */
-+int
-+fpga_done_fn (int cookie)
-+{
-+ PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
-+ return(GPIO_READ(FPGA_DONE));
-+}
-+
-+/*
-+ * Set the FPGA's data line to the specified level
-+ */
-+int
-+fpga_wr_fn (int assert_write, int flush, int cookie)
-+{
-+ PRINTF ("%s:%d: DATA write... ", __FUNCTION__, __LINE__);
-+ GPIO_WRITE( FPGA_DIN, assert_write);
-+ return assert_write;
-+}
-+
-+#endif /* CONFIG_FPGA */
-diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/fpga.h u-boot-1.1.6/board/apx9328/fpga.h
---- ref/u-boot-1.1.6/board/apx9328/fpga.h 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/board/apx9328/fpga.h 2006-11-26 20:28:03.000000000 +0100
-@@ -0,0 +1,30 @@
-+/*
-+ * (C) Copyright 2002
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+extern int fpga_pre_fn (int cookie);
-+extern int fpga_pgm_fn (int assert_pgm, int flush, int cookie);
-+extern int fpga_init_fn (int cookie);
-+extern int fpga_done_fn (int cookie);
-+extern int fpga_clk_fn (int assert_clk, int flush, int cookie);
-+extern int fpga_wr_fn (int assert_write, int flush, int cookie);
-diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/i2c.c u-boot-1.1.6/board/apx9328/i2c.c
---- ref/u-boot-1.1.6/board/apx9328/i2c.c 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/board/apx9328/i2c.c 2006-11-26 20:28:03.000000000 +0100
-@@ -0,0 +1,327 @@
-+/*
-+ * Eric Jarrige <jo...@us...>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ *
-+ */
-+
-+#include <common.h>
-+
-+#ifdef CONFIG_HARD_I2C
-+
-+#include <asm/io.h>
-+#include <asm/arch/imx-regs.h>
-+#include <i2c.h>
-+
-+/*#define DEBUG_I2C*/
-+
-+extern void imx_gpio_mode (int gpio_mode);
-+
-+/*-----------------------------------------------------------------------
-+ * Definitions
-+ */
-+
-+#define I2C_ACK 0 /* level to ack a byte */
-+#define I2C_NOACK 1 /* level to noack a byte */
-+
-+
-+#ifdef DEBUG_I2C
-+#define PRINTD(fmt,args...) do { \
-+ DECLARE_GLOBAL_DATA_PTR; \
-+ if (gd->have_console) \
-+ printf (fmt ,##args); \
-+ } while (0)
-+#else
-+#define PRINTD(fmt,args...)
-+#endif
-+
-+/*-----------------------------------------------------------------------
-+ * Local functions
-+ */
-+
-+/*-----------------------------------------------------------------------
-+ * START: High -> Low on SDA while SCL is High
-+ * after check for a bus free
-+ */
-+static void
-+imxi2c_send_start (void)
-+{
-+ while ((I2SR & I2SR_IBB)) ;
-+ I2CR |= I2CR_MSTA;
-+ I2SR &= ~I2SR_IIF;
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * STOP: Low -> High on SDA while SCL is High
-+ * after the end of previous transfer
-+ */
-+static void
-+imxi2c_send_stop (void)
-+{
-+ while (!(I2SR & I2SR_ICF)) ;
-+ I2CR &= ~I2CR_MSTA;
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * Send 8 bits and look for an acknowledgement.
-+ */
-+static int
-+imxi2c_write_byte (uchar data)
-+{
-+ while (!(I2SR & I2SR_ICF)) ; /* Wait end of transfer */
-+
-+ I2CR |= I2CR_MTX;
-+ I2SR &= ~I2SR_IIF;
-+ I2DR = data;
-+
-+ while (!(I2SR & I2SR_IIF)) ; /* checking IIF before ICF seems required */
-+
-+ I2SR &= ~I2SR_IIF;
-+
-+ while (!(I2SR & I2SR_ICF)) ; /* Wait end of transfer */
-+
-+ return (I2SR & I2SR_RXAK); /* not a nack is an ack */
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * if ack == I2C_ACK, ACK the byte so can continue reading, else
-+ * send I2C_NOACK to end the read.
-+ */
-+static uchar
-+imxi2c_read_byte (int ack)
-+{
-+ int data;
-+
-+ while (!(I2SR & I2SR_ICF)) ;
-+ I2CR &= ~I2CR_MTX;
-+
-+ if (ack)
-+ {
-+ I2CR |= I2CR_TXAK;
-+ }
-+ else
-+ {
-+ I2CR &= ~I2CR_TXAK;
-+ }
-+
-+ data = I2DR;
-+ return (data);
-+}
-+
-+/* ------------------------------------------------------------------------
-+ * API Functions
-+ * ------------------------------------------------------------------------
-+ */
-+
-+/*-----------------------------------------------------------------------
-+ * i2c_init compute the i2c divider to reach the requested speed
-+ * see mxl reference manual
-+ */
-+void
-+i2c_init (int speed, int slaveaddr)
-+{
-+ int hclk_dividers[] = {
-+ 30, 32, 36, 42, 48, 52, 60, 72,
-+ 80, 88, 104, 128, 144, 160, 192, 240,
-+ 288, 320, 384, 480, 576, 640, 768, 960,
-+ 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840,
-+ 22, 24, 26, 26, 32, 36, 40, 44,
-+ 48, 56, 64, 72, 80, 96, 112, 128,
-+ 160, 192, 224, 256, 320, 384, 448, 512,
-+ 640, 768, 896, 1024, 1280, 1536, 1792, 2048
-+ };
-+ int refDiv = get_HCLK () / speed;
-+ int i, tmpIC;
-+
-+ imx_gpio_mode (PA15_PF_I2C_SDA);
-+ imx_gpio_mode (PA16_PF_I2C_SCL);
-+
-+ tmpIC = (sizeof (hclk_dividers) / sizeof (int)) - 1;
-+ for (i = tmpIC; i >= 0; i--)
-+ {
-+ if ((hclk_dividers[i] >= refDiv)
-+ && (hclk_dividers[i] < hclk_dividers[tmpIC]))
-+ {
-+ tmpIC = i;
-+ }
-+ }
-+
-+ IFDR = tmpIC;
-+ IADR = slaveaddr << 1;
-+
-+ if (I2SR & I2SR_IBB)
-+ imxi2c_send_stop ();
-+
-+ I2CR |= I2CR_IEN;
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * Probe to see if a chip is present. Also good for checking for the
-+ * completion of EEPROM writes since the chip stops responding until
-+ * the write completes (typically 10mSec).
-+ * probe sends a read command to probe a an address
-+ */
-+int
-+i2c_probe (uchar addr)
-+{
-+ int rc;
-+
-+ imxi2c_send_start ();
-+ rc = imxi2c_write_byte ((addr << 1) | 0);
-+ imxi2c_send_stop ();
-+
-+ return (rc ? 1 : 0);
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * Read bytes
-+ */
-+int
-+i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
-+{
-+ int shift;
-+ PRINTD ("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
-+ chip, addr, alen, buffer, len);
-+
-+#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
-+ /*
-+ * EEPROM chips that implement "address overflow" are ones
-+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
-+ * address and the extra bits end up in the "chip address"
-+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
-+ * four 256 byte chips.
-+ *
-+ * Note that we consider the length of the address field to
-+ * still be one byte because the extra address bits are
-+ * hidden in the chip address.
-+ */
-+ chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
-+
-+ PRINTD ("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
-+ chip, addr);
-+#endif
-+
-+ /*
-+ * Do the addressing portion of a write cycle to set the
-+ * chip's address pointer. If the address length is zero,
-+ * don't do the normal write cycle to set the address pointer,
-+ * there is no address pointer in this chip.
-+ */
-+ imxi2c_send_start ();
-+ if (alen > 0)
-+ {
-+ if (imxi2c_write_byte (chip << 1))
-+ { /* write cycle */
-+ imxi2c_send_stop ();
-+ PRINTD ("i2c_read, no chip responded %02X\n", chip);
-+ return (1);
-+ }
-+ shift = (alen - 1) * 8;
-+ while (alen-- > 0)
-+ {
-+ if (imxi2c_write_byte (addr >> shift))
-+ {
-+ PRINTD ("i2c_read, address not <ACK>ed\n");
-+ return (1);
-+ }
-+ shift -= 8;
-+ }
-+ imxi2c_send_stop (); /* reportedly some chips need a full stop */
-+ imxi2c_send_start ();
-+ }
-+ /*
-+ * Send the chip address again, this time for a read cycle.
-+ * Then read the data. On the last byte, we do a NACK instead
-+ * of an ACK(len == 0) to terminate the read.
-+ */
-+ imxi2c_write_byte ((chip << 1) | 1); /* read cycle */
-+ imxi2c_read_byte (len <= 2);
-+ while (len-- > 1)
-+ {
-+ *buffer++ = imxi2c_read_byte (len == 1);
-+ }
-+ imxi2c_send_stop ();
-+ *buffer++ = imxi2c_read_byte (0);
-+ return (0);
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * Write bytes
-+ */
-+int
-+i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
-+{
-+ int shift, failures = 0;
-+
-+ PRINTD ("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
-+ chip, addr, alen, buffer, len);
-+
-+ imxi2c_send_start ();
-+ if (imxi2c_write_byte (chip << 1))
-+ { /* write cycle */
-+ imxi2c_send_stop ();
-+ PRINTD ("i2c_write, no chip responded %02X\n", chip);
-+ return (1);
-+ }
-+ shift = (alen - 1) * 8;
-+ while (alen-- > 0)
-+ {
-+ if (imxi2c_write_byte (addr >> shift))
-+ {
-+ PRINTD ("i2c_write, address not <ACK>ed\n");
-+ return (1);
-+ }
-+ shift -= 8;
-+ }
-+
-+ while (len-- > 0)
-+ {
-+ if (imxi2c_write_byte (*buffer++))
-+ {
-+ failures++;
-+ }
-+ }
-+ imxi2c_send_stop ();
-+ return (failures);
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * Read a register
-+ */
-+uchar
-+i2c_reg_read (uchar i2c_addr, uchar reg)
-+{
-+ char buf;
-+
-+ i2c_read (i2c_addr, reg, 1, &buf, 1);
-+
-+ return (buf);
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * Write a register
-+ */
-+void
-+i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
-+{
-+ i2c_write (i2c_addr, reg, 1, &val, 1);
-+}
-+
-+#endif /* CONFIG_HARD_I2C */
-diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/lowlevel_init.S u-boot-1.1.6/board/apx9328/lowlevel_init.S
---- ref/u-boot-1.1.6/board/apx9328/lowlevel_init.S 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/board/apx9328/lowlevel_init.S 2006-12-03 12:06:16.000000000 +0100
-@@ -0,0 +1,443 @@
-+/*
-+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-+ * 02111-1307, USA.
-+ *
-+ */
-+
-+#include <config.h>
-+#include <version.h>
-+#include <asm/arch/imx-regs.h>
-+
-+.globl lowlevel_init
-+lowlevel_init:
-+
-+ mov r10, lr
-+
-+/* Change PERCLK1DIV to 14 ie 14+1 */
-+ ldr r0, =PCDR
-+ ldr r1, =CFG_PCDR_VAL
-+ str r1, [r0]
-+
-+/* set MCU PLL Control Register 0 */
-+
-+ ldr r0, =MPCTL0
-+ ldr r1, =CFG_MPCTL0_VAL
-+ str r1, [r0]
-+
-+/* set MCU PLL Control Register 1 */
-+
-+ ldr r0, =MPCTL1
-+ ldr r1, =CFG_MPCTL1_VAL
-+ str r1, [r0]
-+
-+/* set mpll restart bit */
-+ ldr r0, =CSCR
-+ ldr r1, [r0]
-+ orr r1,r1,#(1<<21)
-+ str r1, [r0]
-+
-+ mov r2,#0x10
-+1:
-+ mov r3,#0x2000
-+2:
-+ subs r3,r3,#1
-+ bne 2b
-+
-+ subs r2,r2,#1
-+ bne 1b
-+
-+/* set System PLL Control Register 0 */
-+
-+ ldr r0, =SPCTL0
-+ ldr r1, =CFG_SPCTL0_VAL
-+ str r1, [r0]
-+
-+/* set System PLL Control Register 1 */
-+
-+ ldr r0, =SPCTL1
-+ ldr r1, =CFG_SPCTL1_VAL
-+ str r1, [r0]
-+
-+/* set spll restart bit */
-+ ldr r0, =CSCR
-+ ldr r1, [r0]
-+ orr r1,r1,#(1<<22)
-+ str r1, [r0]
-+
-+ mov r2,#0x10
-+1:
-+ mov r3,#0x2000
-+2:
-+ subs r3,r3,#1
-+ bne 2b
-+
-+ subs r2,r2,#1
-+ bne 1b
-+
-+ ldr r0, =CSCR
-+ ldr r1, =CFG_CSCR_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GPCR
-+ ldr r1, =CFG_GPCR_VAL
-+ str r1, [r0]
-+
-+/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
-+ *this.....
-+ *
-+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
-+ * register 1, this stops it using the output of the PLL and thus runs at the
-+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
-+ * use the value set in the CM_OSC registers...regardless of what you set it
-+ * too! Thus, although i thought i was running at 140MHz, i'm actually running
-+ * at 40!..
-+
-+ * Slapping this into my bootloader does the trick...
-+
-+ * MRC p15,0,r0,c1,c0,0 ; read core configuration register
-+ * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
-+ * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
-+ * register
-+ */
-+ MRC p15,0,r0,c1,c0,0
-+ ORR r0,r0,#0xC0000000
-+ MCR p15,0,r0,c1,c0,0
-+
-+/* ldr r0, =GPR(0)
-+ ldr r1, =CFG_GPR_A_VAL
-+ str r1, [r0]
-+*/
-+
-+ ldr r0, =DR(0)
-+ ldr r1, =CFG_DR_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR1(0)
-+ ldr r1, =CFG_OCR1_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR2(0)
-+ ldr r1, =CFG_OCR2_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA1(0)
-+ ldr r1, =CFG_ICFA1_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA2(0)
-+ ldr r1, =CFG_ICFA2_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB1(0)
-+ ldr r1, =CFG_ICFB1_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB2(0)
-+ ldr r1, =CFG_ICFB2_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR1(0)
-+ ldr r1, =CFG_ICR1_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR2(0)
-+ ldr r1, =CFG_ICR2_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =IMR(0)
-+ ldr r1, =CFG_IMR_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DDIR(0)
-+ ldr r1, =CFG_DDIR_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GPR(0)
-+ ldr r1, =CFG_GPR_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =PUEN(0)
-+ ldr r1, =CFG_PUEN_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GIUS(0)
-+ ldr r1, =CFG_GIUS_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DR(1)
-+ ldr r1, =CFG_DR_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR1(1)
-+ ldr r1, =CFG_OCR1_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR2(1)
-+ ldr r1, =CFG_OCR2_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA1(1)
-+ ldr r1, =CFG_ICFA1_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA2(1)
-+ ldr r1, =CFG_ICFA2_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB1(1)
-+ ldr r1, =CFG_ICFB1_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB2(1)
-+ ldr r1, =CFG_ICFB2_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR1(1)
-+ ldr r1, =CFG_ICR1_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR2(1)
-+ ldr r1, =CFG_ICR2_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =IMR(1)
-+ ldr r1, =CFG_IMR_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DDIR(1)
-+ ldr r1, =CFG_DDIR_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GPR(1)
-+ ldr r1, =CFG_GPR_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =PUEN(1)
-+ ldr r1, =CFG_PUEN_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GIUS(1)
-+ ldr r1, =CFG_GIUS_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DR(2)
-+ ldr r1, =CFG_DR_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR1(2)
-+ ldr r1, =CFG_OCR1_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR2(2)
-+ ldr r1, =CFG_OCR2_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA1(2)
-+ ldr r1, =CFG_ICFA1_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA2(2)
-+ ldr r1, =CFG_ICFA2_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB1(2)
-+ ldr r1, =CFG_ICFB1_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB2(2)
-+ ldr r1, =CFG_ICFB2_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR1(2)
-+ ldr r1, =CFG_ICR1_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR2(2)
-+ ldr r1, =CFG_ICR2_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =IMR(2)
-+ ldr r1, =CFG_IMR_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DDIR(2)
-+ ldr r1, =CFG_DDIR_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GPR(2)
-+ ldr r1, =CFG_GPR_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =PUEN(2)
-+ ldr r1, =CFG_PUEN_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GIUS(2)
-+ ldr r1, =CFG_GIUS_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DR(3)
-+ ldr r1, =CFG_DR_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR1(3)
-+ ldr r1, =CFG_OCR1_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR2(3)
-+ ldr r1, =CFG_OCR2_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA1(3)
-+ ldr r1, =CFG_ICFA1_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA2(3)
-+ ldr r1, =CFG_ICFA2_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB1(3)
-+ ldr r1, =CFG_ICFB1_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB2(3)
-+ ldr r1, =CFG_ICFB2_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR1(3)
-+ ldr r1, =CFG_ICR1_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR2(3)
-+ ldr r1, =CFG_ICR2_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =IMR(3)
-+ ldr r1, =CFG_IMR_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DDIR(3)
-+ ldr r1, =CFG_DDIR_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GPR(3)
-+ ldr r1, =CFG_GPR_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =PUEN(3)
-+ ldr r1, =CFG_PUEN_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GIUS(3)
-+ ldr r1, =CFG_GIUS_D_VAL
-+ str r1, [r0]
-+
-+/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
-+
-+ ldr r0, =FMCR
-+ ldr r1, =CFG_FMCR_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS0U
-+ ldr r1, =CFG_CS0U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS0L
-+ ldr r1, =CFG_CS0L_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS1U
-+ ldr r1, =CFG_CS1U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS1L
-+ ldr r1, =CFG_CS1L_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS2U
-+ ldr r1, =CFG_CS2U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS2L
-+ ldr r1, =CFG_CS2L_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS3U
-+ ldr r1, =CFG_CS3U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS3L
-+ ldr r1, =CFG_CS3L_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS4U
-+ ldr r1, =CFG_CS4U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS4L
-+ ldr r1, =CFG_CS4L_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS5U
-+ ldr r1, =CFG_CS5U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS5L
-+ ldr r1, =CFG_CS5L_VAL
-+ str r1, [r0]
-+
-+ adr r0, sdramsetup /* r0 <- current position of code */
-+ ldr r1, =CFG_SDRAM_1_BASE /* test if we run from flash or RAM */
-+ cmp r1, r0 /* don't reloc during debug*/
-+ bhi sdramsetup
-+ ldr r1, =CFG_FLASH_BASE /* test if we run from flash or RAM */
-+ cmp r0, r1 /* don't reloc during debug */
-+ bmi endofmemsetup
-+
-+/* SDRAM Setup */
-+sdramsetup:
-+ ldr r0, =SDCTL0
-+ ldr r1, =CFG_PRECHARGE_CMD
-+ str r1, [r0]
-+
-+ ldr r1, =CFG_SDRAM_1_BASE+CFG_SDRAM_PRECHARGE_ALL_VAL
-+ ldr r2, [r1]
-+
-+ ldr r1, =CFG_AUTOREFRESH_CMD
-+ str r1, [r0]
-+
-+ ldr r1, =CFG_SDRAM_1_BASE
-+ ldr r2, [r1] /* Issue AutoRefresh Command */
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+
-+ ldr r1, =CFG_SET_MODE_REG_CMD
-+ str r1, [r0]
-+
-+ ldr r1, =CFG_SDRAM_1_BASE+CFG_SDRAM_MODE_REGISTER_VAL
-+ str r2, [r1]
-+
-+ ldr r1, =CFG_NORMAL_RW_CMD
-+ str r1, [r0]
-+
-+endofmemsetup:
-+ mov pc,r10
-diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/Makefile u-boot-1.1.6/board/apx9328/Makefile
---- ref/u-boot-1.1.6/board/apx9328/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/board/apx9328/Makefile 2006-11-26 20:28:03.000000000 +0100
-@@ -0,0 +1,47 @@
-+#
-+# (C) Copyright 2000-2004
-+# Wolfgang Denk, DENX Software Engineering, wd...@de....
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+include $(TOPDIR)/config.mk
-+
-+LIB = lib$(BOARD).a
-+
-+OBJS := apx9328.o i2c.o apx9328fpga.o fpga.o
-+SOBJS := lowlevel_init.o
-+
-+$(LIB): $(OBJS) $(SOBJS)
-+ $(AR) crv $@ $^
-+
-+clean:
-+ rm -f $(SOBJS) $(OBJS)
-+
-+distclean: clean
-+ rm -f $(LIB) core *.bak .depend
-+
-+#########################################################################
-+
-+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
-+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-+
-+-include .depend
-+
-+#########################################################################
-diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/u-boot.lds u-boot-1.1.6/board/apx9328/u-boot.lds
---- ref/u-boot-1.1.6/board/apx9328/u-boot.lds 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/board/apx9328/u-boot.lds 2006-11-26 20:28:03.000000000 +0100
-@@ -0,0 +1,56 @@
-+/*
-+ * (C) Copyright 2000-2004
-+ * Wolfgang Denk, DENX Software Engineering, wd...@de....
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+
-+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-+OUTPUT_ARCH(arm)
-+ENTRY(_start)
-+SECTIONS
-+{
-+ . = 0x00000000;
-+
-+ . = ALIGN(4);
-+ .text :
-+ {
-+ cpu/arm920t/start.o (.text)
-+ *(.text)
-+ }
-+
-+ . = ALIGN(4);
-+ .rodata : { *(.rodata) }
-+
-+ . = ALIGN(4);
-+ .data : { *(.data) }
-+
-+ . = ALIGN(4);
-+ .got : { *(.got) }
-+
-+ __u_boot_cmd_start = .;
-+ .u_boot_cmd : { *(.u_boot_cmd) }
-+ __u_boot_cmd_end = .;
-+
-+ . = ALIGN(4);
-+ __bss_start = .;
-+ .bss : { *(.bss) }
-+ _end = .;
-+}
-diff -purN -x '*~' ref/u-boot-1.1.6/include/configs/apx9328.h u-boot-1.1.6/include/configs/apx9328.h
---- ref/u-boot-1.1.6/include/configs/apx9328.h 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-1.1.6/include/configs/apx9328.h 2006-12-03 12:08:06.000000000 +0100
-@@ -0,0 +1,954 @@
-+/*
-+ * Eric Jarrige <jo...@us...>
-+ *
-+ * Configuation settings for the Armadeus Project motherboard 9328 board.
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ * 2005/01/14 Initial version taken from the scb9328 configuration file
-+ * 2005/03/10 apx9328 configuration file and trial to improve of
-+ * hardware register control.
-+ * 2005/08/16 added APX9328 fpgas and ethernet
-+ * 2005/12/02 added filesystem boot over NFS
-+ * 2006/11/26 added filesystem boot over NFS
-+ */
-+
-+#ifndef __CONFIG_H
-+#define __CONFIG_H
-+
-+#define CONFIG_IDENT_STRING " apx9328 patch 2.7"
-+
-+#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
-+#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
-+#define CONFIG_APX9328 1 /* on a Armadeus project board */
-+#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
-+
-+/*
-+ * Enable the call to misc_init_r() for miscellaneous platform
-+ * dependent initialization.
-+ */
-+
-+#define CONFIG_MISC_INIT_R
-+
-+/*
-+ * Select serial console configuration
-+ */
-+#define CONFIG_IMX_SERIAL1
-+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-+#define CONFIG_BAUDRATE 115200
-+
-+/*
-+ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
-+ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
-+ * functionality or size of u-boot code.
-+ */
-+#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
-+ | CFG_CMD_NET \
-+ | CFG_CMD_PING \
-+ | CFG_CMD_DHCP \
-+ | CFG_CMD_JFFS2 \
-+ | CFG_CMD_I2C \
-+ | CFG_CMD_DATE \
-+ | CFG_CMD_EEPROM \
-+ | CONFIG_CMD_ALL \
-+ )
-+
-+#include <cmd_confdefs.h>
-+
-+/*
-+ * Select some advanced features of the commande line parser
-+ */
-+#define CONFIG_AUTO_COMPLETE 1 /* Enable auto completion of */
-+ /* commands using TAB */
-+#define CFG_HUSH_PARSER 1 /* enable the "hush" shell */
-+#define CFG_PROMPT_HUSH_PS2 "> " /* secondary prompt string */
-+
-+/* eval_board=evk9328
-+ * Boot options. Setting delay to -1 stops autostart count down.
-+ */
-+#define CONFIG_BOOTDELAY 20
-+
-+#define CONFIG_BOOTARGS \
-+ CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=jffs2 "CONFIG_MTDPARTS
-+
-+#define CONFIG_CONSOLE "console=ttySMX0,"MK_STR(CONFIG_BAUDRATE)"n8"
-+#define CONFIG_MTDMAP "apf9328_flash"
-+#define CONFIG_MTDPARTS "mtdparts=" CONFIG_MTDMAP ":256k(U-boot)ro," \
-+ "128k(U-boot_env),256k(firmware),1536k(kernel),6016k(root)"
-+
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+ "fileaddr=" MK_STR(CFG_LOAD_ADDR) "\0" \
-+ "filesize=" MK_STR(CFG_MONITOR_LEN) "\0" \
-+ "console=" CONFIG_CONSOLE "\0" \
-+ "mtdparts=" CONFIG_MTDPARTS "\0" \
-+ "uboot_addr=" MK_STR(CFG_MONITOR_BASE) "\0" \
-+ "uboot_len=" MK_STR(CFG_MONITOR_LEN) "\0" \
-+ "env_addr=" MK_STR(CFG_ENV_ADDR) "\0" \
-+ "env_len=" MK_STR(CFG_ENV_SIZE) "\0" \
-+ "firmware_addr=" MK_STR(CONFIG_FIRMWARE_ADDR) "\0" \
-+ "firmware_len=" MK_STR(CONFIG_FIRMWARE_LEN) "\0" \
-+ "kernel_addr=" MK_STR(CONFIG_KERNEL_ADDR) "\0" \
-+ "kernel_len=" MK_STR(CONFIG_KERNEL_LEN) "\0" \
-+ "rootfs_addr=" MK_STR(CONFIG_ROOTFS_ADDR) "\0" \
-+ "rootfs_len=" MK_STR(CONFIG_ROOTFS_LEN) "\0" \
-+ "mmcroot=/dev/mmcblk0p1\0" \
-+ "mmcrootfstype=ext2\0" \
-+ "addnfsargs=setenv bootargs ${bootargs} " \
-+ "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
-+ "addjffsargs=setenv bootargs ${bootargs} " \
-+ "root=/dev/mtdblock4 rootfstype=jffs2\0" \
-+ "addmmcargs=setenv bootargs ${bootargs} " \
-+ "root=${mmcroot} rootfstype=${mmcrootfstype}\0" \
-+ "addipargs=setenv bootargs ${bootargs} " \
-+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off \0"\
-+ "nfsboot=setenv bootargs ${console} ${mtdparts};" \
-+ "run addnfsargs addipargs; bootm ${kernel_addr}\0" \
-+ "jffsboot=setenv bootargs ${console} ${mtdparts};" \
-+ "run addjffsargs addipargs; bootm ${kernel_addr}\0" \
-+ "mmcboot=setenv bootargs ${console} ${mtdparts};" \
-+ "run addmmcargs addipargs; bootm ${kernel_addr}\0" \
-+ "firmware_autoload=0\0" \
-+ "flash_uboot=protect off ${uboot_addr} +${uboot_len};" \
-+ "era ${uboot_addr} +${uboot_len};" \
-+ "if cp.b ${fileaddr} ${uboot_addr} ${filesize};" \
-+ "then protect on ${uboot_addr} +${uboot_len};" \
-+ "echo Flashing uboot succeed;" \
-+ "else echo Flashing uboot failed;" \
-+ "fi; \0" \
-+ "flash_firmware=era ${firmware_addr} +${firmware_len};" \
-+ "if cp.b ${fileaddr} ${firmware_addr} ${filesize} ;" \
-+ "then echo Flashing Firmware succeed;" \
-+ "else echo Flashing Firmware failed;" \
-+ "fi\0" \
-+ "flash_kernel=era ${kernel_addr} +${kernel_len};" \
-+ "if cp.b ${fileaddr} ${kernel_addr} ${filesize} ;" \
-+ "then echo Flashing kernel succeed;" \
-+ "else echo Flashing kernel failed;" \
-+ "fi\0" \
-+ "flash_rootfs=era ${rootfs_addr} +${rootfs_len};" \
-+ "if cp.b ${fileaddr} ${rootfs_addr} ${filesize};" \
-+ "then echo Flashing rootfs succeed;" \
-+ "else echo Flashing rootfs failed;" \
-+ "fi\0" \
-+ "flash_reset_env=protect off ${env_addr} +${env_len};" \
-+ "era ${env_addr} +${env_len};" \
-+ "echo Erasinf flash environment variables done!" \
-+
-+#define CONFIG_BOOTCOMMAND "run jffsboot"
-+#define CFG_AUTOLOAD "no"
-+
-+#define MACH_TYPE_APX9328 MACH_TYPE_SCB9328
-+
-+#define CONFIG_MACH_TYPE MACH_TYPE_APF9328
-+#define CONFIG_BOOT_PARAMS_ADDR 0x08000100
-+
-+/*
-+ * #define CONFIG_SHOW_BOOT_PROGRESS
-+ */
-+
-+#define CONFIG_ETHADDR 00:1E:AC:00:00:01
-+#define CONFIG_NETMASK 255.255.255.0
-+#define CONFIG_IPADDR 192.168.000.10
-+#define CONFIG_HOSTNAME "armadeus"
-+#define CONFIG_GATEWAYIP 192.168.000.1
-+#define CONFIG_SERVERIP 192.168.000.1
-+#define CONFIG_ROOTPATH "/tftpboot/root"
-+
-+/*
-+ * General options for u-boot. Modify to save memory foot print
-+ */
-+
-+#define CFG_LONGHELP
-+#define CFG_PROMPT "BIOS> " /* prompt string */
-+#define CFG_CBSIZE 256 /* console I/O buffer */
-+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */
-+#define CFG_MAXARGS 16 /* max command args */
-+#define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */
-+
-+#define CFG_MEMTEST_START 0x08000000 /* memtest test area */
-+#define CFG_MEMTEST_END 0x08700000
-+
-+#undef CFG_CLKS_IN_HZ /* use HZ for freq. display */
-+#define CFG_HZ 1000000 /* incrementer freq: 1 MHz */
-+
-+/*
-+ * Definitions related to passing arguments to kernel.
-+ */
-+
-+#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
-+#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
-+#define CONFIG_INITRD_TAG 1 /* send initrd params */
-+#undef CONFIG_VFD /* do not send framebuffer setup */
-+
-+/*
-+ * Malloc pool need to host env + 128 Kb reserve for other allocations.
-+ */
-+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) )
-+
-+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-+
-+#define CONFIG_STACKSIZE (120<<10) /* stack size */
-+
-+#ifdef CONFIG_USE_IRQ
-+#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
-+#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
-+#endif
-+
-+/*
-+* Clocks configuration
-+*/
-+/*
-+ * PLL configuration
-+
-+ f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
-+ f_ref=16,777216MHz
-+ 32768 Hz xtal
-+ 0x07B32DA5: 192.0000173
-+ 0x002a141f: 191,9944MHz
-+ 0x040b2007: 144MHz
-+ 0x0FB32DA5: 96.00000864 MHz
-+ 0x042a141f: 96MHz
-+ 0x0811140d: 64MHz
-+ 0x040e200e: 150MHz
-+ 0x00321431: 200MHz
-+
-+ 16 MHz xtal
-+ 0x08001800: 64MHz mit 16er Quarz
-+ 0x04001800: 96MHz mit 16er Quarz
-+ 0x04002400: 144MHz mit 16er Quarz
-+
-+ 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
-+ |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|
-+ */
-+
-+#define CFG_OSC32 32768 /* 32768 or 32000 Hz crystal */
-+#undef CFG_OSC16 /* there is no external 16MHz external clock */
-+
-+/* MPU CLOCK source before PLL (should be named CFG_SYS_CLK_FREQ) */
-+#define CONFIG_SYS_CLK_FREQ (512*CFG_OSC32)
-+#define CFG_MPCTL0_VAL 0x07B32DA5 /* 192.000017 MHz */
-+#define CFG_MPCTL1_VAL 0
-+
-+/* system clock source before PLL (should be named CFG_SYSPLL_CLK_FREQ) */
-+#ifndef CFG_OSC16
-+#define CONFIG_SYSPLL_CLK_FREQ (512*CFG_OSC32)
-+#if (CFG_OSC32 == 32000)
-+#define CFG_SPCTL0_VAL 0x043F1437 /* 96 MHz */
-+#define CFG_SPCTL1_VAL 0
-+#define CONFIG_SYS_FREQ 96 /* MHz */
-+#else /* CFG_OSC32 == 32768*/
-+#define CFG_SPCTL0_VAL 0x0FB32DA5 /* 96.000009 MHz */
-+#define CFG_SPCTL1_VAL 0
-+#define CONFIG_SYS_FREQ 96 /* MHz */
-+#endif /* CFG_OSC32 */
-+#else /* CFG_OSC16 in use*/
-+#define CONFIG_SYSPLL_CLK_FREQ CFG_OSC16
-+#define CFG_SPCTL0_VAL 0x04001401 /* 96 MHz */
-+#define CFG_SPCTL1_VAL 0x0C000040
-+#define CONFIG_SYS_FREQ 96 /* MHz */
-+#endif /* CFG_OSC16 */
-+
-+/* external bus frequency (have to be a CONFIG_SYS_FREQ ratio) */
-+#define CONFIG_SYS_BUS_FREQ 96 /* 96|48... MHz (BCLOCK and HCLOCK) */
-+#define CONFIG_USB_FREQ 48 /* 48 MHz */
-+#define CONFIG_PERIF1_FREQ 16 /* 16 MHz UART, Timer PWM*/
-+#define CONFIG_PERIF2_FREQ 48 /* 48 MHz LCD SD SPI*/
-+#define CONFIG_PERIF3_FREQ 16 /* 16 MHz SSI*/
-+
-+
-+/*
-+ * SDRAM definition parameter
-+ */
-+#define CONFIG_NR_DRAM_BANKS 1 /* we have and support only 1 bank of SDRAM */
-+
-+#define CFG_SDRAM_MBYTE_SYZE 16
-+
-+#if (CFG_SDRAM_MBYTE_SYZE == 8)
-+/* micron 8MB */
-+#define CFG_SDRAM_1_BASE 0x08000000 /* SDRAM bank #1 32bits */
-+#define CFG_SDRAM_1_SIZE 0x00800000 /* 8 MB */
-+#define CFG_SDRAM_NUM_COL 8 /* 8, 9, 10 or 11 column address bits */
-+#define CFG_SDRAM_NUM_ROW 11 /* 11, 12 or 13 row address bits */
-+#define CFG_SDRAM_REFRESH 2 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
-+#define CFG_SDRAM_CLOCK_CYCLE_CL_1 20 /* ns clock cycle time when CL=1 */
-+#define CFG_SDRAM_ROW_PRECHARGE_DELAY 20 /* ns SRP */
-+#define CFG_SDRAM_ROW_2_COL_DELAY 20 /* ns SRCD */
-+#define CFG_SDRAM_ROW_CYCLE_DELAY 70 /* ns SRC */
-+#define CFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-+#define CFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
-+#endif
-+
-+#if (CFG_SDRAM_MBYTE_SYZE == 16)
-+/* micron 16MB */
-+#define CFG_SDRAM_1_BASE 0x08000000 /* SDRAM bank #1 32bits */
-+#define CFG_SDRAM_1_SIZE 0x01000000 /* 16 MB */
-+#define CFG_SDRAM_NUM_COL 8 /* 8, 9, 10 or 11 column address bits */
-+#define CFG_SDRAM_NUM_ROW 12 /* 11, 12 or 13 row address bits */
-+#define CFG_SDRAM_REFRESH 2 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
-+#define CFG_SDRAM_CLOCK_CYCLE_CL_1 20 /* ns clock cycle time when CL=1 */
-+#define CFG_SDRAM_ROW_PRECHARGE_DELAY 20 /* ns SRP */
-+#define CFG_SDRAM_ROW_2_COL_DELAY 20 /* ns SRCD */
-+#define CFG_SDRAM_ROW_CYCLE_DELAY 70 /* ns SRC */
-+#define CFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-+#define CFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
-+#endif
-+
-+#if (CFG_SDRAM_MBYTE_SYZE == 32)
-+/* micron 32MB */
-+#define CFG_SDRAM_1_BASE 0x08000000 /* SDRAM bank #1 32bits */
-+#define CFG_SDRAM_1_SIZE 0x02000000 /* 32 MB */
-+#define CFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
-+#define CFG_SDRAM_NUM_ROW 12 /* 11, 12 or 13 row address bits */
-+#define CFG_SDRAM_REFRESH 2 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
-+#define CFG_SDRAM_CLOCK_CYCLE_CL_1 20 /* ns clock cycle time when CL=1 */
-+#define CFG_SDRAM_ROW_PRECHARGE_DELAY 20 /* ns SRP */
-+#define CFG_SDRAM_ROW_2_COL_DELAY 20 /* ns SRCD */
-+#define CFG_SDRAM_ROW_CYCLE_DELAY 70 /* ns SRC */
-+#define CFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-+#define CFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
-+#endif
-+
-+#if (CFG_SDRAM_MBYTE_SYZE == 64)
-+/* micron 64MB */
-+#define CFG_SDRAM_1_BASE 0x08000000 /* SDRAM bank #1 32bits */
-+#define CFG_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-+#define CFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 column address bits */
-+#define CFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13 row address bits */
-+#define CFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 2=4096 3=8192 refresh */
-+#define CFG_SDRAM_CLOCK_CYCLE_CL_1 20 /* ns clock cycle time when CL=1 */
-+#define CFG_SDRAM_ROW_PRECHARGE_DELAY 20 /* ns SRP */
-+#define CFG_SDRAM_ROW_2_COL_DELAY 20 /* ns SRCD */
-+#define CFG_SDRAM_ROW_CYCLE_DELAY 70 /* ns SRC */
-+#define CFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */
-+#define CFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access; 0 = Burst mode */
-+#endif
-+
-+/*
-+ * Configuration for a maximum 32MB of FLASH memory
-+ */
-+#define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count) */
-+#define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
-+#define CFG_FLASH_BASE 0x10000000 /* location of flash memory */
-+
-+/* This should be defined if CFI FLASH device is present. */
-+#define CFG_FLASH_CFI 1
-+#define CFG_FLASH_CFI_DRIVER 1
-+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-+#define CFG_FLASH_PROTECTION 1
-+
-+/*
-+ * This is setting for JFFS2 support in u-boot.
-+ * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
-+ */
-+#define CFG_JFFS2_FIRST_BANK 0
-+#define CFG_JFFS2_FIRST_SECTOR 5
-+#define CFG_JFFS2_NUM_BANKS 1
-+/*
-+ * Environment setup. Definitions of monitor location and size with
-+ * definition of environment setup ends up in 2 possibilities.
-+ * 1. Embeded environment - in u-boot code is space for environment
-+ * 2. Environment is read from predefined sector of flash
-+ * Right now we support 2. possiblity, but expecting no env placed
-+ * on mentioned address right now. This also needs to provide whole
-+ * sector for it - for us 256Kb is really waste of memory. U-boot uses
-+ * default env. and until kernel parameters could be sent to kernel
-+ * env. has no sense to us.
-+ */
-+
-+#define CFG_MONITOR_BASE 0x10000000
-+#define CFG_MONITOR_LEN 0x00040000 /* 256kB ( 2 flash sector ) */
-+#define CFG_ENV_IS_IN_FLASH 1
-+#define CFG_ENV_ADDR 0x10040000 /* absolute address for now */
-+#define CFG_ENV_SIZE 0x00020000
-+#define CFG_ENV_SECT_SIZE 0x00020000
-+#define CONFIG_ENV_OVERWRITE 1 /* env is writable now */
-+#define CONFIG_FIRMWARE_ADDR 0x10060000
-+#define CONFIG_FIRMWARE_LEN 0x00040000 /* 256kB ( 2 flash sector ) */
-+#define CONFIG_KERNEL_ADDR 0x100A0000
-+#define CONFIG_KERNEL_LEN 0x00180000 /* 1.5MB */
-+#define CONFIG_ROOTFS_ADDR 0x10220000
-+#define CONFIG_ROOTFS_LEN 0x005E0000 /* almost 6MB */
-+
-+/*
-+ * Default load address for user programs and kernel
-+ */
-+#define CFG_LOAD_ADDR 0x08000000
-+#define CONFIG_LOADADDR 0x08000000
-+#define CFG_TFTP_LOADADDR 0x08000000
-+/*
-+ * Hardware drivers
-+ */
-+
-+/* DM9000 ethernet chipset assigned to CS4 */
-+/* For the apf board DM9000 base is 0x15C00000 and data is base+2 */
-+/* For the apm board DM9000 base is 0x15C3FFFC and data is base+4 */
-+#define CONFIG_DRIVER_DM9000 1
-+#undef CONFIG_DM9000_DEBUG
-+#define CONFIG_DM9000_BASE 0x15C00000
-+#define DM9000_IO CONFIG_DM9000_BASE
-+#define DM9000_DATA (CONFIG_DM9000_BASE+2)
-+#define CONFIG_DM9000_USE_16BIT
-+
-+/*-----------------------------------------------------------------------
-+ * FPGA stuff
-+ */
-+#define CONFIG_FPGA_COUNT 1
-+/* only digital value for CONFIG_FPGA is supported (investigation pending) */
-+#define CONFIG_FPGA 0x801 /* CFG_XILINX_SPARTAN3 */
-+#define CFG_FPGA_WAIT 250
-+#define CFG_FPGA_PROG_FEEDBACK
-+#define CFG_FPGA_CHECK_CTRLC
-+#define CFG_FPGA_CHECK_ERROR
-+/* FPGA program pin configuration */
-+#define CFG_FPGA_PRG (GPIO_PORTB | 18) /* FPGA prog pin (SSI output) */
-+#define CFG_FPGA_CLK (GPIO_PORTB | 19) /* FPGA clk pin (SSI output) */
-+#define CFG_FPGA_DATA (GPIO_PORTB | 17) /* FPGA data pin (SSI output) */
-+#define CFG_FPGA_INIT (GPIO_PORTB | 15) /* FPGA init pin (SSI input) */
-+#define CFG_FPGA_DONE (GPIO_PORTB | 16) /* FPGA done pin (SSI input) */
-+
-+/*
-+ * I2C bus
-+ */
-+
-+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-+
-+#define CFG_I2C_SPEED 400000 /* 400 kHz */
-+#define CFG_I2C_SLAVE 0x7F
-+
-+# define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC256 */
-+# define CFG_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
-+/* mask of address bits that overflow into the "EEPROM chip address" */
-+/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x00*/
-+#define CFG_EEPROM_PAGE_WRITE_BITS 6
-+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
-+
-+#define CONFIG_RTC_DS1374
-+
-+/*
-+ * External interfaces module
-+ *
-+ * CSxU_VAL:
-+ * 63| x |x|x x|x x x x|x x| x | x |x x x x|48
-+ * |DTACK_SEL|0|BCD| BCS |PSZ|PME|SYNC| DOL |
-+ *
-+ * 47| x x | x x x x x x | x | x x x x | x x x x |32
-+ * | CNC | WSC | 0 | WWS | EDC |
-+ *
-+ * CSxL_VAL:
-+ * 31| x x x x | x x x x | x x x x | x x x x |24
-+ * | OEA | OEN | WEA | WEN |
-+ * 23|x x x x| x | x x x | x x x x |x x| x | x | 0
-+ * | CSA |EBC| DSZ | 0|SP|0|WP|0 0|PA |CSEN |
-+ */
-+
-+/* CS0 configuration for flash memory Micron MT28F128J3-150 */
-+#define CFG_CS0_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 peripherals */
-+#define CFG_CS0_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] pins */
-+ /* 3=8bits on D[7:0] 6=32 bits..*/
-+#define CFG_CS0_SUPERVISOR_PROTECT 0 /* 1 : user mode access prohibited */
-+#define CFG_CS0_WRITE_PROTECT 0 /* 1 : write access prohibited */
-+#define CFG_CS0_EB_SIGNAL_CONTROL_WRITE 1 /* 1 when EB is used as write signal */
-+#define CFG_CS0_READ_CYC_LGTH 150 /* ns */
-+#define CFG_CS0_OE_ASSERT_DLY 0 /* ns */
-+#define CFG_CS0_OE_NEG_DLY 0 /* ns */
-+
-+#define CFG_CS0_CS_NEG_LGTH 0 /* ns CS HIGH to CS LOW : tCWH */
-+#define CFG_CS0_XTRA_DEAD_CYC 35 /* ns from CS HIGH to tristate bus */
-+
-+#define CFG_CS0_WRITE_XTRA_LGTH 0 /* ns */
-+#define CFG_CS0_EB_ASSERT_DLY 0 /* ns */
-+#define CFG_CS0_EB_NEG_DLY 0 /* ns */
-+#define CFG_CS0_CS_ASSERT_NEG_DLY 0 /* ns */
-+
-+#define CFG_CS0_SYNC_ENABLE 1 /* enable synchronous burst mode */
-+#define CFG_CS0_SYNC_PAGE_MODE_EMUL 1 /* enable page mode emulation */
-+#define CFG_CS0_SYNC_PAGE_SIZE 0 /* 4 words page size (8bytes) */
-+#define CFG_CS0_SYNC_BURST_CLK_START 0 /* 0 ns burst clock delay */
-+#define CFG_CS0_SYNC_BURST_CLK_DIV 0 /* 0 : divider is 1 */
-+#define CFG_CS0_SYNC_DAT_OUT_LGTH 25 /* ns */
-+
-+/* CS1 configuration for */
-+#define CFG_CS1_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 peripherals */
-+#define CFG_CS1_PIN_ASSERT 0 /* chip select pin state when */
-+ /* chip select disabled */
-+#define CFG_CS1_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] pins*/
-+ /* 3=8bits on D[7:0] 6=32 bits..*/
-+#define CFG_CS1_SUPERVISOR_PROTECT 0 /* 1 : user mode access prohibited */
-+#define CFG_CS1_WRITE_PROTECT 0 /* 1 : write access prohibited */
-+#define CFG_CS1_EB_SIGNAL_CONTROL_WRITE 1 /* 1 when EB is used as write signal */
-+
-+#define CFG_CS1_READ_CYC_LGTH 30 /* ns */
-+#define CFG_CS1_OE_ASSERT_DLY 0 /* ns */
-+#define CFG_CS1_OE_NEG_DLY 0 /* ns */
-+
-+#define CFG_CS1_CS_NEG_LGTH 0 /* max 30 ns CS HIGH to CS LOW at 100MHz */
-+#define CFG_CS1_XTRA_DEAD_CYC 0 /* ns from CS HIGH to tristate bus */
-+
-+#define CFG_CS1_WRITE_XTRA_LGTH 0 /* ns */
-+#define CFG_CS1_EB_ASSERT_DLY 0 /* ns */
-+#define CFG_CS1_EB_NEG_DLY 0 /* ns */
-+#define CFG_CS1_CS_ASSERT_NEG_DLY 0 /* ns */
-+
-+#define CFG_CS1_SYNC_ENABLE 0 /* enable synchronous burst mode */
-+#define CFG_CS1_SYNC_PAGE_MODE_EMUL 0 /* enable page mode emulation */
-+#define CFG_CS1_SYNC_PAGE_SIZE 0 /* 4 words page size (8bytes) */
-+#define CFG_CS1_SYNC_BURST_CLK_START 0 /* 0 ns burst clock delay */
-+#define CFG_CS1_SYNC_BURST_CLK_DIV 0 /* 0 : divider is 1 */
-+#define CFG_CS1_SYNC_DAT_OUT_LGTH 0 /* ns */
-+
-+/* CS2 configuration for */
-+#define CFG_CS2_CHIP_SELECT_ENABLE 0 /* 1 : enable CS0 peripherals */
-+#define CFG_CS2_PIN_ASSERT 0 /* chip select pin state when */
-+ /*chip select disabled */
-+#define CFG_CS2_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] pins */
-+ /* 3=8bits on D[7:0] 6=32 bits..*/
-+#define CFG_CS2_SUPERVISOR_PROTECT 0 /* 1 : user mode access prohibited */
-+#define CFG_CS2_WRITE_PROTECT 0 /* 1 : write access prohibited */
-+#define CFG_CS2_EB_SIGNAL_CONTROL_WRITE 1 /* 1 when EB is used as write signal */
-+
-+#define CFG_CS2_READ_CYC_LGTH 0 /* ns */
-+#define CFG_CS2_OE_ASSERT_DLY 0 /* ns */
-+#define CFG_CS2_OE_NEG_DLY 0 /* ns */
-+
-+#define CFG_CS2_CS_NEG_LGTH 0 /* max 30 ns CS HIGH to CS LOW at 100MHz */
-+#define CFG_CS2_XTRA_DEAD_CYC 0 /* ns from CS HIGH to tristate bus */
-+
-+#define CFG_CS2_WRITE_XTRA_LGTH 0 /* ns */
-+#define CFG_CS2_EB_ASSERT_DLY 0 /* ns */
-+#define CFG_CS2_EB_NEG_DLY 0 /* ns */
-+#define CFG_CS2_CS_ASSERT_NEG_DLY 0 /* ns */
-+
-+#define CFG_CS2_SYNC_ENABLE 0 /* enable synchronous burst mode */
-+#define CFG_CS2_SYNC_PAGE_MODE_EMUL 0 /* enable page mode emulation*/
-+#define CFG_CS2_SYNC_PAGE_SIZE 0 /* 4 words page size (8bytes) */
-+#define CFG_CS2_SYNC_BURST_CLK_START 0 /* 0 ns burst clock delay */
-+#define CFG_CS2_SYNC_BURST_CLK_DIV 0 /* 0 : divider is 1 */
-+#define CFG_CS2_SYNC_DAT_OUT_LGTH 0 /* ns */
-+
-+/* CS3 configuration for */
-+#define CFG_CS3_CHIP_SELECT_ENABLE 1 /* 1 : enable CS0 peripherals */
-+#define CFG_CS3_PIN_ASSERT 0 /* chip select pin state when */
-+ /* chip select disabled */
-+#define CFG_CS3_DATA_PORT_SIZE 0x5 /* 5=16 bits on D[15:0] pins */
-+ /* 3=8bits on D[7:0] 6=32 bits..*/
-+#define CFG_CS3_SUPERVISOR_PROTECT 0 /* 1: user mode access prohibited*/
-+#define CFG_CS3_WRITE_PROTECT 0 /* 1: write access prohibited */
-+#define CFG_CS3_EB_SIGNAL_CONTROL_WRITE 1 /* 1 when EB is used as write signal*/
-+
-+#define CFG_CS3_READ_CYC_LGTH 0 /* ns */
-+#define CFG_CS3_OE_ASSERT_DLY 0 /* ns */
-+#define CFG_CS3_OE_NEG_DLY 0 /* ns */
-+
-+#define CFG_CS3_CS_NEG_LGTH 0 /* max 30 ns CS HIGH to CS LOW at 100MHz */
-+#define CFG_CS3_XTRA_DEAD_CYC 0 /* ns from CS HIGH to tristate bus */
-+
-+#define CFG_CS3_WRITE_XTRA_LGTH 0 /* ns */
-+#define CFG_CS3_EB_ASSERT_DLY 0 /* ns */
-+#define CFG_CS3_EB_NEG_DLY 0 /* ns */
-+#define CFG_CS3_CS_ASSERT_NEG_DLY 0 /* ns */
-+
-+#define CFG_CS3_SYNC_ENABLE 0 /* e...
[truncated message content] |
|
From: <ar...@us...> - 2008-04-03 17:10:06
|
Revision: 791
http://armadeus.svn.sourceforge.net/armadeus/?rev=791&view=rev
Author: artemys
Date: 2008-04-03 10:08:58 -0700 (Thu, 03 Apr 2008)
Log Message:
-----------
[LINUX] Add support for i.MX27 NAND controller
Modified Paths:
--------------
branches/apf2/buildroot/target/device/armadeus/apf27/linux-2.6.25-rc7.config
Added Paths:
-----------
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/240-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_Kconfig.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/241-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_Makefile.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/242-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_mxc_nd.c.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/243-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_mxc_nd.h.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/244-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_nand_base.c.dif
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/245-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_nand_bbt.c.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/246-apf27-pengu-linux-2.6.19.2_include_linux_mtd_nand.h.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/247-apf27-juju-add_NFMS_to_mx27_h.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/248-apf27-juju-add_nand_desc_to_pcm038.diff
Modified: branches/apf2/buildroot/target/device/armadeus/apf27/linux-2.6.25-rc7.config
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/linux-2.6.25-rc7.config 2008-04-03 14:08:15 UTC (rev 790)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/linux-2.6.25-rc7.config 2008-04-03 17:08:58 UTC (rev 791)
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc7
-# Wed Apr 2 22:41:47 2008
+# Thu Apr 3 17:00:23 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -441,7 +441,19 @@
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_MXC=y
+# CONFIG_MTD_NAND_MXC_SWECC is not set
+# CONFIG_MTD_NAND_MXC_FORCE_CE is not set
+# CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 is not set
+# CONFIG_CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
# CONFIG_MTD_ONENAND is not set
#
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/240-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_Kconfig.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/240-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_Kconfig.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/240-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_Kconfig.diff 2008-04-03 17:08:58 UTC (rev 791)
@@ -0,0 +1,55 @@
+--- linux-2.6.19.2-orig/drivers/mtd/nand/Kconfig 2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2/drivers/mtd/nand/Kconfig 2007-11-22 21:20:06.000000000 +0100
+@@ -8,6 +8,8 @@
+ help
+ This enables support for accessing all type of NAND flash
+ devices. For further information see
++ MXC NAND driver cannot be compiled for MX31ADS with XIP enabled.
++ Refer Errata on EMI for using NOR (WEIM) and NAND simultaneously
+ <http://www.linux-mtd.infradead.org/doc/nand.html>.
+
+ if MTD_NAND
+@@ -297,6 +299,43 @@
+ The simulator may simulate various NAND flash chips for the
+ MTD nand layer.
+
++config MTD_NAND_MXC
++ tristate "MXC NAND support"
++ depends on MTD_NAND
++ depends on ARCH_MXC && (!MACH_MX31ADS || !XIP_KERNEL)
++ help
++ This enables the driver for the NAND flash controller on the
++ MXC processors.
++
++config MTD_NAND_MXC_SWECC
++ bool "Software ECC support "
++ depends on MTD_NAND_MXC
++ help
++ This enables the support for Software ECC handling. By
++ default MXC NAND controller Hardware ECC is supported.
++
++
++config MTD_NAND_MXC_FORCE_CE
++ bool "NAND chip select operation support"
++ depends on MTD_NAND_MXC
++ help
++ This enables the NAND chip select by using CE control line. By
++ default CE operation is disabled.
++
++config MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++ bool "ECC correction in S/W"
++ depends on MTD_NAND_MXC
++ help
++ This enables the Option2 NFC ECC correction in software. By
++ default Option 1 is selected. Enable if you need option2 ECC correction.
++
++config CONFIG_MXC_NAND_LOW_LEVEL_ERASE
++ bool "Low level NAND erase"
++ depends on MTD_NAND_MXC
++ help
++ This enables the erase of whole NAND flash. By
++ default low level erase operation is disabled.
++
+ config MTD_NAND_PLATFORM
+ tristate "Support for generic platform NAND driver"
+ depends on MTD_NAND
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/241-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_Makefile.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/241-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_Makefile.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/241-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_Makefile.diff 2008-04-03 17:08:58 UTC (rev 791)
@@ -0,0 +1,9 @@
+--- linux-2.6.19.2-orig/drivers/mtd/nand/Makefile 2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2/drivers/mtd/nand/Makefile 2007-11-22 21:20:04.000000000 +0100
+@@ -32,5 +32,6 @@
+ obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o
+ obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o
+ obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o
++obj-$(CONFIG_MTD_NAND_MXC) += mxc_nd.o
+
+ nand-objs = nand_base.o nand_bbt.o
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/242-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_mxc_nd.c.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/242-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_mxc_nd.c.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/242-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_mxc_nd.c.diff 2008-04-03 17:08:58 UTC (rev 791)
@@ -0,0 +1,1306 @@
+--- linux-2.6.19.2-orig/drivers/mtd/nand/mxc_nd.c 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.19.2/drivers/mtd/nand/mxc_nd.c 2007-11-22 21:20:07.000000000 +0100
+@@ -0,0 +1,1303 @@
++/*
++ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/nand.h>
++#include <linux/interrupt.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/mtd/partitions.h>
++#include <asm/mach/flash.h>
++#include <asm/io.h>
++#include "mxc_nd.h"
++
++/*!
++ * Number of static partitions on NAND Flash.
++ */
++#define NUM_PARTITIONS (sizeof(partition_info)/sizeof(struct mtd_partition))
++
++#define DVR_VER "2.0"
++
++struct mxc_mtd_s {
++ struct mtd_info mtd;
++ struct nand_chip nand;
++ struct mtd_partition *parts;
++ struct device *dev;
++};
++
++static struct mxc_mtd_s *mxc_nand_data = NULL;
++
++/*
++ * Define delays in microsec for NAND device operations
++ */
++#define TROP_US_DELAY 2000
++/*
++ * Macros to get byte and bit positions of ECC
++ */
++#define COLPOS(x) ((x) >> 3)
++#define BITPOS(x) ((x)& 0xf)
++
++/* Define single bit Error positions in Main & Spare area */
++#define MAIN_SINGLEBIT_ERROR 0x4
++#define SPARE_SINGLEBIT_ERROR 0x1
++
++struct nand_info {
++ bool bSpareOnly;
++ bool bStatusRequest;
++ u16 colAddr;
++};
++
++static struct nand_info g_nandfc_info;
++
++#ifdef CONFIG_MTD_NAND_MXC_SWECC
++static int hardware_ecc = 0;
++#else
++static int hardware_ecc = 1;
++#endif
++
++#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++static int Ecc_disabled;
++#endif
++
++static int is2k_Pagesize = 0;
++
++static struct clk *nfc_clk;
++
++/*
++ * OOB placement block for use with hardware ecc generation
++ */
++static struct nand_ecclayout nand_hw_eccoob_8 = {
++ .eccbytes = 5,
++ .eccpos = {6, 7, 8, 9, 10},
++ .oobfree = {{0, 5}, {11, 5}}
++};
++
++static struct nand_ecclayout nand_hw_eccoob_16 = {
++ .eccbytes = 5,
++ .eccpos = {6, 7, 8, 9, 10},
++ .oobfree = {{0, 6}, {12, 4}}
++};
++
++/*!
++ * @defgroup NAND_MTD NAND Flash MTD Driver for MXC processors
++ */
++
++/*!
++ * @file mxc_nd.c
++ *
++ * @brief This file contains the hardware specific layer for NAND Flash on
++ * MXC processor
++ *
++ * @ingroup NAND_MTD
++ */
++
++#ifdef CONFIG_MTD_PARTITIONS
++static const char *part_probes[] = { /* "RedBoot", */ "cmdlinepart", NULL };
++#endif
++
++static wait_queue_head_t irq_waitq;
++
++static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
++{
++ NFC_CONFIG1 |= NFC_INT_MSK; /* Disable interrupt */
++ wake_up(&irq_waitq);
++
++ return IRQ_RETVAL(1);
++}
++
++/*!
++ * This function polls the NANDFC to wait for the basic operation to complete by
++ * checking the INT bit of config2 register.
++ *
++ * @param maxRetries number of retry attempts (separated by 1 us)
++ * @param param parameter for debug
++ * @param useirq True if IRQ should be used rather than polling
++ */
++static void wait_op_done(int maxRetries, u16 param, bool useirq)
++{
++ if (useirq) {
++ if ((NFC_CONFIG2 & NFC_INT) == 0) {
++ NFC_CONFIG1 &= ~NFC_INT_MSK; /* Enable interrupt */
++ wait_event(irq_waitq, NFC_CONFIG2 & NFC_INT);
++ NFC_CONFIG2 &= ~NFC_INT;
++ }
++ } else {
++ while (maxRetries-- > 0) {
++ if (NFC_CONFIG2 & NFC_INT) {
++ NFC_CONFIG2 &= ~NFC_INT;
++ break;
++ }
++ udelay(1);
++ }
++ if (maxRetries <= 0)
++ DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
++ __FUNCTION__, param);
++ }
++}
++
++/*!
++ * This function issues the specified command to the NAND device and
++ * waits for completion.
++ *
++ * @param cmd command for NAND Flash
++ * @param useirq True if IRQ should be used rather than polling
++ */
++static void send_cmd(u16 cmd, bool useirq)
++{
++ DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(0x%x, %d)\n", cmd, useirq);
++
++ NFC_FLASH_CMD = (u16) cmd;
++ NFC_CONFIG2 = NFC_CMD;
++
++ /* Wait for operation to complete */
++ wait_op_done(TROP_US_DELAY, cmd, useirq);
++}
++
++/*!
++ * This function sends an address (or partial address) to the
++ * NAND device. The address is used to select the source/destination for
++ * a NAND command.
++ *
++ * @param addr address to be written to NFC.
++ * @param islast True if this is the last address cycle for command
++ */
++static void send_addr(u16 addr, bool islast)
++{
++ DEBUG(MTD_DEBUG_LEVEL3, "send_addr(0x%x %d)\n", addr, islast);
++
++ NFC_FLASH_ADDR = addr;
++ NFC_CONFIG2 = NFC_ADDR;
++
++ /* Wait for operation to complete */
++ wait_op_done(TROP_US_DELAY, addr, islast);
++}
++
++/*!
++ * This function requests the NANDFC to initate the transfer
++ * of data currently in the NANDFC RAM buffer to the NAND device.
++ *
++ * @param buf_id Specify Internal RAM Buffer number (0-3)
++ * @param bSpareOnly set true if only the spare area is transferred
++ */
++static void send_prog_page(u8 buf_id, bool bSpareOnly)
++{
++ DEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", bSpareOnly);
++
++ /* NANDFC buffer 0 is used for page read/write */
++
++ NFC_BUF_ADDR = buf_id;
++
++ /* Configure spare or page+spare access */
++ if (!is2k_Pagesize) {
++ if (bSpareOnly) {
++ NFC_CONFIG1 |= NFC_SP_EN;
++ } else {
++ NFC_CONFIG1 &= ~(NFC_SP_EN);
++ }
++ }
++ NFC_CONFIG2 = NFC_INPUT;
++
++ /* Wait for operation to complete */
++ wait_op_done(TROP_US_DELAY, bSpareOnly, true);
++}
++
++/*!
++ * This function will correct the single bit ECC error
++ *
++ * @param buf_id Specify Internal RAM Buffer number (0-3)
++ * @param eccpos Ecc byte and bit position
++ * @param bSpareOnly set to true if only spare area needs correction
++ */
++
++static void mxc_nd_correct_error(u8 buf_id, u16 eccpos, bool bSpareOnly)
++{
++ u16 col;
++ u8 pos;
++ volatile u16 *buf;
++
++ /* Get col & bit position of error
++ these macros works for both 8 & 16 bits */
++ col = COLPOS(eccpos); /* Get half-word position */
++ pos = BITPOS(eccpos); /* Get bit position */
++
++ DEBUG(MTD_DEBUG_LEVEL3,
++ "mxc_nd_correct_error (col=%d pos=%d)\n", col, pos);
++
++ /* Set the pointer for main / spare area */
++ if (!bSpareOnly) {
++ buf = MAIN_AREA0 + (col >> 1) + (512 * buf_id);
++ } else {
++ buf = SPARE_AREA0 + (col >> 1) + (16 * buf_id);
++ }
++
++ /* Fix the data */
++ *buf ^= (1 << pos);
++}
++
++/*!
++ * This function will maintains state of single bit Error
++ * in Main & spare area
++ *
++ * @param buf_id Specify Internal RAM Buffer number (0-3)
++ * @param spare set to true if only spare area needs correction
++ */
++static void mxc_nd_correct_ecc(u8 buf_id, bool spare)
++{
++#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++ static int lastErrMain = 0, lastErrSpare = 0; /* To maintain single bit
++ error in previous page */
++#endif
++ u16 value, ecc_status;
++ /* Read the ECC result */
++ ecc_status = NFC_ECC_STATUS_RESULT;
++ DEBUG(MTD_DEBUG_LEVEL3,
++ "mxc_nd_correct_ecc (Ecc status=%x)\n", ecc_status);
++
++#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++ /* Check for Error in Mainarea */
++ if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) {
++ /* Check for error in previous page */
++ if (lastErrMain && !spare) {
++ value = NFC_RSLTMAIN_AREA;
++ /* Correct single bit error in Mainarea
++ NFC will not correct the error in
++ current page */
++ mxc_nd_correct_error(buf_id, value, false);
++ } else {
++ /* Set if single bit error in current page */
++ lastErrMain = 1;
++ }
++ } else {
++ /* Reset if no single bit error in current page */
++ lastErrMain = 0;
++ }
++
++ /* Check for Error in Sparearea */
++ if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) {
++ /* Check for error in previous page */
++ if (lastErrSpare) {
++ value = NFC_RSLTSPARE_AREA;
++ /* Correct single bit error in Mainarea
++ NFC will not correct the error in
++ current page */
++ mxc_nd_correct_error(buf_id, value, true);
++ } else {
++ /* Set if single bit error in current page */
++ lastErrSpare = 1;
++ }
++ } else {
++ /* Reset if no single bit error in current page */
++ lastErrSpare = 0;
++ }
++#else
++ if (((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR)
++ || ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR)) {
++ if (Ecc_disabled) {
++ if ((ecc_status & 0xC) == MAIN_SINGLEBIT_ERROR) {
++ value = NFC_RSLTMAIN_AREA;
++ /* Correct single bit error in Mainarea
++ NFC will not correct the error in
++ current page */
++ mxc_nd_correct_error(buf_id, value, false);
++ }
++ if ((ecc_status & 0x3) == SPARE_SINGLEBIT_ERROR) {
++ value = NFC_RSLTSPARE_AREA;
++ /* Correct single bit error in Mainarea
++ NFC will not correct the error in
++ current page */
++ mxc_nd_correct_error(buf_id, value, true);
++ }
++
++ } else {
++ /* Disable ECC */
++ NFC_CONFIG1 &= ~(NFC_ECC_EN);
++ Ecc_disabled = 1;
++ }
++ } else if (ecc_status == 0) {
++ if (Ecc_disabled) {
++ /* Enable ECC */
++ NFC_CONFIG1 |= NFC_ECC_EN;
++ Ecc_disabled = 0;
++ }
++ } else {
++ /* 2-bit Error Do nothing */
++ }
++#endif /* CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 */
++
++}
++
++/*!
++ * This function requests the NANDFC to initated the transfer
++ * of data from the NAND device into in the NANDFC ram buffer.
++ *
++ * @param buf_id Specify Internal RAM Buffer number (0-3)
++ * @param bSpareOnly set true if only the spare area is transferred
++ */
++static void send_read_page(u8 buf_id, bool bSpareOnly)
++{
++ DEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", bSpareOnly);
++
++ /* NANDFC buffer 0 is used for page read/write */
++ NFC_BUF_ADDR = buf_id;
++
++ /* Configure spare or page+spare access */
++ if (!is2k_Pagesize) {
++ if (bSpareOnly) {
++ NFC_CONFIG1 |= NFC_SP_EN;
++ } else {
++ NFC_CONFIG1 &= ~(NFC_SP_EN);
++ }
++ }
++
++ NFC_CONFIG2 = NFC_OUTPUT;
++
++ /* Wait for operation to complete */
++ wait_op_done(TROP_US_DELAY, bSpareOnly, true);
++
++ /* If there are single bit errors in
++ two consecutive page reads then
++ the error is not corrected by the
++ NFC for the second page.
++ Correct single bit error in driver */
++
++ mxc_nd_correct_ecc(buf_id, bSpareOnly);
++}
++
++/*!
++ * This function requests the NANDFC to perform a read of the
++ * NAND device ID.
++ */
++static void send_read_id(void)
++{
++ struct nand_chip *this = &mxc_nand_data->nand;
++
++ /* NANDFC buffer 0 is used for device ID output */
++ NFC_BUF_ADDR = 0x0;
++
++ /* Read ID into main buffer */
++ NFC_CONFIG1 &= (~(NFC_SP_EN));
++ NFC_CONFIG2 = NFC_ID;
++
++ /* Wait for operation to complete */
++ wait_op_done(TROP_US_DELAY, 0, true);
++
++ if (this->options & NAND_BUSWIDTH_16) {
++ volatile u16 *mainBuf = MAIN_AREA0;
++
++ /*
++ * Pack the every-other-byte result for 16-bit ID reads
++ * into every-byte as the generic code expects and various
++ * chips implement.
++ */
++
++ mainBuf[0] = (mainBuf[0] & 0xff) | ((mainBuf[1] & 0xff) << 8);
++ mainBuf[1] = (mainBuf[2] & 0xff) | ((mainBuf[3] & 0xff) << 8);
++ mainBuf[2] = (mainBuf[4] & 0xff) | ((mainBuf[5] & 0xff) << 8);
++ }
++}
++
++/*!
++ * This function requests the NANDFC to perform a read of the
++ * NAND device status and returns the current status.
++ *
++ * @return device status
++ */
++static u16 get_dev_status(void)
++{
++ volatile u16 *mainBuf = MAIN_AREA1;
++ u32 store;
++ u16 ret;
++ /* Issue status request to NAND device */
++
++ /* store the main area1 first word, later do recovery */
++ store = *((u32 *) mainBuf);
++ /*
++ * NANDFC buffer 1 is used for device status to prevent
++ * corruption of read/write buffer on status requests.
++ */
++ NFC_BUF_ADDR = 1;
++
++ /* Read status into main buffer */
++ NFC_CONFIG1 &= (~(NFC_SP_EN));
++ NFC_CONFIG2 = NFC_STATUS;
++
++ /* Wait for operation to complete */
++ wait_op_done(TROP_US_DELAY, 0, true);
++
++ /* Status is placed in first word of main buffer */
++ /* get status, then recovery area 1 data */
++ ret = mainBuf[0];
++ *((u32 *) mainBuf) = store;
++
++ return ret;
++}
++
++/*!
++ * This functions is used by upper layer to checks if device is ready
++ *
++ * @param mtd MTD structure for the NAND Flash
++ *
++ * @return 0 if device is busy else 1
++ */
++static int mxc_nand_dev_ready(struct mtd_info *mtd)
++{
++ /*
++ * NFC handles R/B internally.Therefore,this function
++ * always returns status as ready.
++ */
++ return 1;
++}
++
++static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++ /*
++ * If HW ECC is enabled, we turn it on during init. There is
++ * no need to enable again here.
++ */
++}
++
++static int mxc_nand_correct_data(struct mtd_info *mtd, u_char * dat,
++ u_char * read_ecc, u_char * calc_ecc)
++{
++ /*
++ * 1-Bit errors are automatically corrected in HW. No need for
++ * additional correction. 2-Bit errors cannot be corrected by
++ * HW ECC, so we need to return failure
++ */
++ u16 ecc_status = NFC_ECC_STATUS_RESULT;
++
++ if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
++ DEBUG(MTD_DEBUG_LEVEL0,
++ "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
++ return -1;
++ }
++
++ return 0;
++}
++
++static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat,
++ u_char * ecc_code)
++{
++ /*
++ * Just return success. HW ECC does not read/write the NFC spare
++ * buffer. Only the FLASH spare area contains the calcuated ECC.
++ */
++ return 0;
++}
++
++/*!
++ * This function reads byte from the NAND Flash
++ *
++ * @param mtd MTD structure for the NAND Flash
++ *
++ * @return data read from the NAND Flash
++ */
++static u_char mxc_nand_read_byte(struct mtd_info *mtd)
++{
++ u_char retVal = 0;
++ u16 col, rdWord;
++ volatile u16 *mainBuf = MAIN_AREA0;
++ volatile u16 *spareBuf = SPARE_AREA0;
++
++ /* Check for status request */
++ if (g_nandfc_info.bStatusRequest) {
++ return (get_dev_status() & 0xFF);
++ }
++
++ /* Get column for 16-bit access */
++ col = g_nandfc_info.colAddr >> 1;
++
++ /* If we are accessing the spare region */
++ if (g_nandfc_info.bSpareOnly) {
++ rdWord = spareBuf[col];
++ } else {
++ rdWord = mainBuf[col];
++ }
++
++ /* Pick upper/lower byte of word from RAM buffer */
++ if (g_nandfc_info.colAddr & 0x1) {
++ retVal = (rdWord >> 8) & 0xFF;
++ } else {
++ retVal = rdWord & 0xFF;
++ }
++
++ /* Update saved column address */
++ g_nandfc_info.colAddr++;
++
++ return retVal;
++}
++
++/*!
++ * This function reads word from the NAND Flash
++ *
++ * @param mtd MTD structure for the NAND Flash
++ *
++ * @return data read from the NAND Flash
++ */
++static u16 mxc_nand_read_word(struct mtd_info *mtd)
++{
++ u16 col;
++ u16 rdWord, retVal;
++ volatile u16 *p;
++
++ DEBUG(MTD_DEBUG_LEVEL3,
++ "mxc_nand_read_word(col = %d)\n", g_nandfc_info.colAddr);
++
++ col = g_nandfc_info.colAddr;
++ /* Adjust saved column address */
++ if (col < mtd->writesize && g_nandfc_info.bSpareOnly)
++ col += mtd->writesize;
++
++ if (col < mtd->writesize)
++ p = (MAIN_AREA0) + (col >> 1);
++ else
++ p = (SPARE_AREA0) + ((col - mtd->writesize) >> 1);
++
++ if (col & 1) {
++ rdWord = *p;
++ retVal = (rdWord >> 8) & 0xff;
++ rdWord = *(p + 1);
++ retVal |= (rdWord << 8) & 0xff00;
++
++ } else {
++ retVal = *p;
++
++ }
++
++ /* Update saved column address */
++ g_nandfc_info.colAddr = col + 2;
++
++ return retVal;
++}
++
++/*!
++ * This function writes data of length \b len to buffer \b buf. The data to be
++ * written on NAND Flash is first copied to RAMbuffer. After the Data Input
++ * Operation by the NFC, the data is written to NAND Flash
++ *
++ * @param mtd MTD structure for the NAND Flash
++ * @param buf data to be written to NAND Flash
++ * @param len number of bytes to be written
++ */
++static void mxc_nand_write_buf(struct mtd_info *mtd,
++ const u_char * buf, int len)
++{
++ int n;
++ int col;
++ int i = 0;
++
++ DEBUG(MTD_DEBUG_LEVEL3,
++ "mxc_nand_write_buf(col = %d, len = %d)\n", g_nandfc_info.colAddr,
++ len);
++
++ col = g_nandfc_info.colAddr;
++
++ /* Adjust saved column address */
++ if (col < mtd->writesize && g_nandfc_info.bSpareOnly)
++ col += mtd->writesize;
++
++ n = mtd->writesize + mtd->oobsize - col;
++ n = min(len, n);
++
++ DEBUG(MTD_DEBUG_LEVEL3,
++ "%s:%d: col = %d, n = %d\n", __FUNCTION__, __LINE__, col, n);
++
++ while (n) {
++ volatile u32 *p;
++ if (col < mtd->writesize)
++ p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3));
++ else
++ p = (volatile u32 *)((ulong) (SPARE_AREA0) -
++ mtd->writesize + (col & ~3));
++
++ DEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __FUNCTION__,
++ __LINE__, p);
++
++ if (((col | (int)&buf[i]) & 3) || n < 16) {
++ u32 data = 0;
++
++ if (col & 3 || n < 4)
++ data = *p;
++
++ switch (col & 3) {
++ case 0:
++ if (n) {
++ data = (data & 0xffffff00) |
++ (buf[i++] << 0);
++ n--;
++ col++;
++ }
++ case 1:
++ if (n) {
++ data = (data & 0xffff00ff) |
++ (buf[i++] << 8);
++ n--;
++ col++;
++ }
++ case 2:
++ if (n) {
++ data = (data & 0xff00ffff) |
++ (buf[i++] << 16);
++ n--;
++ col++;
++ }
++ case 3:
++ if (n) {
++ data = (data & 0x00ffffff) |
++ (buf[i++] << 24);
++ n--;
++ col++;
++ }
++ }
++
++ *p = data;
++ } else {
++ int m = mtd->writesize - col;
++
++ if (col >= mtd->writesize)
++ m += mtd->oobsize;
++
++ m = min(n, m) & ~3;
++
++ DEBUG(MTD_DEBUG_LEVEL3,
++ "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
++ __FUNCTION__, __LINE__, n, m, i, col);
++
++ memcpy((void *)(p), &buf[i], m);
++ col += m;
++ i += m;
++ n -= m;
++ }
++ }
++ /* Update saved column address */
++ g_nandfc_info.colAddr = col;
++
++}
++
++/*!
++ * This function id is used to read the data buffer from the NAND Flash. To
++ * read the data from NAND Flash first the data output cycle is initiated by
++ * the NFC, which copies the data to RAMbuffer. This data of length \b len is
++ * then copied to buffer \b buf.
++ *
++ * @param mtd MTD structure for the NAND Flash
++ * @param buf data to be read from NAND Flash
++ * @param len number of bytes to be read
++ */
++static void mxc_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
++{
++
++ int n;
++ int col;
++ int i = 0;
++
++ DEBUG(MTD_DEBUG_LEVEL3,
++ "mxc_nand_read_buf(col = %d, len = %d)\n", g_nandfc_info.colAddr,
++ len);
++
++ col = g_nandfc_info.colAddr;
++ /* Adjust saved column address */
++ if (col < mtd->writesize && g_nandfc_info.bSpareOnly)
++ col += mtd->writesize;
++
++ n = mtd->writesize + mtd->oobsize - col;
++ n = min(len, n);
++
++ while (n) {
++ volatile u32 *p;
++
++ if (col < mtd->writesize)
++ p = (volatile u32 *)((ulong) (MAIN_AREA0) + (col & ~3));
++ else
++ p = (volatile u32 *)((ulong) (SPARE_AREA0) -
++ mtd->writesize + (col & ~3));
++
++ if (((col | (int)&buf[i]) & 3) || n < 16) {
++ u32 data;
++
++ data = *p;
++ switch (col & 3) {
++ case 0:
++ if (n) {
++ buf[i++] = (u8) (data);
++ n--;
++ col++;
++ }
++ case 1:
++ if (n) {
++ buf[i++] = (u8) (data >> 8);
++ n--;
++ col++;
++ }
++ case 2:
++ if (n) {
++ buf[i++] = (u8) (data >> 16);
++ n--;
++ col++;
++ }
++ case 3:
++ if (n) {
++ buf[i++] = (u8) (data >> 24);
++ n--;
++ col++;
++ }
++ }
++ } else {
++ int m = mtd->writesize - col;
++
++ if (col >= mtd->writesize)
++ m += mtd->oobsize;
++
++ m = min(n, m) & ~3;
++ memcpy(&buf[i], (void *)(p), m);
++ col += m;
++ i += m;
++ n -= m;
++ }
++ }
++ /* Update saved column address */
++ g_nandfc_info.colAddr = col;
++
++}
++
++/*!
++ * This function is used by the upper layer to verify the data in NAND Flash
++ * with the data in the \b buf.
++ *
++ * @param mtd MTD structure for the NAND Flash
++ * @param buf data to be verified
++ * @param len length of the data to be verified
++ *
++ * @return -EFAULT if error else 0
++ *
++ */
++static int
++mxc_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
++{
++ return -EFAULT;
++}
++
++/*!
++ * This function is used by upper layer for select and deselect of the NAND
++ * chip
++ *
++ * @param mtd MTD structure for the NAND Flash
++ * @param chip val indicating select or deselect
++ */
++static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
++{
++#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
++ if (chip > 0) {
++ DEBUG(MTD_DEBUG_LEVEL0,
++ "ERROR: Illegal chip select (chip = %d)\n", chip);
++ return;
++ }
++
++ if (chip == -1) {
++ NFC_CONFIG1 &= (~(NFC_CE));
++ return;
++ }
++
++ NFC_CONFIG1 |= NFC_CE;
++#endif
++
++ switch (chip) {
++ case -1:
++ /* Disable the NFC clock */
++ clk_disable(nfc_clk);
++ break;
++ case 0:
++ /* Enable the NFC clock */
++ clk_enable(nfc_clk);
++ break;
++
++ default:
++ break;
++ }
++}
++
++/*!
++ * This function is used by the upper layer to write command to NAND Flash for
++ * different operations to be carried out on NAND Flash
++ *
++ * @param mtd MTD structure for the NAND Flash
++ * @param command command for NAND Flash
++ * @param column column offset for the page read
++ * @param page_addr page to be read from NAND Flash
++ */
++static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
++ int column, int page_addr)
++{
++ bool useirq = true;
++
++ DEBUG(MTD_DEBUG_LEVEL3,
++ "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
++ command, column, page_addr);
++
++ if ((NFMS >> NFMS_BIT) & 0x1)
++ is2k_Pagesize = 1;
++
++ /*
++ * Reset command state information
++ */
++ g_nandfc_info.bStatusRequest = false;
++
++ /*
++ * Command pre-processing step
++ */
++ switch (command) {
++
++ case NAND_CMD_STATUS:
++ g_nandfc_info.colAddr = 0;
++ g_nandfc_info.bStatusRequest = true;
++ break;
++
++ case NAND_CMD_READ0:
++ g_nandfc_info.colAddr = column;
++ g_nandfc_info.bSpareOnly = false;
++ useirq = false;
++ break;
++
++ case NAND_CMD_READOOB:
++ g_nandfc_info.colAddr = column;
++ g_nandfc_info.bSpareOnly = true;
++ useirq = false;
++ if (is2k_Pagesize)
++ command = NAND_CMD_READ0; /* only READ0 is valid */
++ break;
++
++ case NAND_CMD_SEQIN:
++ if (column >= mtd->writesize) {
++ if (is2k_Pagesize) {
++ /**
++ * FIXME: before send SEQIN command for write OOB,
++ * We must read one page out.
++ * For K9F1GXX has no READ1 command to set current HW
++ * pointer to spare area, we must write the whole page including OOB together.
++ */
++ /* call itself to read a page */
++ mxc_nand_command(mtd, NAND_CMD_READ0, 0,
++ page_addr);
++ }
++ g_nandfc_info.colAddr = column - mtd->writesize;
++ g_nandfc_info.bSpareOnly = true;
++ /* Set program pointer to spare region */
++ if (!is2k_Pagesize)
++ send_cmd(NAND_CMD_READOOB, false);
++ } else {
++ g_nandfc_info.bSpareOnly = false;
++ g_nandfc_info.colAddr = column;
++ /* Set program pointer to page start */
++ if (!is2k_Pagesize)
++ send_cmd(NAND_CMD_READ0, false);
++ }
++ useirq = false;
++ break;
++
++ case NAND_CMD_PAGEPROG:
++#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++ if (Ecc_disabled) {
++ /* Enable Ecc for page writes */
++ NFC_CONFIG1 |= NFC_ECC_EN;
++ }
++#endif
++
++ send_prog_page(0, g_nandfc_info.bSpareOnly);
++
++ if (is2k_Pagesize) {
++ /* data in 4 areas datas */
++ send_prog_page(1, g_nandfc_info.bSpareOnly);
++ send_prog_page(2, g_nandfc_info.bSpareOnly);
++ send_prog_page(3, g_nandfc_info.bSpareOnly);
++ }
++
++ break;
++
++ case NAND_CMD_ERASE1:
++ useirq = false;
++ break;
++ }
++
++ /*
++ * Write out the command to the device.
++ */
++ send_cmd(command, useirq);
++
++ /*
++ * Write out column address, if necessary
++ */
++ if (column != -1) {
++ /*
++ * MXC NANDFC can only perform full page+spare or
++ * spare-only read/write. When the upper layers
++ * layers perform a read/write buf operation,
++ * we will used the saved column adress to index into
++ * the full page.
++ */
++ send_addr(0, page_addr == -1);
++ if (is2k_Pagesize)
++ send_addr(0, false); /* another col addr cycle for 2k page */
++ }
++
++ /*
++ * Write out page address, if necessary
++ */
++ if (page_addr != -1) {
++ send_addr((page_addr & 0xff), false); /* paddr_0 - p_addr_7 */
++
++ if (is2k_Pagesize) {
++ send_addr((page_addr >> 8) & 0xFF, false);
++ if (mtd->size >= 0x42000000) {
++ send_addr((page_addr >> 16) & 0xff, true);
++ }
++ } else {
++ /* One more address cycle for higher density devices */
++ if (mtd->size >= 0x4000000) {
++ send_addr((page_addr >> 8) & 0xff, false); /* paddr_8 - paddr_15 */
++ send_addr((page_addr >> 16) & 0xff, true);
++ } else
++ send_addr((page_addr >> 8) & 0xff, true); /* paddr_8 - paddr_15 */
++ }
++ }
++
++ /*
++ * Command post-processing step
++ */
++ switch (command) {
++
++ case NAND_CMD_RESET:
++ break;
++
++ case NAND_CMD_READOOB:
++ case NAND_CMD_READ0:
++ if (is2k_Pagesize) {
++ /* send read confirm command */
++ send_cmd(NAND_CMD_READSTART, true);
++ /* read for each AREA */
++ send_read_page(0, g_nandfc_info.bSpareOnly);
++ send_read_page(1, g_nandfc_info.bSpareOnly);
++ send_read_page(2, g_nandfc_info.bSpareOnly);
++ send_read_page(3, g_nandfc_info.bSpareOnly);
++ } else {
++ send_read_page(0, g_nandfc_info.bSpareOnly);
++ }
++ break;
++
++ case NAND_CMD_READID:
++ send_read_id();
++ break;
++
++ case NAND_CMD_PAGEPROG:
++#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++ if (Ecc_disabled) {
++ /* Disble Ecc after page writes */
++ NFC_CONFIG1 &= ~(NFC_ECC_EN);
++ }
++#endif
++ break;
++
++ case NAND_CMD_STATUS:
++ break;
++
++ case NAND_CMD_ERASE2:
++ break;
++ }
++}
++
++#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE
++static void mxc_low_erase(struct mtd_info *mtd)
++{
++
++ struct nand_chip *this = mtd->priv;
++ unsigned int page_addr, addr;
++ u_char status;
++
++ DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : mxc_low_erase:Erasing NAND\n");
++ for (addr = 0; addr < this->chipsize; addr += mtd->erasesize) {
++ page_addr = addr / mtd->writesize;
++ mxc_nand_command(mtd, NAND_CMD_ERASE1, -1, page_addr);
++ mxc_nand_command(mtd, NAND_CMD_ERASE2, -1, -1);
++ mxc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
++ status = mxc_nand_read_byte(mtd);
++ if (status & NAND_STATUS_FAIL) {
++ printk(KERN_ERR
++ "ERASE FAILED(block = %d,status = 0x%x)\n",
++ addr / mtd->erasesize, status);
++ }
++ }
++
++}
++#endif
++/*!
++ * This function is called during the driver binding process.
++ *
++ * @param pdev the device structure used to store device specific
++ * information that is used by the suspend, resume and
++ * remove functions
++ *
++ * @return The function always returns 0.
++ */
++static int __init mxcnd_probe(struct platform_device *pdev)
++{
++ struct nand_chip *this;
++ struct mtd_info *mtd;
++ struct flash_platform_data *flash = pdev->dev.platform_data;
++ int nr_parts = 0;
++
++ int err = 0;
++ /* Allocate memory for MTD device structure and private data */
++ mxc_nand_data = kmalloc(sizeof(struct mxc_mtd_s), GFP_KERNEL);
++ if (!mxc_nand_data) {
++ printk(KERN_ERR "%s: failed to allocate mtd_info\n",
++ __FUNCTION__);
++ err = -ENOMEM;
++ goto out;
++ }
++ memset(mxc_nand_data, 0, sizeof(struct mxc_mtd_s));
++ memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info));
++
++ mxc_nand_data->dev = &pdev->dev;
++ /* structures must be linked */
++ this = &mxc_nand_data->nand;
++ mtd = &mxc_nand_data->mtd;
++ mtd->priv = this;
++ mtd->owner = THIS_MODULE;
++
++ /* 50 us command delay time */
++ this->chip_delay = 5;
++
++ this->priv = mxc_nand_data;
++ this->dev_ready = mxc_nand_dev_ready;
++ this->cmdfunc = mxc_nand_command;
++ this->select_chip = mxc_nand_select_chip;
++ this->read_byte = mxc_nand_read_byte;
++ this->read_word = mxc_nand_read_word;
++ this->write_buf = mxc_nand_write_buf;
++ this->read_buf = mxc_nand_read_buf;
++ this->verify_buf = mxc_nand_verify_buf;
++
++ nfc_clk = clk_get(&pdev->dev, "nfc_clk");
++ clk_enable(nfc_clk);
++
++ NFC_CONFIG1 |= NFC_INT_MSK;
++ init_waitqueue_head(&irq_waitq);
++ err = request_irq(INT_NANDFC, mxc_nfc_irq, 0, "mxc_nd", NULL);
++ if (err) {
++ goto out_1;
++ }
++
++ if (hardware_ecc) {
++ this->ecc.calculate = mxc_nand_calculate_ecc;
++ this->ecc.hwctl = mxc_nand_enable_hwecc;
++ this->ecc.correct = mxc_nand_correct_data;
++ this->ecc.mode = NAND_ECC_HW;
++ this->ecc.size = 512;
++ this->ecc.bytes = 3;
++ this->ecc.layout = &nand_hw_eccoob_8;
++ NFC_CONFIG1 |= NFC_ECC_EN;
++ } else {
++ this->ecc.mode = NAND_ECC_SOFT;
++ }
++
++ /* Reset NAND */
++ this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
++
++ /* preset operation */
++ /* Unlock the internal RAM Buffer */
++ NFC_CONFIG = 0x2;
++
++ /* Blocks to be unlocked */
++ NFC_UNLOCKSTART_BLKADDR = 0x0;
++ NFC_UNLOCKEND_BLKADDR = 0x4000;
++
++ /* Unlock Block Command for given address range */
++ NFC_WRPROT = 0x4;
++
++ /* NAND bus width determines access funtions used by upper layer */
++ if (flash->width == 2) {
++ this->options |= NAND_BUSWIDTH_16;
++ this->ecc.layout = &nand_hw_eccoob_16;
++ } else {
++ this->options |= 0;
++ }
++
++ is2k_Pagesize = 0;
++
++ /* Scan to find existence of the device */
++ if (nand_scan(mtd, 1)) {
++ DEBUG(MTD_DEBUG_LEVEL0,
++ "MXC_ND: Unable to find any NAND device.\n");
++ err = -ENXIO;
++ goto out_1;
++ }
++
++ /* Register the partitions */
++#ifdef CONFIG_MTD_PARTITIONS
++ nr_parts =
++ parse_mtd_partitions(mtd, part_probes, &mxc_nand_data->parts, 0);
++ if (nr_parts > 0)
++ add_mtd_partitions(mtd, mxc_nand_data->parts, nr_parts);
++ else if (flash->parts)
++ add_mtd_partitions(mtd, flash->parts, flash->nr_parts);
++ else
++#endif
++ {
++ pr_info("Registering %s as whole device\n", mtd->name);
++ add_mtd_device(mtd);
++ }
++#ifdef CONFIG_MXC_NAND_LOW_LEVEL_ERASE
++ /* Erase all the blocks of a NAND */
++ mxc_low_erase(mtd);
++#endif
++
++ platform_set_drvdata(pdev, mtd);
++ return 0;
++
++ out_1:
++ kfree(mxc_nand_data);
++ out:
++ return err;
++
++}
++
++ /*!
++ * Dissociates the driver from the device.
++ *
++ * @param pdev the device structure used to give information on which
++ *
++ * @return The function always returns 0.
++ */
++
++static int __exit mxcnd_remove(struct platform_device *pdev)
++{
++ struct mtd_info *mtd = platform_get_drvdata(pdev);
++
++ clk_put(nfc_clk);
++ platform_set_drvdata(pdev, NULL);
++
++ if (mxc_nand_data) {
++ nand_release(mtd);
++ free_irq(INT_NANDFC, NULL);
++ kfree(mxc_nand_data);
++ }
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++/*!
++ * This function is called to put the NAND in a low power state. Refer to the
++ * document driver-model/driver.txt in the kernel source tree for more
++ * information.
++ *
++ * @param pdev the device information structure
++ *
++ * @param state the power state the device is entering
++ *
++ * @return The function returns 0 on success and -1 on failure
++ */
++
++static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ struct mtd_info *info = platform_get_drvdata(pdev);
++ int ret = 0;
++
++ DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
++ if (info)
++ ret = info->suspend(info);
++
++ /* Disable the NFC clock */
++ clk_disable(nfc_clk);
++
++ return ret;
++}
++
++/*!
++ * This function is called to bring the NAND back from a low power state. Refer
++ * to the document driver-model/driver.txt in the kernel source tree for more
++ * information.
++ *
++ * @param pdev the device information structure
++ *
++ * @return The function returns 0 on success and -1 on failure
++ */
++static int mxcnd_resume(struct platform_device *pdev)
++{
++ struct mtd_info *info = platform_get_drvdata(pdev);
++ int ret = 0;
++
++ DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
++ /* Enable the NFC clock */
++ clk_enable(nfc_clk);
++
++ if (info) {
++ info->resume(info);
++ }
++
++ return ret;
++}
++
++#else
++#define mxcnd_suspend NULL
++#define mxcnd_resume NULL
++#endif /* CONFIG_PM */
++
++/*!
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver mxcnd_driver = {
++ .driver = {
++ .name = "mxc_nand_flash",
++ },
++ .probe = mxcnd_probe,
++ .remove = __exit_p(mxcnd_remove),
++ .suspend = mxcnd_suspend,
++ .resume = mxcnd_resume,
++};
++
++/*!
++ * Main initialization routine
++ * @return 0 if successful; non-zero otherwise
++ */
++static int __init mxc_nd_init(void)
++{
++ /* Register the device driver structure. */
++ pr_info("MXC MTD nand Driver %s\n", DVR_VER);
++ if (platform_driver_register(&mxcnd_driver) != 0) {
++ printk(KERN_ERR "Driver register failed for mxcnd_driver\n");
++ return -ENODEV;
++ }
++ return 0;
++}
++
++/*!
++ * Clean up routine
++ */
++static void __exit mxc_nd_cleanup(void)
++{
++ /* Unregister the device structure */
++ platform_driver_unregister(&mxcnd_driver);
++}
++
++module_init(mxc_nd_init);
++module_exit(mxc_nd_cleanup);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC NAND MTD driver");
++MODULE_LICENSE("GPL");
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/243-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_mxc_nd.h.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/243-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_mxc_nd.h.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/243-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_mxc_nd.h.diff 2008-04-03 17:08:58 UTC (rev 791)
@@ -0,0 +1,110 @@
+--- linux-2.6.19.2-orig/drivers/mtd/nand/mxc_nd.h 1970-01-01 01:00:00.000000000 +0100
++++ linux-2.6.19.2/drivers/mtd/nand/mxc_nd.h 2007-11-22 21:20:07.000000000 +0100
+@@ -0,0 +1,107 @@
++/*
++ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++/*
++ * The code contained herein is licensed under the GNU General Public
++ * License. You may obtain a copy of the GNU General Public License
++ * Version 2 or later at the following locations:
++ *
++ * http://www.opensource.org/licenses/gpl-license.html
++ * http://www.gnu.org/copyleft/gpl.html
++ */
++
++/*!
++ * @file mxc_nd.h
++ *
++ * @brief This file contains the NAND Flash Controller register information.
++ *
++ *
++ * @ingroup NAND_MTD
++ */
++
++#ifndef __MXC_ND_H__
++#define __MXC_ND_H__
++
++#include <asm/hardware.h>
++
++/*
++ * Addresses for NFC registers
++ */
++#define NFC_BUF_SIZE (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE00)))
++#define NFC_BUF_ADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE04)))
++#define NFC_FLASH_ADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE06)))
++#define NFC_FLASH_CMD (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE08)))
++#define NFC_CONFIG (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0A)))
++#define NFC_ECC_STATUS_RESULT (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0C)))
++#define NFC_RSLTMAIN_AREA (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE0E)))
++#define NFC_RSLTSPARE_AREA (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE10)))
++#define NFC_WRPROT (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE12)))
++#define NFC_UNLOCKSTART_BLKADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE14)))
++#define NFC_UNLOCKEND_BLKADDR (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE16)))
++#define NFC_NF_WRPRST (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE18)))
++#define NFC_CONFIG1 (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE1A)))
++#define NFC_CONFIG2 (*((volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0xE1C)))
++
++/*!
++ * Addresses for NFC RAM BUFFER Main area 0
++ */
++#define MAIN_AREA0 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x000)
++#define MAIN_AREA1 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x200)
++
++/*!
++ * Addresses for NFC SPARE BUFFER Spare area 0
++ */
++#define SPARE_AREA0 (volatile u16 *)IO_ADDRESS(NFC_BASE_ADDR + 0x800)
++
++/*!
++ * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
++ * operation
++ */
++#define NFC_CMD 0x1
++
++/*!
++ * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
++ * operation
++ */
++#define NFC_ADDR 0x2
++
++/*!
++ * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
++ * operation
++ */
++#define NFC_INPUT 0x4
++
++/*!
++ * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data Output
++ * operation
++ */
++#define NFC_OUTPUT 0x8
++
++/*!
++ * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
++ * operation
++ */
++#define NFC_ID 0x10
++
++/*!
++ * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read Status
++ * operation
++ */
++#define NFC_STATUS 0x20
++
++/*!
++ * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
++ * operation
++ */
++#define NFC_INT 0x8000
++
++#define NFC_SP_EN (1 << 2)
++#define NFC_ECC_EN (1 << 3)
++#define NFC_INT_MSK (1 << 4)
++#define NFC_BIG (1 << 5)
++#define NFC_RST (1 << 6)
++#define NFC_CE (1 << 7)
++#define NFC_ONE_CYCLE (1 << 8)
++
++#endif /* MXCND_H */
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/244-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_nand_base.c.dif
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/244-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_nand_base.c.dif (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/244-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_nand_base.c.dif 2008-04-03 17:08:58 UTC (rev 791)
@@ -0,0 +1,14 @@
+--- linux-2.6.19.2-orig/drivers/mtd/nand/nand_base.c 2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2/drivers/mtd/nand/nand_base.c 2007-11-22 21:20:04.000000000 +0100
+@@ -2272,6 +2272,11 @@
+ if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
+ chip->cmdfunc = nand_command_lp;
+
++ /*if boot from nor flash, and the card is 2k pagesize,then need enable this bit*/
++ if(mtd->writesize==NAND_PAGESIZE_2KB){
++ NFMS |= (1 << NFMS_BIT);
++ }
++
+ printk(KERN_INFO "NAND device: Manufacturer ID:"
+ " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
+ nand_manuf_ids[maf_idx].name, type->name);
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/245-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_nand_bbt.c.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/245-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_nand_bbt.c.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/245-apf27-pengu-linux-2.6.19.2_drivers_mtd_nand_nand_bbt.c.diff 2008-04-03 17:08:58 UTC (rev 791)
@@ -0,0 +1,16 @@
+--- linux-2.6.19.2-orig/drivers/mtd/nand/nand_bbt.c 2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2/drivers/mtd/nand/nand_bbt.c 2007-11-22 21:20:04.000000000 +0100
+@@ -1182,8 +1182,11 @@
+ this->bbt_td = NULL;
+ this->bbt_md = NULL;
+ if (!this->badblock_pattern) {
+- this->badblock_pattern = (mtd->writesize > 512) ?
+- &largepage_memorybased : &smallpage_memorybased;
++ if(mtd->writesize ==NAND_PAGESIZE_2KB)
++ this->badblock_pattern = &smallpage_memorybased;
++ else
++ this->badblock_pattern = (mtd->writesize > 512) ?
++ &largepage_memorybased : &smallpage_memorybased;
+ }
+ }
+ return nand_scan_bbt(mtd, this->badblock_pattern);
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/246-apf27-pengu-linux-2.6.19.2_include_linux_mtd_nand.h.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/246-apf27-pengu-linux-2.6.19.2_include_linux_mtd_nand.h.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/246-apf27-pengu-linux-2.6.19.2_include_linux_mtd_nand.h.diff 2008-04-03 17:08:58 UTC (rev 791)
@@ -0,0 +1,12 @@
+--- linux-2.6.19.2-orig/include/linux/mtd/nand.h 2007-01-10 20:10:37.000000000 +0100
++++ linux-2.6.19.2/include/linux/mtd/nand.h 2007-11-22 21:20:04.000000000 +0100
+@@ -48,6 +48,9 @@
+ #define NAND_MAX_OOBSIZE 64
+ #define NAND_MAX_PAGESIZE 2048
+
++#define NAND_PAGESIZE_512B 512
++#define NAND_PAGESIZE_2KB 2048
++
+ /*
+ * Constants for hardware specific CLE/ALE/NCE function
+ *
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/247-apf27-juju-add_NFMS_to_mx27_h.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/247-apf27-juju-add_NFMS_to_mx27_h.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/247-apf27-juju-add_NFMS_to_mx27_h.diff 2008-04-03 17:08:58 UTC (rev 791)
@@ -0,0 +1,16 @@
+--- linux/include/asm-arm/arch-mxc/mx27.h.org 2008-04-03 17:05:13.000000000 +0200
++++ linux/include/asm-arm/arch-mxc/mx27.h 2008-04-03 17:06:01.000000000 +0200
+@@ -327,6 +327,13 @@
+ #define MXC_TIMER_GPT5 5
+ #define MXC_TIMER_GPT6 6
+
++/*
++ * NFMS bit in FMCR register for pagesize of nandflash
++ */
++#define NFMS (*((volatile u32 *)IO_ADDRESS(SYSCTRL_BASE_ADDR+0x14)))
++
++#define NFMS_BIT 5
++
+ /* silicon revisions specific to i.MX27 */
+ #define CHIP_REV_1_0 0x00
+ #define CHIP_REV_2_0 0x01
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/248-apf27-juju-add_nand_desc_to_pcm038.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/248-apf27-juju-add_nand_desc_to_pcm038.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/248-apf27-juju-add_nand_desc_to_pcm038.diff 2008-04-03 17:08:58 UTC (rev 791)
@@ -0,0 +1,64 @@
+--- linux/arch/arm/mach-mx2/pcm038.c.org 2008-04-03 17:44:02.000000000 +0200
++++ linux/arch/arm/mach-mx2/pcm038.c 2008-04-03 18:33:24.000000000 +0200
+@@ -18,6 +18,7 @@
+
+ #include <linux/platform_device.h>
+ #include <linux/mtd/physmap.h>
++#include <asm/mach/flash.h>
+ #include <linux/i2c.h>
+ #include <linux/spi/spi.h>
+ #include <linux/serial.h>
+@@ -63,6 +64,45 @@
+ .resource = &pcm038_flash_resource,
+ };
+
++/*
++ * Phytec's phyCORE-i.MX27 comes with ST Micro 64MiB 1,8V NAND flash,
++ * 8 bits width
++ */
++
++static struct mtd_partition pcm038_nand_partitions[4] = {
++ {
++ .name = "IPL-SPL",
++ .offset = 0,
++ .size = 128 * 1024
++ }, {
++ .name = "nand.kernel",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 4 * 1024 * 1024
++ }, {
++ .name = "nand.rootfs",
++ .offset = MTDPART_OFS_APPEND,
++ .size = 22 * 1024 * 1024
++ }, {
++ .name = "nand.userfs",
++ .offset = MTDPART_OFS_APPEND,
++ .size = MTDPART_SIZ_FULL
++ },
++};
++
++static struct flash_platform_data pcm038_nand_data = {
++ .parts = pcm038_nand_partitions,
++ .nr_parts = ARRAY_SIZE(pcm038_nand_partitions),
++ .width = 1,
++};
++
++static struct platform_device pcm038_nand_mtd_device = {
++ .name = "mxc_nand_flash",
++ .id = 0,
++ .dev = {
++ .platform_data = &pcm038_nand_data,
++ },
++};
++
+ #ifdef CONFIG_I2C
+ static int pcm038_i2c_1_init(struct platform_device *pdev)
+ {
+@@ -301,6 +341,7 @@
+
+ static struct platform_device *platform_devices[] __initdata = {
+ &pcm038_nor_mtd_device,
++ &pcm038_nand_mtd_device,
+ };
+
+ static void __init pcm038_init(void)
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <ar...@us...> - 2008-04-03 14:08:56
|
Revision: 790
http://armadeus.svn.sourceforge.net/armadeus/?rev=790&view=rev
Author: artemys
Date: 2008-04-03 07:08:15 -0700 (Thu, 03 Apr 2008)
Log Message:
-----------
[DEMOS] Backport from apf2/ branch correction (rev [789]: Armanoid compilation)
Modified Paths:
--------------
trunk/target/demos/armanoid/Makefile
Added Paths:
-----------
trunk/target/demos/armanoid/README
Modified: trunk/target/demos/armanoid/Makefile
===================================================================
--- trunk/target/demos/armanoid/Makefile 2008-04-03 13:37:46 UTC (rev 789)
+++ trunk/target/demos/armanoid/Makefile 2008-04-03 14:08:15 UTC (rev 790)
@@ -1,16 +1,24 @@
ifeq ($(TARGET),)
-INSTALL_DIR="../../../buildroot/build_arm_nofpu/root/usr/bin/"
-CC=arm-linux-gcc
-DEFINES=TARGET
-CFLAGS:=`sh ../../../buildroot/build_arm_nofpu/SDL-1.2.11/sdl-config --cflags`
-LIBS=`sh ../../../buildroot/build_arm_nofpu/SDL-1.2.11/sdl-config --libs`
+ BUILDROOT_DIR:=../../../buildroot/
+ BUILD_DIR_EXT:=$(shell ls $(BUILDROOT_DIR) | grep -e "^build_arm*")
+ BUILD_DIR:=$(BUILDROOT_DIR)/$(BUILD_DIR_EXT)
+
+ SDL_DIR:=$(BUILD_DIR)/SDL-1.2.11/
+ STAGING_DIR:=$(BUILD_DIR)/staging_dir/
+ ROOT_DIR:=$(BUILDROOT_DIR)/project_$(BUILD_DIR_EXT)/armadeus/root/
+ INSTALL_DIR:=$(ROOT_DIR)/usr/bin/
+
+ CC:=$(STAGING_DIR)/bin/arm-linux-gcc
+ DEFINES="TARGET"
+ CFLAGS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --cflags)
+ LIBS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --libs)
else
-INSTALL_DIR="."
-CFLAGS:=`/usr/bin/sdl-config --cflags`
-LIBS=`/usr/bin/sdl-config --libs`
-CC=gcc
-DEFINES=HOST
+ INSTALL_DIR="."
+ CFLAGS=`/usr/bin/sdl-config --cflags`
+ LIBS=`/usr/bin/sdl-config --libs`
+ CC=gcc
+ DEFINES="HOST"
endif
CFLAGS+="-g"
@@ -35,11 +43,8 @@
armanoid: armanoid.o collide.o buzzer.o
$(CC) $(LIBS) -o $@ $^
-install: armanoid
- cp armanoid $INSTALL_DIR
- cp ball.bmp $INSTALL_DIR
- cp block.bmp $INSTALL_DIR
- cp bar.bmp $INSTALL_DIR
+install: armanoid ball.bmp block.bmp bar.bmp
+ cp $^ $(INSTALL_DIR)
clean:
rm -rf armanoid
Copied: trunk/target/demos/armanoid/README (from rev 789, branches/apf2/target/demos/armanoid/README)
===================================================================
--- trunk/target/demos/armanoid/README (rev 0)
+++ trunk/target/demos/armanoid/README 2008-04-03 14:08:15 UTC (rev 790)
@@ -0,0 +1,15 @@
+***********
+OOOOOOOOOO
+OOO OOOOOO
+O O
+ *
+___---____
+
+ Armanoid
+***********
+
+* ARM compiling:
+ $ make clean; make install
+* x86 compiling (SDL devt package should be installed on your system)
+ $ make clean; make TARGET=x86
+
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <ar...@us...> - 2008-04-03 13:38:09
|
Revision: 789
http://armadeus.svn.sourceforge.net/armadeus/?rev=789&view=rev
Author: artemys
Date: 2008-04-03 06:37:46 -0700 (Thu, 03 Apr 2008)
Log Message:
-----------
[DEMOS] Makes Armanoid compile again
Modified Paths:
--------------
branches/apf2/target/demos/armanoid/Makefile
Added Paths:
-----------
branches/apf2/target/demos/armanoid/README
Modified: branches/apf2/target/demos/armanoid/Makefile
===================================================================
--- branches/apf2/target/demos/armanoid/Makefile 2008-04-03 06:43:24 UTC (rev 788)
+++ branches/apf2/target/demos/armanoid/Makefile 2008-04-03 13:37:46 UTC (rev 789)
@@ -1,16 +1,24 @@
ifeq ($(TARGET),)
-INSTALL_DIR="../../../buildroot/build_arm_nofpu/root/usr/bin/"
-CC=arm-linux-gcc
-DEFINES=TARGET
-CFLAGS:=`sh ../../../buildroot/build_arm_nofpu/SDL-1.2.11/sdl-config --cflags`
-LIBS=`sh ../../../buildroot/build_arm_nofpu/SDL-1.2.11/sdl-config --libs`
+ BUILDROOT_DIR:=../../../buildroot/
+ BUILD_DIR_EXT:=$(shell ls $(BUILDROOT_DIR) | grep -e "^build_arm*")
+ BUILD_DIR:=$(BUILDROOT_DIR)/$(BUILD_DIR_EXT)
+
+ SDL_DIR:=$(BUILD_DIR)/SDL-1.2.11/
+ STAGING_DIR:=$(BUILD_DIR)/staging_dir/
+ ROOT_DIR:=$(BUILDROOT_DIR)/project_$(BUILD_DIR_EXT)/armadeus/root/
+ INSTALL_DIR:=$(ROOT_DIR)/usr/bin/
+
+ CC:=$(STAGING_DIR)/bin/arm-linux-gcc
+ DEFINES="TARGET"
+ CFLAGS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --cflags)
+ LIBS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --libs)
else
-INSTALL_DIR="."
-CFLAGS:=`/usr/bin/sdl-config --cflags`
-LIBS=`/usr/bin/sdl-config --libs`
-CC=gcc
-DEFINES=HOST
+ INSTALL_DIR="."
+ CFLAGS=`/usr/bin/sdl-config --cflags`
+ LIBS=`/usr/bin/sdl-config --libs`
+ CC=gcc
+ DEFINES="HOST"
endif
CFLAGS+="-g"
@@ -35,11 +43,8 @@
armanoid: armanoid.o collide.o buzzer.o
$(CC) $(LIBS) -o $@ $^
-install: armanoid
- cp armanoid $INSTALL_DIR
- cp ball.bmp $INSTALL_DIR
- cp block.bmp $INSTALL_DIR
- cp bar.bmp $INSTALL_DIR
+install: armanoid ball.bmp block.bmp bar.bmp
+ cp $^ $(INSTALL_DIR)
clean:
rm -rf armanoid
Added: branches/apf2/target/demos/armanoid/README
===================================================================
--- branches/apf2/target/demos/armanoid/README (rev 0)
+++ branches/apf2/target/demos/armanoid/README 2008-04-03 13:37:46 UTC (rev 789)
@@ -0,0 +1,15 @@
+***********
+OOOOOOOOOO
+OOO OOOOOO
+O O
+ *
+___---____
+
+ Armanoid
+***********
+
+* ARM compiling:
+ $ make clean; make install
+* x86 compiling (SDL devt package should be installed on your system)
+ $ make clean; make TARGET=x86
+
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <ar...@us...> - 2008-04-03 06:43:18
|
Revision: 788
http://armadeus.svn.sourceforge.net/armadeus/?rev=788&view=rev
Author: artemys
Date: 2008-04-02 23:43:24 -0700 (Wed, 02 Apr 2008)
Log Message:
-----------
[LINUX] Add i.MX27 Framebuffer & I2C/SPI drivers (I2C/SPI not functionnal yet)
Modified Paths:
--------------
branches/apf2/buildroot/target/device/armadeus/apf27/linux-2.6.25-rc7.config
Added Paths:
-----------
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/230-apf27-pengu-mx2_devices_full.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/231-apf27-pengu-mxc_i2c_driver.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/232-apf27-pengu-imx27_spi_driver.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/233-apf27-pengu-mx2_framebuffer_beta.diff
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/234-apf27-pengu-mc13783_touch.not_used
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/235-apf27-pengu-make_pcm038_full_featured.diff
Modified: branches/apf2/buildroot/target/device/armadeus/apf27/linux-2.6.25-rc7.config
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/linux-2.6.25-rc7.config 2008-04-02 15:08:36 UTC (rev 787)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/linux-2.6.25-rc7.config 2008-04-03 06:43:24 UTC (rev 788)
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.25-rc7
-# Tue Apr 1 17:39:25 2008
+# Wed Apr 2 22:41:47 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -430,8 +430,6 @@
#
# Self-contained MTD device drivers
#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
@@ -484,7 +482,6 @@
# CONFIG_AX88796 is not set
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
-# CONFIG_ENC28J60 is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -530,7 +527,6 @@
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
@@ -577,59 +573,13 @@
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_CHARDEV is not set
+# CONFIG_I2C is not set
#
-# I2C Algorithms
-#
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
-
-#
-# I2C Hardware Bus support
-#
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_EEPROM is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-
-#
# SPI support
#
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-CONFIG_SPI_BITBANG=y
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_AT25 is not set
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
@@ -659,8 +609,6 @@
# CONFIG_VIDEO_ADV_DEBUG is not set
CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
# CONFIG_RADIO_ADAPTERS is not set
# CONFIG_DVB_CORE is not set
# CONFIG_DAB is not set
@@ -673,9 +621,9 @@
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
-# CONFIG_FB_CFB_FILLRECT is not set
-# CONFIG_FB_CFB_COPYAREA is not set
-# CONFIG_FB_CFB_IMAGEBLIT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
@@ -691,6 +639,13 @@
#
# Frame buffer hardware drivers
#
+CONFIG_FB_MXC=y
+
+#
+# MXC framebuffer options
+#
+CONFIG_FB_MXC_SYNC_PANEL=y
+# CONFIG_FB_MXC_OVERLAY is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
@@ -719,7 +674,10 @@
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
-# CONFIG_LOGO is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
#
# Sound
@@ -745,26 +703,8 @@
# CONFIG_RTC_DRV_TEST is not set
#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-CONFIG_RTC_DRV_PCF8563=y
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-
-#
# SPI RTC drivers
#
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
#
# Platform RTC drivers
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/230-apf27-pengu-mx2_devices_full.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/230-apf27-pengu-mx2_devices_full.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/230-apf27-pengu-mx2_devices_full.diff 2008-04-03 06:43:24 UTC (rev 788)
@@ -0,0 +1,764 @@
+Subject: [@num@/@total@] i.MX2 family: Devices support
+From: Juergen Beisert <j.b...@pe...>
+
+This patch expands the known devices on i.MX21/i.MX27 procesors.
+
+New devices are:
+
+ - spi
+ - i2c
+ - watchdog
+ - framebuffer
+
+Note: This is for development. Not for mainline yet.
+
+Signed-off-by: Juergen Beisert <j.b...@pe...>
+
+---
+
+ arch/arm/mach-mx2/devices.c | 316 +++++++++++++++++++++++++++++++-
+ arch/arm/mach-mx2/devices.h | 14 +
+ include/asm-arm/arch-mxc/imx_fb.h | 81 ++++++++
+ include/asm-arm/arch-mxc/imx_i2c.h | 83 ++++++++
+ include/asm-arm/arch-mxc/imx_spi.h | 145 ++++++++++++++
+ include/asm-arm/arch-mxc/imx_watchdog.h | 44 ++++
+ 6 files changed, 677 insertions(+), 6 deletions(-)
+
+Index: include/asm-arm/arch-mxc/imx_watchdog.h
+===================================================================
+--- /dev/null
++++ linux/include/asm-arm/arch-mxc/imx_watchdog.h
+@@ -0,0 +1,44 @@
++/*
++ * imx_watchdog.h
++ *
++ * Copyright (C) 2008 Juergen Beisert (ke...@pe...)
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++/*
++ * Watchdog register definition for:
++ * - i.MX21
++ * - i.MX27
++ */
++
++/* for direct access, note: All registers are 16 bit wide */
++#define IMX_WCR_REG(x) (*(volatile unsigned short __force*)(x))
++#define IMX_WSR_REG(x) (*(volatile unsigned short __force*)((x) + 2))
++#define IMX_WRSR_REG(x) (*(volatile unsigned short __force*)((x) + 4))
++
++/* for drivers usage */
++#define IMX_WCR 0
++#define IMX_WSR 2
++#define IMX_WRSR 4
++
++/* Bit definitions */
++#define IMX_WCR_WT_SHIFT 8
++#define IMX_WCR_WT_MASK 0xFF00
++#define IMX_WCR_WDA (1<<5)
++#define IMX_WCR_SRS (1<<4)
++#define IMX_WCR_WRE (1<<3)
++#define IMX_WCR_WDE (1<<2)
++#define IMX_WCR_WDBG (1<<1)
++#define IMX_WCR_WDZST (1<<0)
+Index: include/asm-arm/arch-mxc/imx_i2c.h
+===================================================================
+--- /dev/null
++++ linux/include/asm-arm/arch-mxc/imx_i2c.h
+@@ -0,0 +1,83 @@
++/*
++ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2008 Juergen Beisert, ke...@pe...
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++#ifndef __ASM_ARCH_MXC_I2C_H__
++#define __ASM_ARCH_MXC_I2C_H__
++
++struct imx_i2c_platform_data {
++ u32 i2c_clk;
++ int (*init)(struct platform_device *pdev);
++ int (*exit)(struct platform_device *pdev);
++};
++
++int mxc_init_i2c(int id, struct imx_i2c_platform_data *data);
++
++/*
++ * This file contains the I2C chip level configuration details.
++ *
++ * It also contains the API function that other drivers can use to read/write
++ * to the I2C device registers.
++ */
++
++/*
++ * This defines the string used to identify MXC I2C Bus drivers
++ */
++#define MXC_ADAPTER_NAME "MXC I2C Adapter"
++
++#define MXC_I2C_FLAG_READ 0x01 /* if set, is read; else is write */
++#define MXC_I2C_FLAG_POLLING 0x02 /* if set, is polling mode; else is interrupt mode */
++
++int mxc_i2c_read(int bus_id, unsigned int addr, char *reg, int reg_len,
++ char *buf, int num);
++
++int mxc_i2c_write(int bus_id, unsigned int addr, char *reg, int reg_len,
++ char *buf, int num);
++
++int mxc_i2c_polling_read(int bus_id, unsigned int addr, char *reg, int reg_len,
++ char *buf, int num);
++
++int mxc_i2c_polling_write(int bus_id, unsigned int addr, char *reg, int reg_len,
++ char *buf, int num);
++
++/* FIXME: This should be in a generic register file */
++
++/* Address offsets of the I2C registers */
++#define MXC_IADR 0x00 /* Address Register */
++#define MXC_IFDR 0x04 /* Freq div register */
++#define MXC_I2CR 0x08 /* Control regsiter */
++#define MXC_I2SR 0x0C /* Status register */
++#define MXC_I2DR 0x10 /* Data I/O register */
++
++/* Bit definitions of I2CR */
++#define MXC_I2CR_IEN 0x0080
++#define MXC_I2CR_IIEN 0x0040
++#define MXC_I2CR_MSTA 0x0020
++#define MXC_I2CR_MTX 0x0010
++#define MXC_I2CR_TXAK 0x0008
++#define MXC_I2CR_RSTA 0x0004
++
++/* Bit definitions of I2SR */
++#define MXC_I2SR_ICF 0x0080
++#define MXC_I2SR_IAAS 0x0040
++#define MXC_I2SR_IBB 0x0020
++#define MXC_I2SR_IAL 0x0010
++#define MXC_I2SR_SRW 0x0004
++#define MXC_I2SR_IIF 0x0002
++#define MXC_I2SR_RXAK 0x0001
++
++#endif /* __ASM_ARCH_MXC_I2C_H__ */
+Index: include/asm-arm/arch-mxc/imx_spi.h
+===================================================================
+--- /dev/null
++++ linux/include/asm-arm/arch-mxc/imx_spi.h
+@@ -0,0 +1,145 @@
++/*
++ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2008 Juergen Beisert, ke...@pe...
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++#ifndef __MXC_SPI_MX27_H__
++#define __MXC_SPI_MX27_H__
++
++#include <asm/hardware.h>
++#include <asm/mach-types.h>
++
++/*
++ * This structure is used to define the SPI master controller's platform
++ * data. It includes the SPI bus number and the maximum number of
++ * slaves/chips it supports.
++ */
++struct mxc_spi_master {
++ unsigned int bus_num; /* bus number. */
++ unsigned int maxchipselect; /* number of chip selects. */
++ unsigned int spi_version; /* CSPI Hardware Version. */
++
++ int (*init)(struct platform_device *pdev);
++ int (*exit)(struct platform_device *pdev);
++};
++
++int mxc_init_spi(int id, struct mxc_spi_master *master);
++
++#define MXC_CSPIRXDATA 0x00
++#define MXC_CSPITXDATA 0x04
++#define MXC_CSPICTRL 0x08
++#define MXC_CSPIINT 0x0C
++#define MXC_CSPIDMA 0x18
++#define MXC_CSPISTAT 0x0C
++#define MXC_CSPIPERIOD 0x14
++#define MXC_CSPITEST 0x10
++#define MXC_CSPIRESET 0x1C
++
++#define MXC_CSPICTRL_ENABLE (1 << 10)
++#define MXC_CSPICTRL_DISABLE 0x0
++#define MXC_CSPICTRL_MASTER (1 << 11)
++#define MXC_CSPICTRL_SLAVE 0x0
++#define MXC_CSPICTRL_XCH (1 << 9)
++#define MXC_CSPICTRL_LOWPOL (1 << 5)
++#define MXC_CSPICTRL_HIGHPOL 0x0
++#define MXC_CSPICTRL_PHA (1 << 6)
++#define MXC_CSPICTRL_NOPHA 0x0
++#define MXC_CSPICTRL_SSCTL (1 << 7)
++#define MXC_CSPICTRL_HIGHSSPOL (1 << 8)
++#define MXC_CSPICTRL_LOWSSPOL 0x0
++#define MXC_CSPICTRL_CSMASK 0x3
++#define MXC_CSPICTRL_MAXDATRATE 0x10
++#define MXC_CSPICTRL_DATAMASK 0x1F
++#define MXC_CSPICTRL_DATASHIFT 14
++/* This adjustment in the shift is valid only for even states only(i.e. divide
++ ratio of 2). SDHC_SPIEN is not set by default. If SDHC_SPIEN bit is set in
++ MXC_CSPICTRL, then divide ratio is 3, this shift adjustment is invalid. */
++#define MXC_CSPICTRL_ADJUST_SHIFT(x) ((x) = ((x) - 1) * 2)
++
++#define MXC_CSPICTRL_CSSHIFT_0_7 12
++#define MXC_CSPICTRL_BCSHIFT_0_7 20
++#define MXC_CSPICTRL_BCMASK_0_7 0xFFF
++#define MXC_CSPICTRL_DRCTRLSHIFT_0_7 8
++
++#define MXC_CSPICTRL_CSSHIFT_0_5 12
++#define MXC_CSPICTRL_BCSHIFT_0_5 20
++#define MXC_CSPICTRL_BCMASK_0_5 0xFFF
++#define MXC_CSPICTRL_DRCTRLSHIFT_0_5 8
++
++#define MXC_CSPICTRL_CSSHIFT_0_4 24
++#define MXC_CSPICTRL_BCSHIFT_0_4 8
++#define MXC_CSPICTRL_BCMASK_0_4 0x1F
++#define MXC_CSPICTRL_DRCTRLSHIFT_0_4 20
++
++#define MXC_CSPICTRL_CSSHIFT_0_0 19
++#define MXC_CSPICTRL_BCSHIFT_0_0 0
++#define MXC_CSPICTRL_BCMASK_0_0 0x1F
++#define MXC_CSPICTRL_DRCTRLSHIFT_0_0 12
++
++#define MXC_CSPIINT_IRQSHIFT_0_7 8
++#define MXC_CSPIINT_IRQSHIFT_0_5 9
++#define MXC_CSPIINT_IRQSHIFT_0_4 9
++#define MXC_CSPIINT_IRQSHIFT_0_0 18
++#define MXC_CSPIINT_TEEN (1 << 9)
++#define MXC_CSPIINT_THEN (1 << 10)
++#define MXC_CSPIINT_TFEN (1 << 11)
++#define MXC_CSPIINT_RREN (1 << 13)
++#define MXC_CSPIINT_RHEN (1 << 14)
++#define MXC_CSPIINT_RFEN (1 << 15)
++#define MXC_CSPIINT_ROEN (1 << 16)
++#define MXC_CSPIINT_TCEN_0_7 (1 << 7)
++#define MXC_CSPIINT_TCEN_0_5 (1 << 8)
++#define MXC_CSPIINT_TCEN_0_4 (1 << 8)
++#define MXC_CSPIINT_TCEN_0_0 (1 << 12)
++#define MXC_CSPIINT_BOEN_0_7 0
++#define MXC_CSPIINT_BOEN_0_5 (1 << 7)
++#define MXC_CSPIINT_BOEN_0_4 (1 << 7)
++#define MXC_CSPIINT_BOEN_0_0 (1 << 17)
++
++#define MXC_CSPISTAT_TE (1 << 0)
++#define MXC_CSPISTAT_TH (1 << 1)
++#define MXC_CSPISTAT_TF (1 << 2)
++#define MXC_CSPISTAT_RR (1 << 3)
++#define MXC_CSPISTAT_RH (1 << 4)
++#define MXC_CSPISTAT_RF (1 << 5)
++#define MXC_CSPISTAT_RO (1 << 6)
++#define MXC_CSPISTAT_TC_0_7 (1 << 7)
++#define MXC_CSPISTAT_TC_0_5 (1 << 8)
++#define MXC_CSPISTAT_TC_0_4 (1 << 8)
++#define MXC_CSPISTAT_TC_0_0 (1 << 3)
++#define MXC_CSPISTAT_BO_0_7 0
++#define MXC_CSPISTAT_BO_0_5 (1 << 7)
++#define MXC_CSPISTAT_BO_0_4 (1 << 7)
++#define MXC_CSPISTAT_BO_0_0 (1 << 8)
++
++#define MXC_CSPIPERIOD_32KHZ (1 << 15)
++
++#define MXC_CSPITEST_LBC (1 << 14)
++
++/*
++ * This structure contains information that differs with
++ * SPI master controller hardware version
++ */
++struct mxc_spi_unique_def {
++ unsigned int intr_bit_shift; /* Width of valid bits in MXC_CSPIINT. */
++ unsigned int cs_shift; /* Chip Select shift. */
++ unsigned int bc_shift; /* Bit count shift. */
++ unsigned int bc_mask; /* Bit count mask. */
++ unsigned int drctrl_shift; /* Data Control shift. */
++ unsigned int xfer_complete; /* Transfer Complete shift. */
++ unsigned int bc_overflow; /* Bit counnter overflow shift. */
++};
++#endif //__MXC_SPI_MX27_H__
+Index: arch/arm/mach-mx2/devices.c
+===================================================================
+--- linux/arch/arm/mach-mx2/devices.c.orig
++++ linux/arch/arm/mach-mx2/devices.c
+@@ -29,9 +29,149 @@
+ #include <linux/kernel.h>
+ #include <linux/init.h>
+ #include <linux/platform_device.h>
++#include <asm/arch/imx_spi.h>
++#include <asm/arch/imx_i2c.h>
++#include <asm/arch/imx_fb.h>
++#include <linux/spi/spi.h>
+
+ #include <asm/hardware.h>
+
++struct platform_device mxc_w1_device = {
++ .name = "mxc_w1",
++ .id = 0
++};
++
++struct platform_device mxc_rtc_device = {
++ .name = "mxc_rtc",
++ .id = 0,
++};
++
++#if 0
++/* FIXME: declaration of struct mxc_mmc_platform_data missing in patch */
++/* MMC device data */
++extern unsigned int sdhc_get_card_det_status(struct device *dev);
++extern int sdhc_init_card_det(int id);
++
++struct mxc_mmc_platform_data mmc_data = {
++ .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30,
++ .min_clk = 150000,
++ .max_clk = 25000000,
++ .card_inserted_state = 0,
++ .status = sdhc_get_card_det_status,
++};
++
++/*
++ * Resource definition for the SDHC1
++ */
++static struct resource mxc_sdhc1_resources[] = {
++ [0] = {
++ .start = SDHC1_BASE_ADDR,
++ .end = SDHC1_BASE_ADDR + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = INT_SDHC1,
++ .end = INT_SDHC1,
++ .flags = IORESOURCE_IRQ,
++ },
++ [2] = {
++ .start = 0,
++ .end = 0,
++ .flags = IORESOURCE_IRQ,
++ },
++ [3] = {
++ .start = MXC_SDIO1_CARD_IRQ,
++ .end = MXC_SDIO1_CARD_IRQ,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++/* Device Definition for MXC SDHC1 */
++struct platform_device mxc_sdhc1_device = {
++ .name = "mxcmci",
++ .id = 0,
++ .dev = {
++ .platform_data = &mmc_data,
++ },
++ .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
++ .resource = mxc_sdhc1_resources,
++};
++
++/*
++ * Resource definition for the SDHC2
++ */
++static struct resource mxc_sdhc2_resources[] = {
++ [0] = {
++ .start = SDHC2_BASE_ADDR,
++ .end = SDHC2_BASE_ADDR + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = INT_SDHC2,
++ .end = INT_SDHC2,
++ .flags = IORESOURCE_IRQ,
++ },
++ [2] = {
++ .start = 0,
++ .end = 0,
++ .flags = IORESOURCE_IRQ,
++ },
++ [3] = {
++ .start = MXC_SDIO2_CARD_IRQ,
++ .end = MXC_SDIO2_CARD_IRQ,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++/* Device Definition for MXC SDHC2 */
++struct platform_device mxc_sdhc2_device = {
++ .name = "mxcmci",
++ .id = 1,
++ .dev = {
++ .platform_data = &mmc_data,
++ },
++ .num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
++ .resource = mxc_sdhc2_resources,
++};
++
++/*
++ * Resource definition for the SDHC3
++ */
++static struct resource mxc_sdhc3_resources[] = {
++ [0] = {
++ .start = SDHC3_BASE_ADDR,
++ .end = SDHC3_BASE_ADDR + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = INT_SDHC3,
++ .end = INT_SDHC3,
++ .flags = IORESOURCE_IRQ,
++ },
++ [2] = {
++ .start = 0,
++ .end = 0,
++ .flags = IORESOURCE_IRQ,
++ },
++ [3] = {
++ .start = MXC_SDIO3_CARD_IRQ,
++ .end = MXC_SDIO3_CARD_IRQ,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++/* Device Definition for MXC SDHC3 */
++struct platform_device mxc_sdhc3_device = {
++ .name = "mxcmci",
++ .id = 2,
++ .dev = {
++ .platform_data = &mmc_data,
++ },
++ .num_resources = ARRAY_SIZE(mxc_sdhc3_resources),
++ .resource = mxc_sdhc3_resources,
++};
++#endif
++
+ /*
+ * Resource definition for the MXC IrDA
+ */
+@@ -56,6 +196,85 @@
+ .resource = mxc_irda_resources,
+ };
+
++/* Platform Data for MXC VPU */
++struct platform_device mxc_vpu_device = {
++ .name = "mxc_vpu",
++ .id = 0,
++};
++
++/*
++ * SPI master controller
++ *
++ * - i.MX1: 2 channel (slighly different register setting)
++ * - i.MX21: 2 channel
++ * - i.MX27: 3 channel
++ */
++static struct resource imx_spi_0_resources[] = {
++ [0] = {
++ .start = CSPI1_BASE_ADDR,
++ .end = CSPI1_BASE_ADDR + 0x1F,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = INT_CSPI1,
++ .end = INT_CSPI1,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct resource imx_spi_1_resources[] = {
++ [0] = {
++ .start = CSPI2_BASE_ADDR,
++ .end = CSPI2_BASE_ADDR + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = INT_CSPI2,
++ .end = INT_CSPI2,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct resource imx_spi_2_resources[] = {
++ [0] = {
++ .start = CSPI3_BASE_ADDR,
++ .end = CSPI3_BASE_ADDR + SZ_4K - 1,
++ .flags = IORESOURCE_MEM,
++ },
++ [1] = {
++ .start = INT_CSPI3,
++ .end = INT_CSPI3,
++ .flags = IORESOURCE_IRQ,
++ },
++};
++
++static struct platform_device imx_spi_devices[] = {
++ {
++ .name = "mxc_spi",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(imx_spi_0_resources),
++ .resource = imx_spi_0_resources,
++ }, {
++ .name = "mxc_spi",
++ .id = 1,
++ .num_resources = ARRAY_SIZE(imx_spi_1_resources),
++ .resource = imx_spi_1_resources,
++ }
++};
++
++int mxc_init_spi(int id, struct mxc_spi_master *master)
++{
++ imx_spi_devices[id].dev.platform_data = master;
++ return platform_device_register(&imx_spi_devices[id]);
++}
++
++struct platform_device imx_spi_2_device = {
++ .name = "mxc_spi",
++ .id = 2,
++ .num_resources = ARRAY_SIZE(imx_spi_2_resources),
++ .resource = imx_spi_2_resources,
++};
++
+ /*
+ * General Purpose Timer
+ * - i.MX1: 2 timer (slighly different register handling)
+@@ -167,6 +386,59 @@
+ };
+ #endif
+
++/* I2C channel #1 */
++static struct resource imx_i2c_1_resources[] = {
++ [0] = {
++ .start = I2C_BASE_ADDR,
++ .end = I2C_BASE_ADDR + 0x0F,
++ .flags = IORESOURCE_MEM
++ },
++ [1] = {
++ .start = INT_I2C,
++ .end = INT_I2C,
++ .flags = IORESOURCE_IRQ
++ }
++};
++
++#ifdef CONFIG_MACH_MX27
++static struct resource imx_i2c_2_resources[] = {
++ [0] = {
++ .start = I2C2_BASE_ADDR,
++ .end = I2C2_BASE_ADDR + 0x0F,
++ .flags = IORESOURCE_MEM
++ },
++ [1] = {
++ .start = INT_I2C2,
++ .end = INT_I2C2,
++ .flags = IORESOURCE_IRQ
++ }
++};
++
++#endif
++
++struct platform_device imx_i2c_devices[] = {
++ {
++ .name = "imx_i2c",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(imx_i2c_1_resources),
++ .resource = imx_i2c_1_resources
++ },
++#ifdef CONFIG_MACH_MX27
++ {
++ .name = "imx_i2c",
++ .id = 1,
++ .num_resources = ARRAY_SIZE(imx_i2c_2_resources),
++ .resource = imx_i2c_2_resources
++ }
++#endif
++};
++
++int mxc_init_i2c(int id, struct imx_i2c_platform_data *data)
++{
++ imx_i2c_devices[id].dev.platform_data = data;
++ return platform_device_register(&imx_i2c_devices[id]);
++}
++
+ /*
+ * Watchdog:
+ * - i.MX1
+@@ -187,3 +459,33 @@
+ .num_resources = ARRAY_SIZE(mxc_wdt_resources),
+ .resource = mxc_wdt_resources,
+ };
++static struct resource mxc_fb[] = {
++ {
++ .start = LCDC_BASE_ADDR,
++ .end = LCDC_BASE_ADDR + 0xFFF,
++ .flags = IORESOURCE_MEM,
++ },
++ {
++ .start = INT_LCDC,
++ .end = INT_LCDC,
++ .flags = IORESOURCE_IRQ,
++ }
++};
++
++/* mxc lcd driver */
++struct platform_device mxc_fb_device = {
++ .name = "mxc_sdc_fb",
++ .id = 0,
++ .num_resources = ARRAY_SIZE(mxc_fb),
++ .resource = mxc_fb,
++ .dev = {
++ .platform_data = NULL, /* no default video mode */
++ .coherent_dma_mask = 0xFFFFFFFF,
++ },
++};
++
++int mxc_init_fb(struct mxc_fb_platform_data *pdata)
++{
++ mxc_fb_device.dev.platform_data = pdata;
++ return platform_device_register(&mxc_fb_device);
++}
+Index: arch/arm/mach-mx2/devices.h
+===================================================================
+--- linux/arch/arm/mach-mx2/devices.h.orig
++++ linux/arch/arm/mach-mx2/devices.h
+@@ -15,7 +15,14 @@
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
++extern struct platform_device mxc_sdhc1_device;
++extern struct platform_device mxc_sdhc2_device;
++extern struct platform_device mxc_sdhc3_device;
+ extern struct platform_device mxc_irda_device;
++extern struct platform_device mxc_vpu_device;
++extern struct platform_device imx_spi_0_device;
++extern struct platform_device imx_spi_1_device;
++extern struct platform_device imx_spi_2_device;
+ extern struct platform_device mxc_gpt0;
+ extern struct platform_device mxc_gpt1;
+ extern struct platform_device mxc_gpt2;
+@@ -24,4 +31,11 @@ extern struct platform_device mxc_gpt3;
+ extern struct platform_device mxc_gpt4;
+ extern struct platform_device mxc_gpt5;
+ #endif
++extern struct platform_device imx_i2c_1_device;
++#ifdef CONFIG_MACH_MX27
++extern struct platform_device imx_i2c_2_device;
++#endif
+ extern struct platform_device mxc_wdt;
++extern struct platform_device mxc_fb_device;
++
++
+Index: include/asm-arm/arch-mxc/imx_fb.h
+===================================================================
+--- /dev/null
++++ linux/include/asm-arm/arch-mxc/imx_fb.h
+@@ -0,0 +1,81 @@
++/*
++ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2008 Juergen Beisert, ke...@pe...
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++#ifndef __ASM_ARCH_MXCFB_H__
++#define __ASM_ARCH_MXCFB_H__
++
++#include <linux/fb.h>
++#include <linux/platform_device.h>
++
++struct mxc_fb_platform_data {
++ char *mode;
++
++ int (*init)(struct platform_device *pdev);
++ int (*exit)(struct platform_device *pdev);
++
++ int (*power_lcd)(struct platform_device *pdev, int on);
++};
++
++
++int mxc_init_fb(struct mxc_fb_platform_data *pdata);
++
++#define FB_SYNC_OE_ACT_HIGH 0x80000000
++#define FB_SYNC_CLK_INVERT 0x40000000
++#define FB_SYNC_DATA_INVERT 0x20000000
++#define FB_SYNC_CLK_IDLE_EN 0x10000000
++#define FB_SYNC_SHARP_MODE 0x08000000
++#define FB_SYNC_SWAP_RGB 0x04000000
++
++struct mxcfb_gbl_alpha {
++ int enable;
++ int alpha;
++};
++
++struct mxcfb_color_key {
++ int enable;
++ __u32 color_key;
++};
++
++#define MXCFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t)
++#define MXCFB_SET_GBL_ALPHA _IOW('F', 0x21, struct mxcfb_gbl_alpha)
++#define MXCFB_SET_CLR_KEY _IOW('F', 0x22, struct mxcfb_color_key)
++#define MXCFB_SET_BRIGHTNESS _IOW('F', 0x23, __u8)
++
++#ifdef __KERNEL__
++
++extern const struct fb_videomode mxcfb_modedb[];
++extern int mxcfb_modedb_sz;
++
++enum {
++ MXCFB_REFRESH_OFF,
++ MXCFB_REFRESH_AUTO,
++ MXCFB_REFRESH_PARTIAL,
++};
++
++struct mxcfb_rect {
++ u32 top;
++ u32 left;
++ u32 width;
++ u32 height;
++};
++
++int mxcfb_set_refresh_mode(struct fb_info *fbi, int mode,
++ struct mxcfb_rect *update_region);
++
++#endif /* __KERNEL__ */
++#endif
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/231-apf27-pengu-mxc_i2c_driver.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/231-apf27-pengu-mxc_i2c_driver.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/231-apf27-pengu-mxc_i2c_driver.diff 2008-04-03 06:43:24 UTC (rev 788)
@@ -0,0 +1,712 @@
+Subject: [@num@/@total@] i.MXC family: I2C master driver
+From: Juergen Beisert <j.b...@pe...>
+
+This patch adds I2C master driver for i.MX family.
+
+Signed-off-by: Juergen Beisert <j.b...@pe...>
+Signed-off-by: N.N. (FIXME: get a sign from freescale)
+
+---
+
+ drivers/i2c/busses/Kconfig | 10
+ drivers/i2c/busses/Makefile | 1
+ drivers/i2c/busses/imx_i2c.c | 659 +++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 670 insertions(+)
+
+Index: drivers/i2c/busses/Kconfig
+===================================================================
+--- linux/drivers/i2c/busses/Kconfig.orig
++++ linux/drivers/i2c/busses/Kconfig
+@@ -302,6 +302,16 @@ config I2C_MPC
+ This driver can also be built as a module. If so, the module
+ will be called i2c-mpc.
+
++config I2C_MXC
++ tristate "MXC I2C support"
++ depends on I2C && ARCH_MXC
++ help
++ If you say yes to this option, support will be included for Freescale
++ i.MX2 family of processors (like i.MX21 and i.MX27).
++
++ This driver can also be built as a module. If so, the module
++ will be called imx_i2c.
++
+ config I2C_NFORCE2
+ tristate "Nvidia nForce2, nForce3 and nForce4"
+ depends on PCI
+Index: drivers/i2c/busses/Makefile
+===================================================================
+--- linux/drivers/i2c/busses/Makefile.orig
++++ linux/drivers/i2c/busses/Makefile
+@@ -52,6 +52,7 @@ obj-$(CONFIG_I2C_VIAPRO) += i2c-viapro.o
+ obj-$(CONFIG_I2C_VOODOO3) += i2c-voodoo3.o
+ obj-$(CONFIG_SCx200_ACB) += scx200_acb.o
+ obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o
++obj-$(CONFIG_I2C_MXC) += imx_i2c.o
+
+ ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
+ EXTRA_CFLAGS += -DDEBUG
+Index: drivers/i2c/busses/imx_i2c.c
+===================================================================
+--- /dev/null
++++ linux/drivers/i2c/busses/imx_i2c.c
+@@ -0,0 +1,659 @@
++/*
++ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright 2008 Juergen Beisert, ke...@pe...
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++/*
++ * Driver for the Freescale Semiconductor MXC I2C buses.
++ * Based on i2c driver algorithm for PCF8584 adapters
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++#include <linux/clk.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/imx_i2c.h>
++
++#define DRV_NAME "imx_i2c"
++
++typedef struct {
++ struct i2c_adapter adap;
++ wait_queue_head_t wq;
++ unsigned long membase; /* FIXME iomem? */
++ int irq;
++ unsigned int clkdiv;
++ struct clk *clk;
++ bool low_power;
++ struct imx_i2c_platform_data *pdata;
++} imx_i2c_device;
++
++/*
++ * HACK: Why is it not channel specific?
++ * Boolean to indicate if data was transferred
++ */
++static bool transfer_done = false;
++
++/*
++ * HACK: Why is it not channel specific?
++ * Boolean to indicate if we received an ACK for the data transmitted
++ */
++static bool tx_success = false;
++
++struct clk_div_table {
++ int reg_value;
++ int div;
++};
++
++static const struct clk_div_table i2c_clk_table[] = {
++ {0x20, 22}, {0x21, 24}, {0x22, 26}, {0x23, 28},
++ {0, 30}, {1, 32}, {0x24, 32}, {2, 36},
++ {0x25, 36}, {0x26, 40}, {3, 42}, {0x27, 44},
++ {4, 48}, {0x28, 48}, {5, 52}, {0x29, 56},
++ {6, 60}, {0x2A, 64}, {7, 72}, {0x2B, 72},
++ {8, 80}, {0x2C, 80}, {9, 88}, {0x2D, 96},
++ {0xA, 104}, {0x2E, 112}, {0xB, 128}, {0x2F, 128},
++ {0xC, 144}, {0xD, 160}, {0x30, 160}, {0xE, 192},
++ {0x31, 192}, {0x32, 224}, {0xF, 240}, {0x33, 256},
++ {0x10, 288}, {0x11, 320}, {0x34, 320}, {0x12, 384},
++ {0x35, 384}, {0x36, 448}, {0x13, 480}, {0x37, 512},
++ {0x14, 576}, {0x15, 640}, {0x38, 640}, {0x16, 768},
++ {0x39, 768}, {0x3A, 896}, {0x17, 960}, {0x3B, 1024},
++ {0x18, 1152}, {0x19, 1280}, {0x3C, 1280}, {0x1A, 1536},
++ {0x3D, 1536}, {0x3E, 1792}, {0x1B, 1920}, {0x3F, 2048},
++ {0x1C, 2304}, {0x1D, 2560}, {0x1E, 3072}, {0x1F, 3840},
++ {0, 0}
++};
++
++/* Transmit a STOP signal to the slave device */
++static void imx_i2c_stop(imx_i2c_device * dev)
++{
++ unsigned int cr;
++ int retry = 16;
++
++ cr = readw(dev->membase + MXC_I2CR);
++ cr &= ~(MXC_I2CR_MSTA | MXC_I2CR_MTX);
++ writew(cr, dev->membase + MXC_I2CR);
++
++ /*
++ * Make sure STOP meets setup requirement.
++ */
++ for (;;) {
++ unsigned int sr = readw(dev->membase + MXC_I2SR);
++ if ((sr & MXC_I2SR_IBB) == 0) break;
++ if (retry-- <= 0) {
++ printk(KERN_DEBUG "Bus busy\n");
++ break;
++ }
++ udelay(3);
++ }
++}
++
++/*
++ * Wait for the transmission of the data byte to complete. This function waits
++ * till we get a signal from the interrupt service routine indicating completion
++ * of the address cycle or we time out.
++ * The function returns 0 on success or -1 if an ack was not received
++ */
++static int imx_i2c_wait_for_tc(imx_i2c_device * dev, int trans_flag)
++{
++ int retry = 16;
++
++ while (retry-- && !transfer_done) {
++ wait_event_interruptible_timeout(dev->wq,
++ transfer_done,
++ dev->adap.timeout);
++ }
++ transfer_done = false;
++
++ if (retry <= 0) {
++ /* Unable to send data */
++ printk(KERN_DEBUG "Data not transmitted\n");
++ return -1;
++ } else if (!(trans_flag & I2C_M_RD)) {
++ if (!tx_success) {
++ /* An ACK was not received for transmitted byte */
++ printk(KERN_DEBUG "ACK not received \n");
++ return -1;
++ }
++ }
++
++ return 0;
++}
++
++/* Transmit a START signal to the slave device */
++static void imx_i2c_start(imx_i2c_device * dev, struct i2c_msg *msg)
++{
++ unsigned int cr, sr;
++ unsigned int addr_trans;
++ int retry = 16;
++
++ /*
++ * Set the slave address and the requested transfer mode
++ * in the data register
++ */
++ addr_trans = msg->addr << 1;
++ if (msg->flags & I2C_M_RD) {
++ addr_trans |= 0x01;
++ }
++
++ /* Set the Master bit */
++ cr = readw(dev->membase + MXC_I2CR);
++ cr |= MXC_I2CR_MSTA;
++ writew(cr, dev->membase + MXC_I2CR);
++
++ /* Wait till the Bus Busy bit is set */
++ sr = readw(dev->membase + MXC_I2SR);
++ while (retry-- && (!(sr & MXC_I2SR_IBB))) {
++ udelay(3);
++ sr = readw(dev->membase + MXC_I2SR);
++ }
++ if (retry <= 0) {
++ printk(KERN_DEBUG "Could not grab Bus ownership\n");
++ }
++
++ /* Set the Transmit bit */
++ cr = readw(dev->membase + MXC_I2CR);
++ cr |= MXC_I2CR_MTX;
++ writew(cr, dev->membase + MXC_I2CR);
++
++ writew(addr_trans, dev->membase + MXC_I2DR);
++}
++
++/* Transmit a REPEAT START to the slave device */
++static void imx_i2c_repstart(imx_i2c_device * dev, struct i2c_msg *msg)
++{
++ unsigned int cr;
++ unsigned int addr_trans;
++
++ /*
++ * Set the slave address and the requested transfer mode
++ * in the data register
++ */
++ addr_trans = msg->addr << 1;
++ if (msg->flags & I2C_M_RD) {
++ addr_trans |= 0x01;
++ }
++ cr = readw(dev->membase + MXC_I2CR);
++ cr |= MXC_I2CR_RSTA;
++ writew(cr, dev->membase + MXC_I2CR);
++ udelay(3);
++ writew(addr_trans, dev->membase + MXC_I2DR);
++}
++
++/*
++ * Read the received data. The function waits till data is available or times
++ * out. Generates a stop signal if this is the last message to be received.
++ * Sends an ack for all the bytes received except the last byte.
++ * The function returns the number of bytes read or -1 on time out.
++ */
++static int imx_i2c_readbytes(imx_i2c_device * dev, struct i2c_msg *msg,
++ int last, int addr_comp)
++{
++ int i;
++ char *buf = msg->buf;
++ int len = msg->len;
++ unsigned int cr;
++
++ cr = readw(dev->membase + MXC_I2CR);
++
++ /* switch to receive mode */
++ cr &= ~MXC_I2CR_MTX;
++ /*
++ * Clear the TXAK bit to gen an ack when receiving only one byte.
++ */
++ if (len == 1)
++ cr |= MXC_I2CR_TXAK;
++ else
++ cr &= ~MXC_I2CR_TXAK;
++
++ writew(cr, dev->membase + MXC_I2CR);
++ /*
++ * Dummy read only at the end of an address cycle
++ */
++ if (addr_comp > 0)
++ readw(dev->membase + MXC_I2DR);
++
++ for (i = 0; i < len; i++) {
++ /* Wait for data transmission to complete */
++ if (imx_i2c_wait_for_tc(dev, msg->flags)) {
++ imx_i2c_stop(dev);
++ return -1;
++ }
++ /* Do not generate an ACK for the last byte */
++ if (i == (len - 2)) {
++ cr = readw(dev->membase + MXC_I2CR);
++ cr |= MXC_I2CR_TXAK;
++ writew(cr, dev->membase + MXC_I2CR);
++ } else if (i == (len - 1)) {
++ if (last)
++ imx_i2c_stop(dev);
++ }
++ /* Read the data */
++ *buf++ = readw(dev->membase + MXC_I2DR);
++ }
++
++ return i;
++}
++
++/*
++ * Write the data to the data register. Generates a stop signal if this is
++ * the last message to be sent or if no ack was received for the data sent.
++ * The function returns the number of bytes written or -1 on time out
++ * or if no ack was received for the data that was sent.
++ */
++static int imx_i2c_writebytes(imx_i2c_device * dev, struct i2c_msg *msg,
++ int last)
++{
++ int i;
++ char *buf = msg->buf;
++ int len = msg->len;
++ unsigned int cr;
++
++ cr = readw(dev->membase + MXC_I2CR);
++ /* switch to transmit mode */
++ cr |= MXC_I2CR_MTX;
++ writew(cr, dev->membase + MXC_I2CR);
++
++ for (i = 0; i < len; i++) {
++ /* Write the data */
++ writew(*buf++, dev->membase + MXC_I2DR);
++ if (imx_i2c_wait_for_tc(dev, msg->flags)) {
++ imx_i2c_stop(dev);
++ return -1;
++ }
++ }
++ if (last > 0) {
++ imx_i2c_stop(dev);
++ }
++
++ return i;
++}
++
++/* Function enables the I2C module and initializes the registers */
++static void imx_i2c_module_en(imx_i2c_device * dev, int trans_flag)
++{
++ clk_enable(dev->clk);
++ /* Set the frequency divider */
++ writew(dev->clkdiv, dev->membase + MXC_IFDR);
++ /* Clear the status register */
++ writew(0x0, dev->membase + MXC_I2SR);
++ /* Enable I2C and its interrupts */
++ writew(MXC_I2CR_IEN, dev->membase + MXC_I2CR);
++ writew(MXC_I2CR_IEN | MXC_I2CR_IIEN, dev->membase + MXC_I2CR);
++}
++
++/* Disables the I2C module */
++static void imx_i2c_module_dis(imx_i2c_device * dev)
++{
++ writew(0x0, dev->membase + MXC_I2CR);
++ clk_disable(dev->clk);
++}
++
++/*
++ * The function is registered in the adapter structure. It is called when an MXC
++ * driver wishes to transfer data to a device connected to the I2C device.
++ * The function returns the number of messages transferred, -EREMOTEIO on I2C
++ * failure and a 0 if the num argument is less than 0.
++ */
++static int imx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
++ int num)
++{
++ imx_i2c_device *dev = (imx_i2c_device *) (i2c_get_adapdata(adap));
++ int i, ret = 0, addr_comp = 0;
++ unsigned int sr;
++
++ if (dev->low_power) {
++ printk(KERN_ERR "I2C Device in low power mode\n");
++ return -EREMOTEIO;
++ }
++
++ if (num < 1)
++ return 0;
++
++ imx_i2c_module_en(dev, msgs[0].flags);
++ sr = readw(dev->membase + MXC_I2SR);
++
++ /* Check bus state */
++ if (sr & MXC_I2SR_IBB) {
++ imx_i2c_module_dis(dev);
++ printk(KERN_DEBUG "Bus busy\n");
++ return -EREMOTEIO;
++ }
++
++ transfer_done = false;
++ tx_success = false;
++ for (i = 0; i < num && ret >= 0; i++) {
++ addr_comp = 0;
++ /*
++ * Send the slave address and transfer direction in the
++ * address cycle
++ */
++ if (i == 0) {
++ /* Send a start or repeat start signal */
++ imx_i2c_start(dev, &msgs[0]);
++ /* Wait for the address cycle to complete */
++ if (imx_i2c_wait_for_tc(dev, msgs[0].flags)) {
++ imx_i2c_stop(dev);
++ imx_i2c_module_dis(dev);
++ return -EREMOTEIO;
++ }
++ addr_comp = 1;
++ } else {
++ /*
++ * Generate repeat start only if required i.e the address
++ * changed or the transfer direction changed
++ */
++ if ((msgs[i].addr != msgs[i - 1].addr) ||
++ ((msgs[i].flags & I2C_M_RD) !=
++ (msgs[i - 1].flags & I2C_M_RD))) {
++ imx_i2c_repstart(dev, &msgs[i]);
++ /* Wait for the address cycle to complete */
++ if (imx_i2c_wait_for_tc(dev, msgs[i].flags)) {
++ imx_i2c_stop(dev);
++ imx_i2c_module_dis(dev);
++ return -EREMOTEIO;
++ }
++ addr_comp = 1;
++ }
++ }
++
++ /* Transfer the data */
++ if (msgs[i].flags & I2C_M_RD) {
++ /* Read the data */
++ ret = imx_i2c_readbytes(dev, &msgs[i], (i + 1 == num),
++ addr_comp);
++ if (ret < 0) {
++ printk(KERN_ERR "imx_i2c_readbytes: fail.\n");
++ break;
++ }
++ } else {
++ /* Write the data */
++ ret = imx_i2c_writebytes(dev, &msgs[i], (i + 1 == num));
++ if (ret < 0) {
++ printk(KERN_ERR "imx_i2c_writebytes: fail.\n");
++ break;
++ }
++ }
++ }
++
++ imx_i2c_module_dis(dev);
++ return i;
++}
++
++/*
++ * Returns the i2c functionality supported by this driver.
++ * Returns the functionality that is supported.
++ */
++static u32 imx_i2c_func(struct i2c_adapter *adap)
++{
++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++/*
++ * Stores the pointers for the i2c algorithm functions. The algorithm functions
++ * is used by the i2c bus driver to talk to the i2c bus
++ */
++static struct i2c_algorithm imx_i2c_algorithm = {
++ .master_xfer = imx_i2c_xfer,
++ .functionality = imx_i2c_func
++};
++
++/*
++ * Interrupt Service Routine. It signals to the process about the data transfer
++ * completion. Also sets a flag if bus arbitration is lost.
++ * The function returns IRQ_HANDLED.
++ */
++static irqreturn_t imx_i2c_handler(int irq, void *dev_id)
++{
++ imx_i2c_device *dev = dev_id;
++ unsigned int sr, cr;
++
++ sr = readw(dev->membase + MXC_I2SR);
++ cr = readw(dev->membase + MXC_I2CR);
++
++ /*
++ * Clear the interrupt bit
++ */
++ writew(0x0, dev->membase + MXC_I2SR);
++
++ if (sr & MXC_I2SR_IAL) {
++ printk(KERN_DEBUG "Bus Arbitration lost\n");
++ } else {
++ /* Interrupt due byte transfer completion */
++ tx_success = false;
++ /* Check if RXAK is received in Transmit mode */
++ if ((cr & MXC_I2CR_MTX) && (!(sr & MXC_I2SR_RXAK))) {
++ tx_success = true;
++ }
++ transfer_done = true;
++ wake_up_interruptible(&dev->wq);
++ }
++
++ return IRQ_HANDLED;
++}
++
++/*
++ * This function is called to put the I2C adapter in a low power state. Refer to the
++ * document driver-model/driver.txt in the kernel source tree for more
++ * information.
++ * The function returns 0 on success and -1 on failure.
++ */
++static int mxci2c_suspend(struct platform_device *pdev, pm_message_t state)
++{
++ imx_i2c_device *mxcdev = platform_get_drvdata(pdev);
++ unsigned int sr;
++
++ if (mxcdev == NULL)
++ return -1;
++
++ /* Prevent further calls to be processed */
++ mxcdev->low_power = true;
++ /* Wait till we finish the current transfer */
++ sr = readw(mxcdev->membase + MXC_I2SR);
++ while (sr & MXC_I2SR_IBB) {
++ msleep(10);
++ sr = readw(mxcdev->membase + MXC_I2SR);
++ }
++
++ mxcdev->pdata->exit(pdev);
++
++ return 0;
++}
++
++/*
++ * This function is called to bring the I2C adapter back from a low power state. Refer
++ * to the document driver-model/driver.txt in the kernel source tree for more
++ * information.
++ * The function returns 0 on success and -1 on failure
++ */
++static int mxci2c_resume(struct platform_device *pdev)
++{
++ imx_i2c_device *mxcdev = platform_get_drvdata(pdev);
++
++ if (mxcdev == NULL)
++ return -1;
++
++ mxcdev->low_power = false;
++ mxcdev->pdata->init(pdev);
++
++ return 0;
++}
++
++/*
++ * This function is called during the driver binding process.
++ * The function always returns 0.
++ */
++static int mxci2c_probe(struct platform_device *pdev)
++{
++ imx_i2c_device *imx_i2c;
++ struct imx_i2c_platform_data *i2c_plat_data = pdev->dev.platform_data;
++ struct resource *res;
++ int id = pdev->id;
++ u32 clk_freq;
++ int ret = 0;
++ int i=0;
++
++ imx_i2c = kzalloc(sizeof(imx_i2c_device), GFP_KERNEL);
++ if (!imx_i2c) {
++ return -ENOMEM;
++ }
++
++ imx_i2c->pdata = i2c_plat_data;
++ /* claim the region we will work on */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ if (res == NULL) {
++ ret = -ENODEV;
++ goto err1;
++ }
++ if (!request_mem_region(res->start, res->end - res->start + 1, DRV_NAME)) {
++ dev_err(&pdev->dev, "request_mem_region failed for IMX I2C %d\n", id);
++ ret = -EBUSY;
++ goto err1;
++ }
++
++ /* TODO: use iomap() */
++ imx_i2c->membase = IO_ADDRESS(res->start);
++
++ /* Claim the I2C irq line */
++ imx_i2c->irq = platform_get_irq(pdev, 0);
++ if (imx_i2c->irq < 0) {
++ dev_err(&pdev->dev, "No interrupt defined for IMX I2C %d\n", id);
++ ret = imx_i2c->irq;
++ goto err2;
++ }
++ ret = request_irq(imx_i2c->irq, imx_i2c_handler,
++ 0, DRV_NAME, imx_i2c);
++ if (ret < 0) {
++ dev_err(&pdev->dev, "Cannot claim interrupt %d for IMX I2C %d\n",
++ imx_i2c->irq, id);
++ goto err2;
++ }
++
++ init_waitqueue_head(&imx_i2c->wq);
++
++ imx_i2c->low_power = false;
++
++ imx_i2c->pdata->init(pdev);
++
++ imx_i2c->clk = clk_get(&pdev->dev, "i2c_clk");
++ if (imx_i2c == NULL) {
++ dev_err(&pdev->dev, "Cannot get clock for for IMX I2C %d\n", id);
++ goto err3;
++ }
++
++ clk_freq = clk_get_rate(imx_i2c->clk);
++ imx_i2c->clkdiv = -1;
++ if (i2c_plat_data->i2c_clk) {
++ /* Calculate divider and round up any fractional part */
++ int div = (clk_freq + i2c_plat_data->i2c_clk - 1) /
++ i2c_plat_data->i2c_clk;
++ for (i = 0; i2c_clk_table[i].div != 0; i++) {
++ if (i2c_clk_table[i].div >= div) {
++ imx_i2c->clkdiv = i2c_clk_table[i].reg_value;
++ break;
++ }
++ }
++ }
++ if (imx_i2c->clkdiv == -1) {
++ i--;
++ imx_i2c->clkdiv = 0x1F; /* Use max divider */
++ }
++ dev_dbg(&pdev->dev, "i2c speed is %d/%d = %d bps, reg val = 0x%02X\n",
++ clk_freq, i2c_clk_table[i].div,
++ clk_freq / i2c_clk_table[i].div, imx_i2c->clkdiv);
++
++ /*
++ * Set the adapter information
++ */
++ strcpy(imx_i2c->adap.name, MXC_ADAPTER_NAME);
++ imx_i2c->adap.id = id;
++ imx_i2c->adap.nr = id;
++ imx_i2c->adap.algo = &imx_i2c_algorithm;
++ imx_i2c->adap.timeout = 1;
++ platform_set_drvdata(pdev, imx_i2c);
++ i2c_set_adapdata(&imx_i2c->adap, imx_i2c);
++ if ((ret = i2c_add_numbered_adapter(&imx_i2c->adap)) < 0) {
++ dev_err(&pdev->dev, "Cannot register the IMX I2C %d master\n", id);
++ goto err3;
++ }
++
++ return 0;
++
++err3:
++ imx_i2c->pdata->exit(pdev);
++ free_irq(imx_i2c->irq, imx_i2c);
++err2:
++ release_mem_region(res->start, res->end - res->start + 1);
++err1:
++ dev_err(&pdev->dev, "failed to probe i2c adapter\n");
++ kfree(imx_i2c);
++ return ret;
++}
++
++/*
++ * Dissociates the driver from the I2C device.
++ */
++static int mxci2c_remove(struct platform_device *pdev)
++{
++ imx_i2c_device *imx_i2c = platform_get_drvdata(pdev);
++ struct resource *res;
++
++ free_irq(imx_i2c->irq, imx_i2c);
++ i2c_del_adapter(&imx_i2c->adap);
++ imx_i2c->pdata->exit(pdev);
++ clk_put(imx_i2c->clk);
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ release_mem_region(res->start, res->end - res->start + 1);
++ platform_set_drvdata(pdev, NULL);
++ return 0;
++}
++
++/*
++ * This structure contains pointers to the power management callback functions.
++ */
++static struct platform_driver mxci2c_driver = {
++ .driver = {
++ .name = DRV_NAME,
++ .owner = THIS_MODULE,
++ },
++ .probe = mxci2c_probe,
++ .remove = mxci2c_remove,
++ .suspend = mxci2c_suspend,
++ .resume = mxci2c_resume,
++};
++
++static int __init imx_i2c_init(void)
++{
++ return platform_driver_register(&mxci2c_driver);
++}
++
++static void __exit imx_i2c_exit(void)
++{
++ platform_driver_unregister(&mxci2c_driver);
++}
++
++subsys_initcall(imx_i2c_init);
++module_exit(imx_i2c_exit);
++
++MODULE_AUTHOR("Freescale Semiconductor, Inc.");
++MODULE_DESCRIPTION("MXC I2C driver");
++MODULE_LICENSE("GPL");
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/232-apf27-pengu-imx27_spi_driver.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/232-apf27-pengu-imx27_spi_driver.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/232-apf27-pengu-imx27_spi_driver.diff 2008-04-03 06:43:24 UTC (rev 788)
@@ -0,0 +1,821 @@
+Subject: [@num@/@total@] i.MX27: SPI driver
+From: Juergen Beisert <j.b...@pe...>
+
+This patch adds basic SPI master driver support for the i.MX family
+
+TODO: Discover what the mxc_spi_unique_def structures mean. Do they rely on
+internal silicon revisions or different family members (i.MX1, i.MX21, i.MX27)
+
+At least the i.MX21 and i.MX27 are using the same SPI device. iMX1 uses nearly
+the same, but with less register bits and data registers are only 16 bit
+instead of 32 bit.
+
+Signed-off-by: Juergen Beisert <j.b...@pe...>
+Signed-off-by: N.N. (FIXME: get a sign from freescale)
+
+---
+
+ drivers/spi/Kconfig | 27 +
+ drivers/spi/Makefile | 1
+ drivers/spi/mxc_spi.c | 744 ++++++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 772 insertions(+)
+
+Index: drivers/spi/mxc_spi.c
+===================================================================
+--- /dev/null
++++ linux/drivers/spi/mxc_spi.c
+@@ -0,0 +1,744 @@
++/*
++ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ * Copyright (C) 2008 Juergen Beisert
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
++ */
++
++#undef DEBUG
++
++#include <linux/completion.h>
++#include <linux/platform_device.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/types.h>
++#include <linux/clk.h>
++
++#include <linux/spi/spi.h>
++#include <linux/spi/spi_bitbang.h>
++
++#include <asm/hardware.h>
++#include <asm/irq.h>
++#include <asm/io.h>
++#include <asm/arch/gpio.h>
++#include <asm/arch/imx_spi.h>
++
++#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK
++struct spi_chip_info {
++ int lb_enable;
++};
++
++static struct spi_chip_info lb_chip_info = {
++ .lb_enable = 1,
++};
++
++static struct spi_board_info loopback_info[] = {
++#ifdef CONFIG_SPI_MXC_SELECT1
++ {
++ .modalias = "loopback_spi",
++ .controller_data = &lb_chip_info,
++ .irq = 0,
++ .max_speed_hz = 4000000,
++ .bus_num = 0,
++ .chip_select = 4,
++ },
++#endif
++#ifdef CONFIG_SPI_MXC_SELECT2
++ {
++ .modalias = "loopback_spi",
++ .controller_data = &lb_chip_info,
++ .irq = 0,
++ .max_speed_hz = 4000000,
++ .bus_num = 1,
++ .chip_select = 4,
++ },
++#endif
++#ifdef CONFIG_SPI_MXC_SELECT3
++ {
++ .modalias = "loopback_spi",
++ .controller_data = &lb_chip_info,
++ .irq = 0,
++ .max_speed_hz = 4000000,
++ .bus_num = 2,
++ .chip_select = 4,
++ },
++#endif
++};
++#endif
++
++static struct mxc_spi_unique_def spi_ver_0_7 = {
++ .intr_bit_shift = MXC_CSPIINT_IRQSHIFT_0_7,
++ .cs_shift = MXC_CSPICTRL_CSSHIFT_0_7,
++ .bc_shift = MXC_CSPICTRL_BCSHIFT_0_7,
++ .bc_mask = MXC_CSPICTRL_BCMASK_0_7,
++ .drctrl_shift = MXC_CSPICTRL_DRCTRLSHIFT_0_7,
++ .xfer_complete = MXC_CSPISTAT_TC_0_7,
++ .bc_overflow = MXC_CSPISTAT_BO_0_7,
++};
++
++static struct mxc_spi_unique_def spi_ver_0_5 = {
++ .intr_bit_shift = MXC_CSPIINT_IRQSHIFT_0_5,
++ .cs_shift = MXC_CSPICTRL_CSSHIFT_0_5,
++ .bc_shift = MXC_CSPICTRL_BCSHIFT_0_5,
++ .bc_mask = MXC_CSPICTRL_BCMASK_0_5,
++ .drctrl_shift = MXC_CSPICTRL_DRCTRLSHIFT_0_5,
++ .xfer_complete = MXC_CSPISTAT_TC_0_5,
++ .bc_overflow = MXC_CSPISTAT_BO_0_5,
++};
++
++static struct mxc_spi_unique_def spi_ver_0_4 = {
++ .intr_bit_shift = MXC_CSPIINT_IRQSHIFT_0_4,
++ .cs_shift = MXC_CSPICTRL_CSSHIFT_0_4,
++ .bc_shift = MXC_CSPICTRL_BCSHIFT_0_4,
++ .bc_mask = MXC_CSPICTRL_BCMASK_0_4,
++ .drctrl_shift = MXC_CSPICTRL_DRCTRLSHIFT_0_4,
++ .xfer_complete = MXC_CSPISTAT_TC_0_4,
++ .bc_overflow = MXC_CSPISTAT_BO_0_4,
++};
++
++static struct mxc_spi_unique_def spi_ver_0_0 = {
++ .intr_bit_shift = MXC_CSPIINT_IRQSHIFT_0_0,
++ .cs_shift = MXC_CSPICTRL_CSSHIFT_0_0,
++ .bc_shift = MXC_CSPICTRL_BCSHIFT_0_0,
++ .bc_mask = MXC_CSPICTRL_BCMASK_0_0,
++ .drctrl_shift = MXC_CSPICTRL_DRCTRLSHIFT_0_0,
++ .xfer_complete = MXC_CSPISTAT_TC_0_0,
++ .bc_overflow = MXC_CSPISTAT_BO_0_0,
++};
++
++struct mxc_spi;
++/*
++ * Structure to group together all the data buffers and functions
++ * used in data transfers.
++ */
++struct mxc_spi_xfer {
++ const void *tx_buf; /* Transmit buffer. */
++ void *rx_buf; /* Receive buffer. */
++ unsigned int count; /* Data transfered count. */
++ void (*rx_get) (struct mxc_spi *, u32 val); /* Function to read the FIFO data to rx_buf. */
++ u32(*tx_get) (struct mxc_spi *); /* Function to get the data to be written to FIFO. */
++};
++
++/*
++ * This structure is a way for the low level driver to define their own
++ * spi_master structure. This structure includes the core spi_master
++ * structure that is provided by Linux SPI Framework/driver as an
++ * element and has other elements that are specifically required by this
++ * low-level driver.
++ */
++struct mxc_spi {
++ struct spi_bitbang mxc_bitbang; /* SPI Master and a simple I/O queue runner. */
++ struct completion xfer_done; /* Completion flags used in data transfers. */
++ struct mxc_spi_xfer transfer; /* Data transfer structure. */
++ struct resource *res; /* Resource structure, which will maintain base addresses and IRQs. */
++ void *base; /* Base address of CSPI, used in readl and writel. */
++ int irq; /* CSPI IRQ number. */
++ struct clk *clk; /* CSPI Clock id. */
++ /*!
++ * CSPI input clock SCLK.
++ */
++ unsigned long spi_ipg_clk;
++ /*!
++ * CSPI registers' bit pattern.
++ */
++ struct mxc_spi_unique_def *spi_ver_def;
++};
++
++#define MXC_SPI_BUF_RX(type) \
++void mxc_spi_buf_rx_##type(struct mxc_spi *master_drv_data, u32 val)\
++{\
++ type *rx = master_drv_data->transfer.rx_buf;\
++ *rx++ = (type)val;\
++ master_drv_data->transfer.rx_buf = rx;\
++}
++
++#define MXC_SPI_BUF_TX(type) \
++u32 mxc_spi_buf_tx_##type(struct mxc_spi *master_drv_data)\
++{\
++ u32 val;\
++ const type *tx = master_drv_data->transfer.tx_buf;\
++ val = *tx++;\
++ master_drv_data->transfer.tx_buf = tx;\
++ return val;\
++}
++MXC_SPI_BUF_RX(u8)
++ MXC_SPI_BUF_TX(u8)
++ MXC_SPI_BUF_RX(u16)
++ MXC_SPI_BUF_TX(u16)
++ MXC_SPI_BUF_RX(u32)
++ MXC_SPI_BUF_TX(u32)
++
++static int spi_enable_interrupt(struct mxc_spi *master_data, unsigned int irqs)
++{
++ if (irqs & ~((1 << master_data->spi_ver_def->intr_bit_shift) - 1)) {
++ return -1;
++ }
++
++ writel((irqs | readl(master_data->base + MXC_CSPIINT)),
++ master_data->base + MXC_CSPIINT);
++
++ return 0;
++}
++
++static int spi_disable_interrupt(struct mxc_spi *master_data, unsigned int irqs)
++{
++ if (irqs & ~((1 << master_data->spi_ver_def->intr_bit_shift) - 1)) {
++ return -1;
++ }
++
++ writel((~irqs & readl(master_data->base + MXC_CSPIINT)),
++ master_data->base + MXC_CSPIINT);
++ return 0;
++}
++
++static unsigned int spi_find_baudrate(struct mxc_spi *master_data,
++ unsigned int baud)
++{
++ unsigned int divisor;
++ unsigned int shift = 0;
++
++ /* Calculate required divisor (rounded) */
++ divisor = (master_data->spi_ipg_clk + baud / 2) / baud;
++ while (divisor >>= 1)
++ shift++;
++ MXC_CSPICTRL_ADJUST_SHIFT(shift);
++ if (shift > MXC_CSPICTRL_MAXDATRATE)
++ shift = MXC_CSPICTRL_MAXDATRATE;
++
++ return (shift << MXC_CSPICTRL_DATASHIFT);
++}
++
++static unsigned int spi_get_rx_data(void *base)
++{
++ return readl(base + MXC_CSPIRXDATA);
++}
++
++static void spi_put_tx_data(void *base, unsigned int val)
++{
++ unsigned int ctrl_reg;
++
++ writel(val, base + MXC_CSPITXDATA);
++
++ ctrl_reg = readl(base + MXC_CSPICTRL);
++
++ ctrl_reg |= MXC_CSPICTRL_XCH;
++
++ writel(ctrl_reg, base + MXC_CSPICTRL);
++
++ return;
++}
++
++void mxc_spi_chipselect(struct spi_device *spi, int is_active)
++{
++ struct mxc_spi *master_drv_data;
++ struct mxc_spi_xfer *ptransfer;
++ struct mxc_spi_unique_def *spi_ver_def;
++ unsigned int ctrl_reg;
++ unsigned int ctrl_mask;
++ unsigned int xfer_len;
++
++ if (is_active == BITBANG_CS_INACTIVE) {
++ /*Need to deselect the slave */
++ return;
++ }
++
++ /* Get the master controller driver data from spi device's master */
++
++ master_drv_data = spi_master_get_devdata(spi->master);
++ spi_ver_def = master_drv_data->spi_ver_def;
++
++ xfer_len = spi->bits_per_word;
++
++ /* Control Register Settings for transfer to this slave */
++
++ ctrl_reg = readl(master_drv_data->base + MXC_CSPICTRL);
++
++ ctrl_mask =
++ (MXC_CSPICTRL_LOWPOL | MXC_CSPICTRL_PHA | MXC_CSPICTRL_HIGHSSPOL |
++ MXC_CSPICTRL_CSMASK << spi_ver_def->cs_shift |
++ MXC_CSPICTRL_DATAMASK << MXC_CSPICTRL_DATASHIFT |
++ spi_ver_def->bc_mask << spi_ver_def->bc_shift);
++ ctrl_reg &= ~ctrl_mask;
++
++ ctrl_reg |=
++ ((spi->chip_select & MXC_CSPICTRL_CSMASK) << spi_ver_def->cs_shift);
++ ctrl_reg |= spi_find_baudrate(master_drv_data, spi->max_speed_hz);
++ ctrl_reg |=
++ (((xfer_len - 1) & spi_ver_def->bc_mask) << spi_ver_def->bc_shift);
++ if (spi->mode & SPI_CPHA)
++ ctrl_reg |= MXC_CSPICTRL_PHA;
++ if (!(spi->mode & SPI_CPOL))
++ ctrl_reg |= MXC_CSPICTRL_LOWPOL;
++ if (spi->mode & SPI_CS_HIGH)
++ ctrl_reg |= MXC_CSPICTRL_HIGHSSPOL;
++
++ writel(ctrl_reg, master_drv_data->base + MXC_CSPICTRL);
++
++ /* Initialize the functions for transfer */
++ ptransfer = &master_drv_data->transfer;
++ if (xfer_len <= 8) {
++ ptransfer->rx_get = mxc_spi_buf_rx_u8;
++ ptransfer->tx_get = mxc_spi_buf_tx_u8;
++ } else if (xfer_len <= 16) {
++ ptransfer->rx_get = mxc_spi_buf_rx_u16;
++ ptransfer->tx_get = mxc_spi_buf_tx_u16;
++ } else if (xfer_len <= 32) {
++ ptransfer->rx_get = mxc_spi_buf_rx_u32;
++ ptransfer->tx_get = mxc_spi_buf_tx_u32;
++ }
++#ifdef CONFIG_SPI_MXC_TEST_LOOPBACK
++ {
++ struct...
[truncated message content] |
|
From: <Fa...@us...> - 2008-04-02 15:08:45
|
Revision: 787
http://armadeus.svn.sourceforge.net/armadeus/?rev=787&view=rev
Author: FabM
Date: 2008-04-02 08:08:36 -0700 (Wed, 02 Apr 2008)
Log Message:
-----------
[KERNEL] modify patch for apf0328.c
Modified Paths:
--------------
trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff
Modified: trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff
===================================================================
--- trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff 2008-04-02 15:07:16 UTC (rev 786)
+++ trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff 2008-04-02 15:08:36 UTC (rev 787)
@@ -807,8 +807,8 @@
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
--- linux-2.6.23.1.1/arch/arm/mach-imx/apf9328.c 1970-01-01 01:00:00.000000000 +0100
-+++ linux-2.6.23.1.1.mod/arch/arm/mach-imx/apf9328.c 2007-07-22 22:46:57.000000000 +0200
-@@ -0,0 +1,533 @@
++++ linux-2.6.23.1.1.mod/arch/arm/mach-imx/apf9328.c 2008-04-01 16:15:37.000000000 +0200
+@@ -0,0 +1,543 @@
+/*
+ * linux/arch/arm/mach-imx/apf9328.c
+ *
@@ -1288,6 +1288,10 @@
+ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+#endif
+
++#ifdef CONFIG_ARMADEUS_FPGA_DRIVERS
++ request_mem_region(IMX_CS1_PHYS,IMX_CS1_SIZE,"FPGA");
++#endif // CONFIG_ARMADEUS_FPGA_DRIVERS
++
+ printk("--- APF9328 ressources registered\n");
+}
+
@@ -1329,6 +1333,12 @@
+#ifdef CONFIG_CAN_MCP251X
+ set_irq_type( IRQ_GPIOC(CAN_MPC251X_INT_GPIOC), IRQF_TRIGGER_FALLING );
+#endif // CONFIG_CAN_MCP251X
++
++#ifdef CONFIG_ARMADEUS_FPGA_DRIVERS
++#define FPGA_INT_GPIOA 1
++ set_irq_type(IRQ_GPIOA(FPGA_INT_GPIOA),IRQF_TRIGGER_RISING);
++#endif // CONFIG_ARMADEUS_FPGA_DRIVERS
++
+}
+
+
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <Fa...@us...> - 2008-04-02 15:07:16
|
Revision: 786
http://armadeus.svn.sourceforge.net/armadeus/?rev=786&view=rev
Author: FabM
Date: 2008-04-02 08:07:16 -0700 (Wed, 02 Apr 2008)
Log Message:
-----------
[FIRMWARE][FPGA] correct some mistakes, and adding GPL
Modified Paths:
--------------
trunk/firmware/Wisbone_example/Makefile
trunk/firmware/Wisbone_example/src/Wb_button.vhd
trunk/firmware/Wisbone_example/src/Wb_led.ucf
trunk/firmware/Wisbone_example/src/Wb_led.vhd
trunk/firmware/Wisbone_example/src/Wb_top.vhd
trunk/firmware/Wisbone_example/src/intercon.vhd
trunk/firmware/Wisbone_example/src/wishbone/imx_wrapper.vhd
trunk/firmware/Wisbone_example/src/wishbone/irq_mngr.vhd
trunk/firmware/Wisbone_example/src/wishbone/syscon.vhd
trunk/firmware/apf_pkg/apf_test_pkg.vhd
trunk/firmware/bus_led/src/bus_led.vhd
trunk/firmware/bus_led/src/bus_led_top.vhd
trunk/firmware/bus_led/testbench/led_top_tb.vhd
Modified: trunk/firmware/Wisbone_example/Makefile
===================================================================
--- trunk/firmware/Wisbone_example/Makefile 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/Wisbone_example/Makefile 2008-04-02 15:07:16 UTC (rev 786)
@@ -67,6 +67,7 @@
messages : bit
$(BRIEF) $(BIN)/$(PROJECT)
+ @echo bitstream : $(PROJECT).bit
bit : $(BIN)/$(PROJECT).ncd trace
Modified: trunk/firmware/Wisbone_example/src/Wb_button.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/Wb_button.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/Wisbone_example/src/Wb_button.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -7,8 +7,23 @@
--
-- Abstract :
--
----------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
Modified: trunk/firmware/Wisbone_example/src/Wb_led.ucf
===================================================================
--- trunk/firmware/Wisbone_example/src/Wb_led.ucf 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/Wisbone_example/src/Wb_led.ucf 2008-04-02 15:07:16 UTC (rev 786)
@@ -1,4 +1,6 @@
-# Clock at 96MHz
+
+
+# Clock at 96MHzi
NET "clk" LOC = "P55" | IOSTANDARD = LVCMOS33 ;
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10.42 ns HIGH 50 %;
@@ -50,7 +52,7 @@
# led output
NET "LED" LOC = "P116" | IOSTANDARD = LVCMOS33 ;
# Button input
-NET "button" LOC = "P102" | IOSTANDARD = LVCMOS33 ;
+NET "button" LOC = "P141" | IOSTANDARD = LVCMOS33 ;
# Test (X10 on devfull) connection
#NET "imx_data0_test" LOC = "P102" | IOSTANDARD = LVCMOS33 ;
Modified: trunk/firmware/Wisbone_example/src/Wb_led.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/Wb_led.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/Wisbone_example/src/Wb_led.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -7,7 +7,21 @@
--
-- Abstract : drive one led with Wishbone bus
--
----------------------------------------------------------------------------
+------------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Modified: trunk/firmware/Wisbone_example/src/Wb_top.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/Wb_top.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/Wisbone_example/src/Wb_top.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -7,8 +7,23 @@
--
-- Abstract :
--
----------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
Modified: trunk/firmware/Wisbone_example/src/intercon.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/intercon.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/Wisbone_example/src/intercon.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -8,8 +8,23 @@
-- Abstract : connect master wishbone device with
-- slave(s) wishbone device
--
----------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
Modified: trunk/firmware/Wisbone_example/src/wishbone/imx_wrapper.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/wishbone/imx_wrapper.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/Wisbone_example/src/wishbone/imx_wrapper.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -17,7 +17,23 @@
-- adding comments and changing some signals names
--
-------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Modified: trunk/firmware/Wisbone_example/src/wishbone/irq_mngr.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/wishbone/irq_mngr.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/Wisbone_example/src/wishbone/irq_mngr.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -13,7 +13,23 @@
-- Modifications :
--
-------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
Modified: trunk/firmware/Wisbone_example/src/wishbone/syscon.vhd
===================================================================
--- trunk/firmware/Wisbone_example/src/wishbone/syscon.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/Wisbone_example/src/wishbone/syscon.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -8,7 +8,23 @@
-- Abstract :
--
---------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
Modified: trunk/firmware/apf_pkg/apf_test_pkg.vhd
===================================================================
--- trunk/firmware/apf_pkg/apf_test_pkg.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/apf_pkg/apf_test_pkg.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -1,11 +1,27 @@
-
----------------------------------------------
-- Design Name : Test bench utils
--- File Name : apf_test_pkg.vhw
+-- File Name : apf_test_pkg.vhd
-- Function : Defines communication function between imx and fpga
--- Author : Fabien Marteau
+-- Author : Fabien Marteau <fab...@ar...>
-- Version : 1.00
---------------------------------------------
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
+
library ieee;
use ieee.std_logic_1164.all;
Modified: trunk/firmware/bus_led/src/bus_led.vhd
===================================================================
--- trunk/firmware/bus_led/src/bus_led.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/bus_led/src/bus_led.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -7,7 +7,21 @@
--
-- Abstract :
--
----------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Modified: trunk/firmware/bus_led/src/bus_led_top.vhd
===================================================================
--- trunk/firmware/bus_led/src/bus_led_top.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/bus_led/src/bus_led_top.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -1,8 +1,8 @@
----------------------------------------------------------------------------------
-- Company: ARMadeus Systems
--- Engineer: Fabien Marteau
+-- Engineer: Fabien Marteau <fab...@ar...>
--
--- Create Date:
+-- Create Date: 2008
-- Design Name:
-- Module Name:
-- Project Name:
@@ -17,6 +17,20 @@
-- Additional Comments:
--
----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Modified: trunk/firmware/bus_led/testbench/led_top_tb.vhd
===================================================================
--- trunk/firmware/bus_led/testbench/led_top_tb.vhd 2008-04-02 15:05:24 UTC (rev 785)
+++ trunk/firmware/bus_led/testbench/led_top_tb.vhd 2008-04-02 15:07:16 UTC (rev 786)
@@ -1,6 +1,6 @@
----------------------------------------------------------------------------------
-- Company : ARMadeus Systems
--- Author(s) : Fabien Marteau
+-- Author(s) : Fabien Marteau <fab...@ar...>
--
-- Creation Date : 14/02/2008
-- File : led_top_tb.vhd
@@ -8,7 +8,23 @@
-- Abstract : Testbench for simple design that switch a led with the imx
--
----------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <Fa...@us...> - 2008-04-02 15:05:18
|
Revision: 785
http://armadeus.svn.sourceforge.net/armadeus/?rev=785&view=rev
Author: FabM
Date: 2008-04-02 08:05:24 -0700 (Wed, 02 Apr 2008)
Log Message:
-----------
[LINUX][DRIVERS] adding GPL, and correct some mistakes
Modified Paths:
--------------
trunk/target/linux/modules/fpga/Wb_button/button.c
trunk/target/linux/modules/fpga/Wb_button/button.h
trunk/target/linux/modules/fpga/Wb_led/led.c
trunk/target/linux/modules/fpga/Wb_led/led.h
trunk/target/linux/modules/fpga/fpga_devtools/fpga-loader.h
Modified: trunk/target/linux/modules/fpga/Wb_button/button.c
===================================================================
--- trunk/target/linux/modules/fpga/Wb_button/button.c 2008-04-02 12:28:13 UTC (rev 784)
+++ trunk/target/linux/modules/fpga/Wb_button/button.c 2008-04-02 15:05:24 UTC (rev 785)
@@ -1,6 +1,24 @@
-/* button.c
- * Driver for bus_led fpga IP
+/*
+ ***********************************************************************
+ *
+ * (c) Copyright 2007 Armadeus project
* Fabien Marteau <fab...@ar...>
+ * Driver for Wb_button IP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
*/
#include "button.h"
@@ -33,12 +51,16 @@
struct button_dev *ldev = dev_id;
u16 data;
- /* wake up reading process */
- if(ldev->reading)up(&ldev->sem);
- /* acknowledge irq_mngr */
- data=1;
- BUG_ON((button_fpga_write(ldev->fpga_virtual_base_address + FPGA_IRQ_ACK,&data,ldev))<0);
+ button_fpga_read(ldev->fpga_virtual_base_address + FPGA_IRQ_PEND,&data,ldev);
+ if(data&WB_BUTTON_IRQ){
+ /* wake up reading process */
+ if(ldev->reading)up(&ldev->sem);
+ /* acknowledge irq_mngr */
+ button_fpga_write(ldev->fpga_virtual_base_address + FPGA_IRQ_ACK,&data,ldev);
+ }
+ PDEBUG("Interrupt raised %x\n",data);
+
return IRQ_HANDLED;
}
@@ -114,6 +136,10 @@
return -ENOMEM;
}
+ /* initiate mutex locked */
+ sdev->reading = 0;
+ init_MUTEX_LOCKED(&sdev->sem);
+
/* Get the major and minor device numbers */
PDEBUG("Get the major and minor device numbers\n");
if(button_major){
@@ -141,25 +167,24 @@
/* Requested I/O memory */
sdev->fpga_virtual_base_address = (void*)IMX_CS1_VIRT;
- /* irq registering */
- if(request_irq(IRQ_GPIOA(1),(irq_handler_t)fpga_interrupt,IRQF_SHARED,FPGA_IRQ_NAME,sdev)<0){
- printk(KERN_ERR "Can't request fpga irq\n");
+ /* irq unmask */
+ data=1;
+ if((result=button_fpga_write(sdev->fpga_virtual_base_address + FPGA_IRQ_MASK,&data,sdev))<0)
goto error;
- }
+
/* irq acknowledge */
data=1;
if((result=button_fpga_write(sdev->fpga_virtual_base_address + FPGA_IRQ_ACK,&data,sdev))<0)
goto error;
- /* irq unmask */
- data=1;
- if((result=button_fpga_write(sdev->fpga_virtual_base_address + FPGA_IRQ_MASK,&data,sdev))<0)
+
+ /* irq registering */
+ printk(KERN_INFO "button: fpga irq shared gpioa 1\n");
+ if(request_irq(IRQ_GPIOA(1),(irq_handler_t)fpga_interrupt,IRQF_SHARED,FPGA_IRQ_NAME,sdev)<0){
+ printk(KERN_ERR "Can't request fpga irq\n");
goto error;
+ }
- /* initiate mutex locked */
- sdev->reading = 0;
- init_MUTEX_LOCKED(&sdev->sem);
-
/* OK module inserted ! */
buttondev = sdev;
printk(KERN_INFO "button module insered\n");
Modified: trunk/target/linux/modules/fpga/Wb_button/button.h
===================================================================
--- trunk/target/linux/modules/fpga/Wb_button/button.h 2008-04-02 12:28:13 UTC (rev 784)
+++ trunk/target/linux/modules/fpga/Wb_button/button.h 2008-04-02 15:05:24 UTC (rev 785)
@@ -1,7 +1,24 @@
-/* button.h
+/*
+ ***********************************************************************
+ *
+ * (c) Copyright 2007 Armadeus project
+ * Fabien Marteau <fab...@ar...>
* Driver for Wb_button IP
- * Fabien Marteau <fab...@ar...>
- * 28 mars 2008
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
*/
@@ -46,13 +63,13 @@
#endif
/* for debugging messages*/
-#define BUTTON_DEBUG
+/*#define BUTTON_DEBUG*/
#undef PDEBUG
#ifdef BUTTON_DEBUG
# ifdef __KERNEL__
/* for kernel spage */
-# define PDEBUG(fmt,args...) printk(KERN_DEBUG "button : " fmt, ##args)
+# define PDEBUG(fmt,args...) printk(KERN_INFO "button : " fmt, ##args)
# else
/* for user space */
# define PDEBUG(fmt,args...) printk(stderr, fmt, ##args)
Modified: trunk/target/linux/modules/fpga/Wb_led/led.c
===================================================================
--- trunk/target/linux/modules/fpga/Wb_led/led.c 2008-04-02 12:28:13 UTC (rev 784)
+++ trunk/target/linux/modules/fpga/Wb_led/led.c 2008-04-02 15:05:24 UTC (rev 785)
@@ -1,6 +1,24 @@
-/* led.c
- * Driver for bus_led fpga IP
+/*
+ ***********************************************************************
+ *
+ * (c) Copyright 2008 Armadeus project
* Fabien Marteau <fab...@ar...>
+ * Driver for Wb_led fpga IP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
*/
#include "led.h"
Modified: trunk/target/linux/modules/fpga/Wb_led/led.h
===================================================================
--- trunk/target/linux/modules/fpga/Wb_led/led.h 2008-04-02 12:28:13 UTC (rev 784)
+++ trunk/target/linux/modules/fpga/Wb_led/led.h 2008-04-02 15:05:24 UTC (rev 785)
@@ -1,6 +1,24 @@
-/* led.h
- * Driver for bus_led IP
+/*
+ ***********************************************************************
+ *
+ * (c) Copyright 2007 Armadeus project
* Fabien Marteau <fab...@ar...>
+ * Driver for Wb_led IP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
*/
Modified: trunk/target/linux/modules/fpga/fpga_devtools/fpga-loader.h
===================================================================
--- trunk/target/linux/modules/fpga/fpga_devtools/fpga-loader.h 2008-04-02 12:28:13 UTC (rev 784)
+++ trunk/target/linux/modules/fpga/fpga_devtools/fpga-loader.h 2008-04-02 15:05:24 UTC (rev 785)
@@ -1,26 +1,26 @@
-/*
- ***********************************************************************
- *
- * (c) Copyright 2006 Armadeus project
- * Julien Boibessot <jul...@ar...>
- * Nicolas Colombain <nic...@ar...>
- * Generic Xilinx FPGA loader
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- **********************************************************************
- */
+/*
+ ***********************************************************************
+ *
+ * (c) Copyright 2006 Armadeus project
+ * Julien Boibessot <jul...@ar...>
+ * Nicolas Colombain <nic...@ar...>
+ * Generic Xilinx FPGA loader
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ **********************************************************************
+ */
#ifndef __FPGA_LOADER_H__
#define __FPGA_LOADER_H__
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <ar...@us...> - 2008-04-02 12:28:34
|
Revision: 784
http://armadeus.svn.sourceforge.net/armadeus/?rev=784&view=rev
Author: artemys
Date: 2008-04-02 05:28:13 -0700 (Wed, 02 Apr 2008)
Log Message:
-----------
[BUILDROOT] Add specific rootfs skeleton & device table for APF27
Modified Paths:
--------------
branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in
Added Paths:
-----------
branches/apf2/buildroot/target/device/armadeus/apf27/device_table.txt
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/bin/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/dev/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/dev/log
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/dev/pts/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/TZ
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/fb.modes
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/fstab
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/group
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/hostname
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/hosts
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S20urandom
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S22i2c
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S40network
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S50mountfs
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/rcS
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/inittab
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/inputrc
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/issue
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/network/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/network/interfaces
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/passwd
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/profile
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/protocols
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/random-seed
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/resolv.conf
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/securetty
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/services
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/shadow
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/home/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/lib/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/mnt/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/mnt/mmc/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/mnt/nfs/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/mnt/smb/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/opt/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/proc/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bash_history
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bash_logout
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bash_profile
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bashrc
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/sbin/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/sys/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/tmp/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/bin/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/lib/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/sbin/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/share/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/share/udhcpc/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/share/udhcpc/default.script
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lib/
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lib/pcmcia
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lock
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/log
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/pcmcia
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/run
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/spool
branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/tmp
Modified: branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in 2008-04-02 11:54:58 UTC (rev 783)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in 2008-04-02 12:28:13 UTC (rev 784)
@@ -1,3 +1,4 @@
+
U-BOOT_TARGET_NAME=apx9328
LINUX_FORMAT=uImage
LINUX_KCONFIG=$(ARMADEUS_CONFIG_PATH)/linux-$(BR2_PACKAGE_LINUX_VERSION).config
@@ -2,2 +3,6 @@
-UCLIBC_CONFIG_FILE:=$(ARMADEUS_PATH)/$(ARMADEUS_TARGET_NAME)/uClibc.config.$(ARCH)
+APF27_TARGET_PATH=$(ARMADEUS_PATH)/apf27
+UCLIBC_CONFIG_FILE:=$(APF27_TARGET_PATH)/uClibc.config.$(ARCH)
+TARGET_SKELETON=$(APF27_TARGET_PATH)/target_skeleton
+TARGET_DEVICE_TABLE=$(APF27_TARGET_PATH)/device_table.txt
+
Added: branches/apf2/buildroot/target/device/armadeus/apf27/device_table.txt
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/device_table.txt (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/device_table.txt 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,186 @@
+# When building a target filesystem, it is desirable to not have to
+# become root and then run 'mknod' a thousand times. Using a device
+# table you can create device nodes and directories "on the fly".
+#
+# This is a sample device table file for use with genext2fs. You can
+# do all sorts of interesting things with a device table file. For
+# example, if you want to adjust the permissions on a particular file
+# you can just add an entry like:
+# /sbin/foobar f 2755 0 0 - - - - -
+# and (assuming the file /sbin/foobar exists) it will be made setuid
+# root (regardless of what its permissions are on the host filesystem.
+# Furthermore, you can use a single table entry to create a many device
+# minors. For example, if I wanted to create /dev/hda and /dev/hda[0-15]
+# I could just use the following two table entries:
+# /dev/hda b 640 0 0 3 0 0 0 -
+# /dev/hda b 640 0 0 3 1 1 1 15
+#
+# Device table entries take the form of:
+# <name> <type> <mode> <uid> <gid> <major> <minor> <start> <inc> <count>
+# where name is the file name, type can be one of:
+# f A regular file
+# d Directory
+# c Character special device file
+# b Block special device file
+# p Fifo (named pipe)
+# uid is the user id for the target file, gid is the group id for the
+# target file. The rest of the entries (major, minor, etc) apply only
+# to device special files.
+
+# Have fun
+# -Erik Andersen <and...@co...>
+#
+
+#<name> <type> <mode> <uid> <gid> <major> <minor> <start> <inc> <count>
+/dev d 755 0 0 - - - - -
+/dev/pts d 755 0 0 - - - - -
+/dev/snd d 755 0 0 - - - - -
+/tmp d 1777 0 0 - - - - -
+/etc d 755 0 0 - - - - -
+/home/default d 2755 1000 1000 - - - - -
+#<name> <type> <mode> <uid> <gid> <major> <minor> <start> <inc> <count>
+/bin/busybox f 4755 0 0 - - - - -
+/etc/shadow f 600 0 0 - - - - -
+/etc/passwd f 644 0 0 - - - - -
+/etc/network/if-up.d d 755 0 0 - - - - -
+/etc/network/if-pre-up.d d 755 0 0 - - - - -
+/etc/network/if-down.d d 755 0 0 - - - - -
+/etc/network/if-post-down.d d 755 0 0 - - - - -
+/usr/share/udhcpc/default.script f 755 0 0 - - - - -
+# uncomment this to allow starting x as non-root
+#/usr/X11R6/bin/Xfbdev f 4755 0 0 - - - - -
+# Normal system devices
+/dev/mem c 640 0 0 1 1 0 0 -
+/dev/kmem c 640 0 0 1 2 0 0 -
+/dev/null c 666 0 0 1 3 0 0 -
+/dev/zero c 666 0 0 1 5 0 0 -
+/dev/random c 666 0 0 1 8 0 0 -
+/dev/urandom c 666 0 0 1 9 0 0 -
+/dev/ram b 640 0 0 1 1 0 0 -
+/dev/ram b 640 0 0 1 0 0 1 4
+/dev/loop b 640 0 0 7 0 0 1 2
+/dev/rtc c 640 0 0 254 0 - - -
+/dev/rtc c 640 0 0 254 0 0 1 3
+/dev/console c 666 0 0 5 1 - - -
+/dev/tty c 666 0 0 5 0 - - -
+/dev/tty c 666 0 0 4 0 0 1 8
+/dev/ttyp c 666 0 0 3 0 0 1 10
+/dev/ptyp c 666 0 0 2 0 0 1 10
+/dev/ptmx c 666 0 0 5 2 - - -
+/dev/ttyP c 666 0 0 57 0 0 1 4
+/dev/ttyS c 666 0 0 4 64 0 1 4
+/dev/ttygserial c 666 0 0 127 0 - - -
+/dev/fb c 640 0 5 29 0 0 32 4
+#/dev/ttySMX c 666 0 0 204 41 0 1 2
+/dev/ttymxc c 666 0 0 207 16 0 1 6
+#/dev/ttySA c 666 0 0 204 5 0 1 3
+/dev/psaux c 666 0 0 10 1 0 0 -
+#/dev/ppp c 666 0 0 108 0 - - -
+
+# MTD stuff
+/dev/mtd c 640 0 0 90 0 0 2 8
+/dev/mtdblock b 640 0 0 31 0 0 1 8
+
+#Tun/tap driver
+/dev/net d 755 0 0 - - - - -
+/dev/net/tun c 660 0 0 10 200 - - -
+
+# Audio stuff
+#/dev/audio c 666 0 29 14 4 - - -
+#/dev/audio1 c 666 0 29 14 20 - - -
+#/dev/dsp c 666 0 29 14 3 - - -
+#/dev/dsp1 c 666 0 29 14 19 - - -
+#/dev/sndstat c 666 0 29 14 6 - - -
+
+/dev/audio c 666 0 29 14 4 - - -
+/dev/audio1 c 666 0 29 14 20 - - -
+/dev/dsp c 666 0 29 14 3 - - -
+/dev/dsp1 c 666 0 29 14 19 - - -
+/dev/sndstat c 666 0 29 14 6 - - -
+/dev/snd/controlC0 c 666 0 29 116 0 - - -
+/dev/snd/pcmC0D0p c 666 0 29 116 16 - - -
+/dev/snd/pcmC0D1p c 666 0 29 116 17 - - -
+/dev/snd/pcmC0D0c c 666 0 29 116 24 - - -
+/dev/snd/timer c 666 0 29 116 33 - - -
+
+# User-mode Linux stuff
+/dev/ubda b 640 0 0 98 0 0 0 -
+/dev/ubda b 640 0 0 98 1 1 1 15
+
+# IDE Devices
+/dev/hda b 640 0 0 3 0 0 0 -
+/dev/hda b 640 0 0 3 1 1 1 15
+#/dev/hdb b 640 0 0 3 64 0 0 -
+#/dev/hdb b 640 0 0 3 65 1 1 15
+#/dev/hdc b 640 0 0 22 0 0 0 -
+#/dev/hdc b 640 0 0 22 1 1 1 15
+#/dev/hdd b 640 0 0 22 64 0 0 -
+#/dev/hdd b 640 0 0 22 65 1 1 15
+#/dev/hde b 640 0 0 33 0 0 0 -
+#/dev/hde b 640 0 0 33 1 1 1 15
+#/dev/hdf b 640 0 0 33 64 0 0 -
+#/dev/hdf b 640 0 0 33 65 1 1 15
+#/dev/hdg b 640 0 0 34 0 0 0 -
+#/dev/hdg b 640 0 0 34 1 1 1 15
+#/dev/hdh b 640 0 0 34 64 0 0 -
+#/dev/hdh b 640 0 0 34 65 1 1 15
+
+# SCSI Devices
+#/dev/sda b 640 0 0 8 0 0 0 -
+#/dev/sda b 640 0 0 8 1 1 1 15
+#/dev/sdb b 640 0 0 8 16 0 0 -
+#/dev/sdb b 640 0 0 8 17 1 1 15
+#/dev/sdc b 640 0 0 8 32 0 0 -
+#/dev/sdc b 640 0 0 8 33 1 1 15
+#/dev/sdd b 640 0 0 8 48 0 0 -
+#/dev/sdd b 640 0 0 8 49 1 1 15
+#/dev/sde b 640 0 0 8 64 0 0 -
+#/dev/sde b 640 0 0 8 65 1 1 15
+#/dev/sdf b 640 0 0 8 80 0 0 -
+#/dev/sdf b 640 0 0 8 81 1 1 15
+#/dev/sdg b 640 0 0 8 96 0 0 -
+#/dev/sdg b 640 0 0 8 97 1 1 15
+#/dev/sdh b 640 0 0 8 112 0 0 -
+#/dev/sdh b 640 0 0 8 113 1 1 15
+#/dev/sg c 640 0 0 21 0 0 1 15
+#/dev/scd b 640 0 0 11 0 0 1 15
+#/dev/st c 640 0 0 9 0 0 1 8
+#/dev/nst c 640 0 0 9 128 0 1 8
+#/dev/st c 640 0 0 9 32 1 1 4
+#/dev/st c 640 0 0 9 64 1 1 4
+#/dev/st c 640 0 0 9 96 1 1 4
+
+# Floppy disk devices
+#/dev/fd b 640 0 0 2 0 0 1 2
+#/dev/fd0d360 b 640 0 0 2 4 0 0 -
+#/dev/fd1d360 b 640 0 0 2 5 0 0 -
+#/dev/fd0h1200 b 640 0 0 2 8 0 0 -
+#/dev/fd1h1200 b 640 0 0 2 9 0 0 -
+#/dev/fd0u1440 b 640 0 0 2 28 0 0 -
+#/dev/fd1u1440 b 640 0 0 2 29 0 0 -
+#/dev/fd0u2880 b 640 0 0 2 32 0 0 -
+#/dev/fd1u2880 b 640 0 0 2 33 0 0 -
+
+# All the proprietary cdrom devices in the world
+#/dev/aztcd b 640 0 0 29 0 0 0 -
+#/dev/bpcd b 640 0 0 41 0 0 0 -
+#/dev/capi20 c 640 0 0 68 0 0 1 2
+#/dev/cdu31a b 640 0 0 15 0 0 0 -
+#/dev/cdu535 b 640 0 0 24 0 0 0 -
+#/dev/cm206cd b 640 0 0 32 0 0 0 -
+#/dev/sjcd b 640 0 0 18 0 0 0 -
+#/dev/sonycd b 640 0 0 15 0 0 0 -
+#/dev/gscd b 640 0 0 16 0 0 0 -
+#/dev/sbpcd b 640 0 0 25 0 0 0 -
+#/dev/sbpcd b 640 0 0 25 0 0 1 4
+#/dev/mcd b 640 0 0 23 0 0 0 -
+#/dev/optcd b 640 0 0 17 0 0 0 -
+
+# I2C bus interface
+ /dev/i2c-0 c 666 0 0 89 0
+
+# MMC/SD Devices
+/dev/mmcblk0 b 640 0 0 179 0 0 0 -
+/dev/mmcblk0p b 640 0 0 179 1 1 1 8
+
+
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/dev/log
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/dev/log (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/dev/log 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+link /tmp/log
\ No newline at end of file
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/dev/log
___________________________________________________________________
Name: svn:special
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/TZ
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/TZ (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/TZ 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+GMT+0
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/fb.modes
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/fb.modes (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/fb.modes 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,15 @@
+# Armadeus default LCD (Microtips):
+mode "320x240-145"
+ # D: 16.000 MHz, H: 38.835 kHz, V: 145.449 Hz
+ geometry 320 240 320 240 16
+ timings 62500 24 38 1 23 30 3
+ rgba 5/11,6/5,5/0,0/0
+endmode
+
+# Sharp LQ057:
+# mode "320x240-176"
+# # D: 16.000 MHz, H: 43.836 kHz, V: 176.047 Hz
+# geometry 320 240 320 240 16
+# timings 62500 9 27 0 7 9 2
+# rgba 5/11,6/5,5/0,0/0
+# endmode
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/fstab
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/fstab (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/fstab 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,9 @@
+# /etc/fstab: static file system information.
+#
+# <file system> <mount pt> <type> <options> <dump> <pass>
+/dev/root / ext2 rw,noauto 0 1
+proc /proc proc defaults 0 0
+devpts /dev/pts devpts defaults,gid=5,mode=620 0 0
+tmpfs /tmp tmpfs defaults 0 0
+sysfs /sys sysfs defaults 0 0
+
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/group
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/group (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/group 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,14 @@
+root:x:0:
+daemon:x:1:
+bin:x:2:
+sys:x:3:
+adm:x:4:
+tty:x:5:
+disk:x:6:
+wheel:x:10:root
+utmp:x:43:
+staff:x:50:
+nobody:x:99:
+nogroup:x:99:
+users:x:100:
+default:x:1000:
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/hostname
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/hostname (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/hostname 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+armadeus
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/hosts
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/hosts (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/hosts 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+127.0.0.1 localhost
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S20urandom
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S20urandom (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S20urandom 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,44 @@
+#! /bin/sh
+#
+# urandom This script saves the random seed between reboots.
+# It is called from the boot, halt and reboot scripts.
+#
+# Version: @(#)urandom 1.33 22-Jun-1998 mi...@ci...
+#
+
+[ -c /dev/urandom ] || exit 0
+#. /etc/default/rcS
+
+case "$1" in
+ start|"")
+ if [ "$VERBOSE" != no ]
+ then
+ echo -n "Initializing random number generator... "
+ fi
+ # Load and then save 512 bytes,
+ # which is the size of the entropy pool
+ if [ -f /etc/random-seed ]
+ then
+ cat /etc/random-seed >/dev/urandom
+ fi
+ rm -f /etc/random-seed
+ umask 077
+ dd if=/dev/urandom of=/etc/random-seed count=1 \
+ >/dev/null 2>&1 || echo "urandom start: failed."
+ umask 022
+ [ "$VERBOSE" != no ] && echo "done."
+ ;;
+ stop)
+ # Carry a random seed from shut-down to start-up;
+ # see documentation in linux/drivers/char/random.c
+ [ "$VERBOSE" != no ] && echo -n "Saving random seed... "
+ umask 077
+ dd if=/dev/urandom of=/etc/random-seed count=1 \
+ >/dev/null 2>&1 || echo "urandom stop: failed."
+ [ "$VERBOSE" != no ] && echo "done."
+ ;;
+ *)
+ echo "Usage: urandom {start|stop}" >&2
+ exit 1
+ ;;
+esac
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S20urandom
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S22i2c
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S22i2c (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S22i2c 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,33 @@
+#!/bin/sh
+#
+# start/stop i2c interface.
+
+test -f /lib/modules/2.6.12/kernel/drivers/i2c/busses/i2c-imx.ko || exit 0
+test -f /lib/modules/2.6.12/kernel/drivers/i2c/i2c-core.ko || exit 0
+test -f /lib/modules/2.6.12/kernel/drivers/i2c/i2c-dev.ko || exit 0
+
+case "$1" in
+ start)
+ echo "Starting i2c drivers"
+ insmod /lib/modules/2.6.12/kernel/drivers/i2c/i2c-core.ko
+ insmod /lib/modules/2.6.12/kernel/drivers/i2c/i2c-dev.ko
+ insmod /lib/modules/2.6.12/kernel/drivers/i2c/busses/i2c-imx.ko
+ ;;
+ stop)
+ echo "Stopping i2c drivers"
+ rmmod /lib/modules/2.6.12/kernel/drivers/i2c/busses/i2c-imx.ko
+ rmmod /lib/modules/2.6.12/kernel/drivers/i2c/i2c-dev.ko
+ rmmod /lib/modules/2.6.12/kernel/drivers/i2c/i2c-core.ko
+ ;;
+ restart)
+ $0 stop
+ $0 start
+ ;;
+ *)
+ echo "Usage: /etc/init.d/S22i2c {start|stop|restart}"
+ exit 1
+ ;;
+esac
+
+exit 0
+
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S22i2c
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S40network
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S40network (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S40network 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,35 @@
+#!/bin/sh
+#
+# Start the network....
+#
+
+start() {
+ echo "Starting network..."
+ /sbin/ifup -a
+}
+stop() {
+ echo -n "Stopping network..."
+ /sbin/ifdown -a
+}
+restart() {
+ stop
+ start
+}
+
+case "$1" in
+ start)
+ start
+ ;;
+ stop)
+ stop
+ ;;
+ restart|reload)
+ restart
+ ;;
+ *)
+ echo $"Usage: $0 {start|stop|restart}"
+ exit 1
+esac
+
+exit $?
+
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S40network
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S50mountfs
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S50mountfs (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S50mountfs 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,27 @@
+#!/bin/sh
+#
+# Mount/unmount all filesystem in /etc/fstab
+
+test -f /etc/fstab || exit 0
+
+case "$1" in
+ start)
+ echo "Mounting all filesystems in /etc/fstab"
+ /bin/mount -a
+ ;;
+ stop)
+ echo "Unmounting all filesystems"
+ /bin/umount -a
+ ;;
+ restart)
+ $0 stop
+ $0 start
+ ;;
+ *)
+ echo "Usage: $0 {start|stop|restart}"
+ exit 1
+ ;;
+esac
+
+exit 0
+
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/S50mountfs
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/rcS
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/rcS (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/rcS 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,27 @@
+#!/bin/sh
+
+
+# Start all init scripts in /etc/init.d
+# executing them in numerical order.
+#
+for i in /etc/init.d/S??* ;do
+
+ # Ignore dangling symlinks (if any).
+ [ ! -f "$i" ] && continue
+
+ case "$i" in
+ *.sh)
+ # Source shell script for speed.
+ (
+ trap - INT QUIT TSTP
+ set start
+ . $i
+ )
+ ;;
+ *)
+ # No sh extension, so fork subprocess.
+ $i start
+ ;;
+ esac
+done
+
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/init.d/rcS
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/inittab
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/inittab (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/inittab 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,50 @@
+# /etc/inittab
+#
+# Copyright (C) 2001 Erik Andersen <and...@co...>
+#
+# Note: BusyBox init doesn't support runlevels. The runlevels field is
+# completely ignored by BusyBox init. If you want runlevels, use
+# sysvinit.
+#
+# Format for each entry: <id>:<runlevels>:<action>:<process>
+#
+# id == tty to run on, or empty for /dev/console
+# runlevels == ignored
+# action == one of sysinit, respawn, askfirst, wait, and once
+# process == program to run
+
+# Startup the system
+null::sysinit:/bin/mount -o remount,rw /
+null::sysinit:/bin/mount -t proc proc /proc
+#null::sysinit:/bin/mount -a
+# fs will be mounted later with init.d/S50mountfs
+null::sysinit:/bin/hostname -F /etc/hostname
+null::sysinit:/sbin/ifconfig lo 127.0.0.1 up
+null::sysinit:/sbin/route add -net 127.0.0.0 netmask 255.0.0.0 lo
+# now run any rc scripts
+::sysinit:/etc/init.d/rcS
+
+# Set up a couple of getty's
+tty1::respawn:/sbin/getty 38400 tty1
+#tty2::respawn:/sbin/getty 38400 tty2
+
+# Put a getty on the serial port
+#ttyS0::respawn:/sbin/getty -L ttySMX0 115200,57600,38400,230400 vt100
+ttymxc0::respawn:/sbin/getty -L ttymxc0 115200,57600,38400 vt100
+#null::respawn:/sbin/getty -L ttygserial 115200 vt100
+
+# Logging junk
+null::sysinit:/bin/touch /var/log/messages
+null::respawn:/sbin/syslogd -n -m 0
+null::respawn:/sbin/klogd -n
+#tty3::respawn:/usr/bin/tail -f /var/log/messages
+
+# Stuff to do for the 3-finger salute
+::ctrlaltdel:/sbin/reboot
+
+# Stuff to do before rebooting
+null::shutdown:/usr/bin/killall klogd
+null::shutdown:/usr/bin/killall syslogd
+null::shutdown:/bin/umount -a -r
+null::shutdown:/sbin/swapoff -a
+
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/inputrc
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/inputrc (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/inputrc 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,44 @@
+# /etc/inputrc - global inputrc for libreadline
+# See readline(3readline) and `info readline' for more information.
+
+# Be 8 bit clean.
+set input-meta on
+set output-meta on
+set bell-style visible
+
+# To allow the use of 8bit-characters like the german umlauts, comment out
+# the line below. However this makes the meta key not work as a meta key,
+# which is annoying to those which don't need to type in 8-bit characters.
+
+# set convert-meta off
+
+"\e0d": backward-word
+"\e0c": forward-word
+"\e[h": beginning-of-line
+"\e[f": end-of-line
+"\e[1~": beginning-of-line
+"\e[4~": end-of-line
+#"\e[5~": beginning-of-history
+#"\e[6~": end-of-history
+"\e[3~": delete-char
+"\e[2~": quoted-insert
+
+# Common standard keypad and cursor
+# (codes courtsey Werner Fink, <we...@su...>)
+#"\e[1~": history-search-backward
+"\e[2~": yank
+"\e[3~": delete-char
+#"\e[4~": set-mark
+"\e[5~": history-search-backward
+"\e[6~": history-search-forward
+# Normal keypad and cursor of xterm
+"\e[F": end-of-line
+"\e[H": beginning-of-line
+# Application keypad and cursor of xterm
+"\eOA": previous-history
+"\eOC": forward-char
+"\eOB": next-history
+"\eOD": backward-char
+"\eOF": end-of-line
+"\eOH": beginning-of-line
+
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/issue
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/issue (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/issue 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,3 @@
+
+Welcome to the Armadeus project.
+
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/network/interfaces
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/network/interfaces (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/network/interfaces 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,4 @@
+# Configure Loopback
+auto lo
+iface lo inet loopback
+
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/passwd
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/passwd (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/passwd 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,13 @@
+root:x:0:0:root:/root:/bin/sh
+daemon:x:1:1:daemon:/usr/sbin:/bin/sh
+bin:x:2:2:bin:/bin:/bin/sh
+sys:x:3:3:sys:/dev:/bin/sh
+sync:x:4:100:sync:/bin:/bin/sync
+mail:x:8:8:mail:/var/spool/mail:/bin/sh
+proxy:x:13:13:proxy:/bin:/bin/sh
+www-data:x:33:33:www-data:/var/www:/bin/sh
+backup:x:34:34:backup:/var/backups:/bin/sh
+operator:x:37:37:Operator:/var:/bin/sh
+sshd:x:103:99:Operator:/var:/bin/sh
+nobody:x:99:99:nobody:/home:/bin/sh
+default:x:1000:1000:Default non-root user:/home/default:/bin/sh
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/profile
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/profile (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/profile 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,48 @@
+# ~/.bashrc: executed by bash(1) for non-login interactive shells.
+
+export PATH=\
+/bin:\
+/sbin:\
+/usr/bin:\
+/usr/sbin:\
+/usr/bin/X11:\
+/usr/local/bin
+
+# If running interactively, then:
+if [ "$PS1" ]; then
+
+ if [ "$BASH" ]; then
+ export PS1="[\u@\h \W]\\$ "
+ alias ll='/bin/ls --color=tty -laFh'
+ alias ls='/bin/ls --color=tty -F'
+ export LS_COLORS='no=00:fi=00:di=01;34:ln=01;36:pi=40;33:so=01;35:do=01;35:bd=40;33;01:cd=40;33;01:or=40;31;01:ex=01;32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.bz2=01;31:*.deb=01;31:*.rpm=01;31:*.jar=01;31:*.jpg=01;35:*.jpeg=01;35:*.png=01;35:*.gif=01;35:*.bmp=01;35:*.pbm=01;35:*.pgm=01;35:*.ppm=01;35:*.tga=01;35:*.xbm=01;35:*.xpm=01;35:*.tif=01;35:*.tiff=01;35:*.mpg=01;35:*.mpeg=01;35:*.avi=01;35:*.fli=01;35:*.gl=01;35:*.dl=01;35:*.xcf=01;35:*.xwd=01;35:';
+ else
+ if [ "`id -u`" -eq 0 ]; then
+ export PS1='# '
+ else
+ export PS1='$ '
+ fi
+ fi
+
+ export USER=`id -un`
+ export LOGNAME=$USER
+ export HOSTNAME=`/bin/hostname`
+ export HISTSIZE=1000
+ export HISTFILESIZE=1000
+ export PAGER='/bin/more '
+ export EDITOR='/bin/vi'
+ export INPUTRC=/etc/inputrc
+ export DMALLOC_OPTIONS=debug=0x34f47d83,inter=100,log=logfile
+
+ ### Some aliases
+ alias ps2='ps facux '
+ alias ps1='ps faxo "%U %t %p %a" '
+ alias af='ps af'
+ alias cls='clear'
+ alias df='df -h'
+ alias indent='indent -bad -bap -bbo -nbc -br -brs -c33 -cd33 -ncdb -ce -ci4 -cli0 -cp33 -cs -d0 -di1 -nfc1 -nfca -hnl -i4 -ip0 -l75 -lp -npcs -npsl -nsc -nsob -nss -ts4 '
+ #alias bc='bc -l'
+ alias minicom='minicom -c on'
+ alias calc='calc -Cd '
+ alias bc='calc -Cd '
+fi;
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/protocols
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/protocols (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/protocols 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,31 @@
+# /etc/protocols:
+# $Id: protocols,v 1.1 2004/10/09 02:49:18 andersen Exp $
+#
+# Internet (IP) protocols
+#
+# from: @(#)protocols 5.1 (Berkeley) 4/17/89
+#
+# Updated for NetBSD based on RFC 1340, Assigned Numbers (July 1992).
+
+ip 0 IP # internet protocol, pseudo protocol number
+icmp 1 ICMP # internet control message protocol
+igmp 2 IGMP # Internet Group Management
+ggp 3 GGP # gateway-gateway protocol
+ipencap 4 IP-ENCAP # IP encapsulated in IP (officially ``IP'')
+st 5 ST # ST datagram mode
+tcp 6 TCP # transmission control protocol
+egp 8 EGP # exterior gateway protocol
+pup 12 PUP # PARC universal packet protocol
+udp 17 UDP # user datagram protocol
+hmp 20 HMP # host monitoring protocol
+xns-idp 22 XNS-IDP # Xerox NS IDP
+rdp 27 RDP # "reliable datagram" protocol
+iso-tp4 29 ISO-TP4 # ISO Transport Protocol class 4
+xtp 36 XTP # Xpress Tranfer Protocol
+ddp 37 DDP # Datagram Delivery Protocol
+idpr-cmtp 39 IDPR-CMTP # IDPR Control Message Transport
+rspf 73 RSPF #Radio Shortest Path First.
+vmtp 81 VMTP # Versatile Message Transport
+ospf 89 OSPFIGP # Open Shortest Path First IGP
+ipip 94 IPIP # Yet Another IP encapsulation
+encap 98 ENCAP # Yet Another IP encapsulation
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/random-seed
===================================================================
(Binary files differ)
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/random-seed
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/resolv.conf
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/resolv.conf (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/resolv.conf 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,2 @@
+domain dev.null
+nameserver 127.0.0.1
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/securetty
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/securetty (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/securetty 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,15 @@
+tty1
+tty2
+tty3
+tty4
+tty5
+tty6
+tty7
+tty8
+ttyS0
+ttyS1
+ttyS2
+ttyS3
+ttymxc0
+ttymxc1
+ttygserial
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/services
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/services (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/services 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,302 @@
+# /etc/services:
+# $Id: services,v 1.1 2004/10/09 02:49:18 andersen Exp $
+#
+# Network services, Internet style
+#
+# Note that it is presently the policy of IANA to assign a single well-known
+# port number for both TCP and UDP; hence, most entries here have two entries
+# even if the protocol doesn't support UDP operations.
+# Updated from RFC 1700, ``Assigned Numbers'' (October 1994). Not all ports
+# are included, only the more common ones.
+
+tcpmux 1/tcp # TCP port service multiplexer
+echo 7/tcp
+echo 7/udp
+discard 9/tcp sink null
+discard 9/udp sink null
+systat 11/tcp users
+daytime 13/tcp
+daytime 13/udp
+netstat 15/tcp
+qotd 17/tcp quote
+msp 18/tcp # message send protocol
+msp 18/udp # message send protocol
+chargen 19/tcp ttytst source
+chargen 19/udp ttytst source
+ftp-data 20/tcp
+ftp 21/tcp
+fsp 21/udp fspd
+ssh 22/tcp # SSH Remote Login Protocol
+ssh 22/udp # SSH Remote Login Protocol
+telnet 23/tcp
+# 24 - private
+smtp 25/tcp mail
+# 26 - unassigned
+time 37/tcp timserver
+time 37/udp timserver
+rlp 39/udp resource # resource location
+nameserver 42/tcp name # IEN 116
+whois 43/tcp nicname
+re-mail-ck 50/tcp # Remote Mail Checking Protocol
+re-mail-ck 50/udp # Remote Mail Checking Protocol
+domain 53/tcp nameserver # name-domain server
+domain 53/udp nameserver
+mtp 57/tcp # deprecated
+bootps 67/tcp # BOOTP server
+bootps 67/udp
+bootpc 68/tcp # BOOTP client
+bootpc 68/udp
+tftp 69/udp
+gopher 70/tcp # Internet Gopher
+gopher 70/udp
+rje 77/tcp netrjs
+finger 79/tcp
+www 80/tcp http # WorldWideWeb HTTP
+www 80/udp # HyperText Transfer Protocol
+link 87/tcp ttylink
+kerberos 88/tcp kerberos5 krb5 # Kerberos v5
+kerberos 88/udp kerberos5 krb5 # Kerberos v5
+supdup 95/tcp
+# 100 - reserved
+hostnames 101/tcp hostname # usually from sri-nic
+iso-tsap 102/tcp tsap # part of ISODE.
+csnet-ns 105/tcp cso-ns # also used by CSO name server
+csnet-ns 105/udp cso-ns
+# unfortunately the poppassd (Eudora) uses a port which has already
+# been assigned to a different service. We list the poppassd as an
+# alias here. This should work for programs asking for this service.
+# (due to a bug in inetd the 3com-tsmux line is disabled)
+#3com-tsmux 106/tcp poppassd
+#3com-tsmux 106/udp poppassd
+rtelnet 107/tcp # Remote Telnet
+rtelnet 107/udp
+pop-2 109/tcp postoffice # POP version 2
+pop-2 109/udp
+pop-3 110/tcp # POP version 3
+pop-3 110/udp
+sunrpc 111/tcp portmapper # RPC 4.0 portmapper TCP
+sunrpc 111/udp portmapper # RPC 4.0 portmapper UDP
+auth 113/tcp authentication tap ident
+sftp 115/tcp
+uucp-path 117/tcp
+nntp 119/tcp readnews untp # USENET News Transfer Protocol
+ntp 123/tcp
+ntp 123/udp # Network Time Protocol
+netbios-ns 137/tcp # NETBIOS Name Service
+netbios-ns 137/udp
+netbios-dgm 138/tcp # NETBIOS Datagram Service
+netbios-dgm 138/udp
+netbios-ssn 139/tcp # NETBIOS session service
+netbios-ssn 139/udp
+imap2 143/tcp # Interim Mail Access Proto v2
+imap2 143/udp
+snmp 161/udp # Simple Net Mgmt Proto
+snmp-trap 162/udp snmptrap # Traps for SNMP
+cmip-man 163/tcp # ISO mgmt over IP (CMOT)
+cmip-man 163/udp
+cmip-agent 164/tcp
+cmip-agent 164/udp
+xdmcp 177/tcp # X Display Mgr. Control Proto
+xdmcp 177/udp
+nextstep 178/tcp NeXTStep NextStep # NeXTStep window
+nextstep 178/udp NeXTStep NextStep # server
+bgp 179/tcp # Border Gateway Proto.
+bgp 179/udp
+prospero 191/tcp # Cliff Neuman's Prospero
+prospero 191/udp
+irc 194/tcp # Internet Relay Chat
+irc 194/udp
+smux 199/tcp # SNMP Unix Multiplexer
+smux 199/udp
+at-rtmp 201/tcp # AppleTalk routing
+at-rtmp 201/udp
+at-nbp 202/tcp # AppleTalk name binding
+at-nbp 202/udp
+at-echo 204/tcp # AppleTalk echo
+at-echo 204/udp
+at-zis 206/tcp # AppleTalk zone information
+at-zis 206/udp
+qmtp 209/tcp # The Quick Mail Transfer Protocol
+qmtp 209/udp # The Quick Mail Transfer Protocol
+z3950 210/tcp wais # NISO Z39.50 database
+z3950 210/udp wais
+ipx 213/tcp # IPX
+ipx 213/udp
+imap3 220/tcp # Interactive Mail Access
+imap3 220/udp # Protocol v3
+ulistserv 372/tcp # UNIX Listserv
+ulistserv 372/udp
+https 443/tcp # MCom
+https 443/udp # MCom
+snpp 444/tcp # Simple Network Paging Protocol
+snpp 444/udp # Simple Network Paging Protocol
+saft 487/tcp # Simple Asynchronous File Transfer
+saft 487/udp # Simple Asynchronous File Transfer
+npmp-local 610/tcp dqs313_qmaster # npmp-local / DQS
+npmp-local 610/udp dqs313_qmaster # npmp-local / DQS
+npmp-gui 611/tcp dqs313_execd # npmp-gui / DQS
+npmp-gui 611/udp dqs313_execd # npmp-gui / DQS
+hmmp-ind 612/tcp dqs313_intercell# HMMP Indication / DQS
+hmmp-ind 612/udp dqs313_intercell# HMMP Indication / DQS
+#
+# UNIX specific services
+#
+exec 512/tcp
+biff 512/udp comsat
+login 513/tcp
+who 513/udp whod
+shell 514/tcp cmd # no passwords used
+syslog 514/udp
+printer 515/tcp spooler # line printer spooler
+talk 517/udp
+ntalk 518/udp
+route 520/udp router routed # RIP
+timed 525/udp timeserver
+tempo 526/tcp newdate
+courier 530/tcp rpc
+conference 531/tcp chat
+netnews 532/tcp readnews
+netwall 533/udp # -for emergency broadcasts
+uucp 540/tcp uucpd # uucp daemon
+afpovertcp 548/tcp # AFP over TCP
+afpovertcp 548/udp # AFP over TCP
+remotefs 556/tcp rfs_server rfs # Brunhoff remote filesystem
+klogin 543/tcp # Kerberized `rlogin' (v5)
+kshell 544/tcp krcmd # Kerberized `rsh' (v5)
+kerberos-adm 749/tcp # Kerberos `kadmin' (v5)
+#
+webster 765/tcp # Network dictionary
+webster 765/udp
+#
+# From ``Assigned Numbers'':
+#
+#> The Registered Ports are not controlled by the IANA and on most systems
+#> can be used by ordinary user processes or programs executed by ordinary
+#> users.
+#
+#> Ports are used in the TCP [45,106] to name the ends of logical
+#> connections which carry long term conversations. For the purpose of
+#> providing services to unknown callers, a service contact port is
+#> defined. This list specifies the port used by the server process as its
+#> contact port. While the IANA can not control uses of these ports it
+#> does register or list uses of these ports as a convienence to the
+#> community.
+#
+nfsdstatus 1110/tcp
+nfsd-keepalive 1110/udp
+
+ingreslock 1524/tcp
+ingreslock 1524/udp
+prospero-np 1525/tcp # Prospero non-privileged
+prospero-np 1525/udp
+datametrics 1645/tcp old-radius # datametrics / old radius entry
+datametrics 1645/udp old-radius # datametrics / old radius entry
+sa-msg-port 1646/tcp old-radacct # sa-msg-port / old radacct entry
+sa-msg-port 1646/udp old-radacct # sa-msg-port / old radacct entry
+radius 1812/tcp # Radius
+radius 1812/udp # Radius
+radacct 1813/tcp # Radius Accounting
+radacct 1813/udp # Radius Accounting
+nfsd 2049/tcp nfs
+nfsd 2049/udp nfs
+cvspserver 2401/tcp # CVS client/server operations
+cvspserver 2401/udp # CVS client/server operations
+mysql 3306/tcp # MySQL
+mysql 3306/udp # MySQL
+rfe 5002/tcp # Radio Free Ethernet
+rfe 5002/udp # Actually uses UDP only
+cfengine 5308/tcp # CFengine
+cfengine 5308/udp # CFengine
+bbs 7000/tcp # BBS service
+#
+#
+# Kerberos (Project Athena/MIT) services
+# Note that these are for Kerberos v4, and are unofficial. Sites running
+# v4 should uncomment these and comment out the v5 entries above.
+#
+kerberos4 750/udp kerberos-iv kdc # Kerberos (server) udp
+kerberos4 750/tcp kerberos-iv kdc # Kerberos (server) tcp
+kerberos_master 751/udp # Kerberos authentication
+kerberos_master 751/tcp # Kerberos authentication
+passwd_server 752/udp # Kerberos passwd server
+krb_prop 754/tcp # Kerberos slave propagation
+krbupdate 760/tcp kreg # Kerberos registration
+kpasswd 761/tcp kpwd # Kerberos "passwd"
+kpop 1109/tcp # Pop with Kerberos
+knetd 2053/tcp # Kerberos de-multiplexor
+zephyr-srv 2102/udp # Zephyr server
+zephyr-clt 2103/udp # Zephyr serv-hm connection
+zephyr-hm 2104/udp # Zephyr hostmanager
+eklogin 2105/tcp # Kerberos encrypted rlogin
+#
+# Unofficial but necessary (for NetBSD) services
+#
+supfilesrv 871/tcp # SUP server
+supfiledbg 1127/tcp # SUP debugging
+#
+# Datagram Delivery Protocol services
+#
+rtmp 1/ddp # Routing Table Maintenance Protocol
+nbp 2/ddp # Name Binding Protocol
+echo 4/ddp # AppleTalk Echo Protocol
+zip 6/ddp # Zone Information Protocol
+#
+# Services added for the Debian GNU/Linux distribution
+poppassd 106/tcp # Eudora
+poppassd 106/udp # Eudora
+mailq 174/tcp # Mailer transport queue for Zmailer
+mailq 174/tcp # Mailer transport queue for Zmailer
+omirr 808/tcp omirrd # online mirror
+omirr 808/udp omirrd # online mirror
+rmtcfg 1236/tcp # Gracilis Packeten remote config server
+xtel 1313/tcp # french minitel
+coda_opcons 1355/udp # Coda opcons (Coda fs)
+coda_venus 1363/udp # Coda venus (Coda fs)
+coda_auth 1357/udp # Coda auth (Coda fs)
+coda_udpsrv 1359/udp # Coda udpsrv (Coda fs)
+coda_filesrv 1361/udp # Coda filesrv (Coda fs)
+codacon 1423/tcp venus.cmu # Coda Console (Coda fs)
+coda_aux1 1431/tcp # coda auxiliary service (Coda fs)
+coda_aux1 1431/udp # coda auxiliary service (Coda fs)
+coda_aux2 1433/tcp # coda auxiliary service (Coda fs)
+coda_aux2 1433/udp # coda auxiliary service (Coda fs)
+coda_aux3 1435/tcp # coda auxiliary service (Coda fs)
+coda_aux3 1435/udp # coda auxiliary service (Coda fs)
+cfinger 2003/tcp # GNU Finger
+afbackup 2988/tcp # Afbackup system
+afbackup 2988/udp # Afbackup system
+icp 3130/tcp # Internet Cache Protocol (Squid)
+icp 3130/udp # Internet Cache Protocol (Squid)
+postgres 5432/tcp # POSTGRES
+postgres 5432/udp # POSTGRES
+fax 4557/tcp # FAX transmission service (old)
+hylafax 4559/tcp # HylaFAX client-server protocol (new)
+noclog 5354/tcp # noclogd with TCP (nocol)
+noclog 5354/udp # noclogd with UDP (nocol)
+hostmon 5355/tcp # hostmon uses TCP (nocol)
+hostmon 5355/udp # hostmon uses TCP (nocol)
+ircd 6667/tcp # Internet Relay Chat
+ircd 6667/udp # Internet Relay Chat
+webcache 8080/tcp # WWW caching service
+webcache 8080/udp # WWW caching service
+tproxy 8081/tcp # Transparent Proxy
+tproxy 8081/udp # Transparent Proxy
+mandelspawn 9359/udp mandelbrot # network mandelbrot
+amanda 10080/udp # amanda backup services
+amandaidx 10082/tcp # amanda backup services
+amidxtape 10083/tcp # amanda backup services
+isdnlog 20011/tcp # isdn logging system
+isdnlog 20011/udp # isdn logging system
+vboxd 20012/tcp # voice box system
+vboxd 20012/udp # voice box system
+binkp 24554/tcp # Binkley
+binkp 24554/udp # Binkley
+asp 27374/tcp # Address Search Protocol
+asp 27374/udp # Address Search Protocol
+tfido 60177/tcp # Ifmail
+tfido 60177/udp # Ifmail
+fido 60179/tcp # Ifmail
+fido 60179/udp # Ifmail
+
+# Local services
+
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/shadow
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/shadow (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/etc/shadow 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,12 @@
+root::10933:0:99999:7:::
+bin:*:10933:0:99999:7:::
+daemon:*:10933:0:99999:7:::
+adm:*:10933:0:99999:7:::
+lp:*:10933:0:99999:7:::
+sync:*:10933:0:99999:7:::
+shutdown:*:10933:0:99999:7:::
+halt:*:10933:0:99999:7:::
+uucp:*:10933:0:99999:7:::
+operator:*:10933:0:99999:7:::
+nobody:*:10933:0:99999:7:::
+default::10933:0:99999:7:::
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bash_history
===================================================================
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bash_logout
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bash_logout (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bash_logout 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,7 @@
+# ~/.bash_logout: executed by bash(1) when login shell exits.
+
+# when leaving the console clear the screen to increase privacy
+
+case "`tty`" in
+ /dev/tty[0-9]*) clear
+esac
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bash_profile
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bash_profile (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bash_profile 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,15 @@
+# .bash_profile
+
+export PATH=\
+/bin:\
+/sbin:\
+/usr/bin:\
+/usr/sbin:\
+/usr/bin/X11:\
+/usr/local/bin
+
+umask 022
+
+if [ -f ~/.bashrc ]; then
+ source ~/.bashrc
+fi
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bashrc
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bashrc (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/root/.bashrc 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,48 @@
+# ~/.bashrc: executed by bash(1) for non-login interactive shells.
+
+export PATH=\
+/bin:\
+/sbin:\
+/usr/bin:\
+/usr/sbin:\
+/usr/bin/X11:\
+/usr/local/bin
+
+# If running interactively, then:
+if [ "$PS1" ]; then
+
+ if [ "$BASH" ]; then
+ export PS1="[\u@\h \W]\\$ "
+ else
+ if [ "`id -u`" -eq 0 ]; then
+ export PS1='# '
+ else
+ export PS1='$ '
+ fi
+ fi
+
+ export USER=`id -un`
+ export LOGNAME=$USER
+ export HOSTNAME=`/bin/hostname`
+ export HISTSIZE=1000
+ export HISTFILESIZE=1000
+ export PAGER='/bin/more '
+ export EDITOR='/bin/vi'
+ export INPUTRC=/etc/inputrc
+ export DMALLOC_OPTIONS=debug=0x34f47d83,inter=100,log=logfile
+ export LS_COLORS='no=00:fi=00:di=01;34:ln=01;36:pi=40;33:so=01;35:do=01;35:bd=40;33;01:cd=40;33;01:or=40;31;01:ex=01;32:*.tar=01;31:*.tgz=01;31:*.arj=01;31:*.taz=01;31:*.lzh=01;31:*.zip=01;31:*.z=01;31:*.Z=01;31:*.gz=01;31:*.bz2=01;31:*.deb=01;31:*.rpm=01;31:*.jar=01;31:*.jpg=01;35:*.jpeg=01;35:*.png=01;35:*.gif=01;35:*.bmp=01;35:*.pbm=01;35:*.pgm=01;35:*.ppm=01;35:*.tga=01;35:*.xbm=01;35:*.xpm=01;35:*.tif=01;35:*.tiff=01;35:*.mpg=01;35:*.mpeg=01;35:*.avi=01;35:*.fli=01;35:*.gl=01;35:*.dl=01;35:*.xcf=01;35:*.xwd=01;35:';
+
+ ### Some aliases
+ alias ps2='ps facux '
+ alias ps1='ps faxo "%U %t %p %a" '
+ alias af='ps af'
+ alias cls='clear'
+ alias ll='/bin/ls -laFh'
+ alias ls='/bin/ls -F'
+ alias df='df -h'
+ alias indent='indent -bad -bap -bbo -nbc -br -brs -c33 -cd33 -ncdb -ce -ci4 -cli0 -cp33 -cs -d0 -di1 -nfc1 -nfca -hnl -i4 -ip0 -l75 -lp -npcs -npsl -nsc -nsob -nss -ts4 '
+ #alias bc='bc -l'
+ alias minicom='minicom -c on'
+ alias calc='calc -Cd '
+ alias bc='calc -Cd '
+fi;
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/share/udhcpc/default.script
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/share/udhcpc/default.script (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/share/udhcpc/default.script 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1,39 @@
+#!/bin/sh
+
+# udhcpc script edited by Tim Riker <Ti...@Ri...>
+
+[ -z "$1" ] && echo "Error: should be called from udhcpc" && exit 1
+
+RESOLV_CONF="/etc/resolv.conf"
+[ -n "$broadcast" ] && BROADCAST="broadcast $broadcast"
+[ -n "$subnet" ] && NETMASK="netmask $subnet"
+
+case "$1" in
+ deconfig)
+ /sbin/ifconfig $interface 0.0.0.0
+ ;;
+
+ renew|bound)
+ /sbin/ifconfig $interface $ip $BROADCAST $NETMASK
+
+ if [ -n "$router" ] ; then
+ echo "deleting routers"
+ while route del default gw 0.0.0.0 dev $interface ; do
+ :
+ done
+
+ for i in $router ; do
+ route add default gw $i dev $interface
+ done
+ fi
+
+ echo -n > $RESOLV_CONF
+ [ -n "$domain" ] && echo search $domain >> $RESOLV_CONF
+ for i in $dns ; do
+ echo adding dns $i
+ echo nameserver $i >> $RESOLV_CONF
+ done
+ ;;
+esac
+
+exit 0
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/usr/share/udhcpc/default.script
___________________________________________________________________
Name: svn:executable
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lib/pcmcia
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lib/pcmcia (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lib/pcmcia 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+link ../../tmp
\ No newline at end of file
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lib/pcmcia
___________________________________________________________________
Name: svn:special
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lock
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lock (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lock 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+link ../tmp
\ No newline at end of file
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/lock
___________________________________________________________________
Name: svn:special
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/log
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/log (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/log 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+link ../tmp
\ No newline at end of file
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/log
___________________________________________________________________
Name: svn:special
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/pcmcia
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/pcmcia (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/pcmcia 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+link ../tmp
\ No newline at end of file
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/pcmcia
___________________________________________________________________
Name: svn:special
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/run
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/run (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/run 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+link ../tmp
\ No newline at end of file
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/run
___________________________________________________________________
Name: svn:special
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/spool
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/spool (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/spool 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+link ../tmp
\ No newline at end of file
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/spool
___________________________________________________________________
Name: svn:special
+ *
Added: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/tmp
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/tmp (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/tmp 2008-04-02 12:28:13 UTC (rev 784)
@@ -0,0 +1 @@
+link ../tmp
\ No newline at end of file
Property changes on: branches/apf2/buildroot/target/device/armadeus/apf27/target_skeleton/var/tmp
___________________________________________________________________
Name: svn:special
+ *
This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site.
|
|
From: <ar...@us...> - 2008-04-02 11:54:52
|
Revision: 783
http://armadeus.svn.sourceforge.net/armadeus/?rev=783&view=rev
Author: artemys
Date: 2008-04-02 04:54:58 -0700 (Wed, 02 Apr 2008)
Log Message:
-----------
[LINUX] Add support for i.MX27 Ethernet controller (old but working driver)
Added Paths:
-----------
branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/220-apf27-pengu-fec-old.diff
Added: branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/220-apf27-pengu-fec-old.diff
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/220-apf27-pengu-fec-old.diff (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/linux/kernel-patches/2.6.25-rc7/220-apf27-pengu-fec-old.diff 2008-04-02 11:54:58 UTC (rev 783)
@@ -0,0 +1,3402 @@
+Subject: [@num@/@total@] i.MX27: Adding network support (reference only)
+From: Juergen Beisert <j.b...@pe...>
+
+This patch adds network support for the phyCORE-i.MX27 cpu module (aka
+pcm038). The patch is here for reference only and to make it possible
+for people to actually work with the board. It is more or less a copy of
+the original ifdef-cluttered patch from Freescale, cleaned up to only
+contain i.MX27-FEC code and does not even follow the driver model
+correctly. Has to be reworked before it can go into the mainline.
+
+The FEC is similar to that one on the MPC5200B; we don't know if it is
+worth the effort to merge it with the mpc-fec code. Oppinions?
+
+Signed-off-by: Juergen Beisert <j.b...@pe...>
+
+---
+
+ drivers/net/Kconfig | 7
+ drivers/net/Makefile | 1
+ drivers/net/fec_old.c | 3164 ++++++++++++++++++++++++++++++++++++++++++++++++++
+ drivers/net/fec_old.h | 175 ++
+ 4 files changed, 3347 insertions(+)
+
+Index: drivers/net/Makefile
+===================================================================
+--- linux/drivers/net/Makefile.orig
++++ linux/drivers/net/Makefile
+@@ -104,6 +104,7 @@ obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx
+ ifeq ($(CONFIG_FEC_MPC52xx_MDIO),y)
+ obj-$(CONFIG_FEC_MPC52xx) += fec_mpc52xx_phy.o
+ endif
++obj-$(CONFIG_FEC_OLD) += fec_old.o
+ obj-$(CONFIG_68360_ENET) += 68360enet.o
+ obj-$(CONFIG_WD80x3) += wd.o 8390.o
+ obj-$(CONFIG_EL2) += 3c503.o 8390.o
+Index: drivers/net/Kconfig
+===================================================================
+--- linux/drivers/net/Kconfig.orig
++++ linux/drivers/net/Kconfig
+@@ -1884,6 +1884,13 @@ config FEC_MPC52xx_MDIO
+ If not sure, enable.
+ If compiled as module, it will be called 'fec_mpc52xx_phy.ko'.
+
++config FEC_OLD
++ tristate "FEC ethernet controller"
++ depends on ARCH_MX2
++ help
++ Say Y here if you want to use the built-in 10/100 Fast ethernet
++ controller on some Motorola/Freescale processors.
++
+ config NE_H8300
+ tristate "NE2000 compatible support for H8/300"
+ depends on H8300
+Index: drivers/net/fec_old.c
+===================================================================
+--- /dev/null
++++ linux/drivers/net/fec_old.c
+@@ -0,0 +1,3164 @@
++/*
++ * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
++ * Copyright (c) 1997 Dan Malek (dm...@jl...)
++ *
++ * This version of the driver is specific to the FADS implementation,
++ * since the board contains control registers external to the processor
++ * for the control of the LevelOne LXT970 transceiver. The MPC860T manual
++ * describes connections using the internal parallel port I/O, which
++ * is basically all of Port D.
++ *
++ * Right now, I am very wasteful with the buffers. I allocate memory
++ * pages and then divide them into 2K frame buffers. This way I know I
++ * have buffers large enough to hold one frame within one buffer descriptor.
++ * Once I get this working, I will use 64 or 128 byte CPM buffers, which
++ * will be much more memory efficient and will easily handle lots of
++ * small packets.
++ *
++ * Much better multiple PHY support by Magnus Damm.
++ * Copyright (c) 2000 Ericsson Radio Systems AB.
++ *
++ * Support for FEC controller of ColdFire processors.
++ * Copyright (c) 2001-2005 Greg Ungerer (ge...@sn...)
++ *
++ * Bug fixes and cleanup by Philippe De Muyter (ph...@ma...)
++ * Copyright (c) 2004-2006 Macq Electronique SA.
++ */
++/*
++ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/ptrace.h>
++#include <linux/errno.h>
++#include <linux/ioport.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/pci.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/spinlock.h>
++#include <linux/workqueue.h>
++#include <linux/bitops.h>
++#include <linux/clk.h>
++#include <linux/kthread.h>
++#include <linux/delay.h>
++
++#include <asm/irq.h>
++#include <asm/uaccess.h>
++#include <asm/io.h>
++#include <asm/pgtable.h>
++
++#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
++ defined(CONFIG_M5272) || defined(CONFIG_M528x) || \
++ defined(CONFIG_M520x) || defined(CONFIG_M532x)
++#include <asm/coldfire.h>
++#include <asm/mcfsim.h>
++#include "fec_old.h"
++#define FEC_ALIGNMENT (0x03) /*FEC needs 4bytes alignment*/
++#elif defined(CONFIG_ARCH_MXC)
++#include <asm/arch/hardware.h>
++#include <asm/arch/iim.h>
++#include "fec_old.h"
++#define FEC_ALIGNMENT (0x0F) /*FEC needs 128bits(32bytes) alignment*/
++#else
++#include <asm/8xx_immap.h>
++#include <asm/mpc8xx.h>
++#include "commproc.h"
++#define FEC_ALIGNMENT (0x03) /*FEC needs 4bytes alignment */
++#endif
++
++#define FEC_ADDR_ALIGNMENT(x) ((unsigned char *)(((unsigned long )(x) + (FEC_ALIGNMENT)) & (~FEC_ALIGNMENT)))
++
++#if defined(CONFIG_FEC2)
++#define FEC_MAX_PORTS 2
++#else
++#define FEC_MAX_PORTS 1
++#endif
++
++/*
++ * Define the fixed address of the FEC hardware.
++ */
++static unsigned int fec_hw[] = {
++#if defined(CONFIG_M5272)
++ (MCF_MBAR + 0x840),
++#elif defined(CONFIG_M527x)
++ (MCF_MBAR + 0x1000),
++ (MCF_MBAR + 0x1800),
++#elif defined(CONFIG_M523x) || defined(CONFIG_M528x)
++ (MCF_MBAR + 0x1000),
++#elif defined(CONFIG_M520x)
++ (MCF_MBAR+0x30000),
++#elif defined(CONFIG_M532x)
++ (MCF_MBAR+0xfc030000),
++#elif defined(CONFIG_ARCH_MXC)
++ (IO_ADDRESS(FEC_BASE_ADDR)),
++#else
++ &(((immap_t *)IMAP_ADDR)->im_cpm.cp_fec),
++#endif
++};
++
++static unsigned char fec_mac_default[] = {
++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++};
++
++/*
++ * Some hardware gets it MAC address out of local flash memory.
++ * if this is non-zero then assume it is the address to get MAC from.
++ */
++#if defined(CONFIG_NETtel)
++#define FEC_FLASHMAC 0xf0006006
++#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
++#define FEC_FLASHMAC 0xf0006000
++#elif defined (CONFIG_MTD_KeyTechnology)
++#define FEC_FLASHMAC 0xffe04000
++#elif defined(CONFIG_CANCam)
++#define FEC_FLASHMAC 0xf0020000
++#elif defined (CONFIG_M5272C3)
++#define FEC_FLASHMAC (0xffe04000 + 4)
++#elif defined(CONFIG_MOD5272)
++#define FEC_FLASHMAC 0xffc0406b
++#else
++#define FEC_FLASHMAC 0
++#endif
++
++/* Forward declarations of some structures to support different PHYs
++*/
++
++typedef struct {
++ uint mii_data;
++ void (*funct)(uint mii_reg, struct net_device *dev);
++} phy_cmd_t;
++
++typedef struct {
++ uint id;
++ char *name;
++
++ const phy_cmd_t *config;
++ const phy_cmd_t *startup;
++ const phy_cmd_t *ack_int;
++ const phy_cmd_t *shutdown;
++} phy_info_t;
++
++/* The number of Tx and Rx buffers. These are allocated from the page
++ * pool. The code may assume these are power of two, so it it best
++ * to keep them that size.
++ * We don't need to allocate pages for the transmitter. We just use
++ * the skbuffer directly.
++ */
++#define FEC_ENET_RX_PAGES 8
++#define FEC_ENET_RX_FRSIZE 2048
++#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
++#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
++#define FEC_ENET_TX_FRSIZE 2048
++#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
++#define TX_RING_SIZE 16 /* Must be power of two */
++#define TX_RING_MOD_MASK 15 /* for this to work */
++
++#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
++#error "FEC: descriptor ring size constants too large"
++#endif
++
++/* Interrupt events/masks.
++*/
++#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
++#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
++#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
++#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
++#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
++#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
++#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
++#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
++#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
++#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
++
++#ifndef CONFIG_ARCH_MXC
++#define FEC_ENET_MASK ((uint)0xffc00000)
++#else
++#define FEC_ENET_MASK ((uint)0xfff80000)
++#endif
++
++/* The FEC stores dest/src/type, data, and checksum for receive packets.
++ */
++#define PKT_MAXBUF_SIZE 1518
++#define PKT_MINBUF_SIZE 64
++#define PKT_MAXBLR_SIZE 1520
++
++
++/*
++ * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
++ * size bits. Other FEC hardware does not, so we need to take that into
++ * account when setting it.
++ */
++#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
++ defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
++#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
++#else
++#define OPT_FRAME_SIZE 0
++#endif
++
++/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
++ * tx_bd_base always point to the base of the buffer descriptors. The
++ * cur_rx and cur_tx point to the currently available buffer.
++ * The dirty_tx tracks the current buffer that is being sent by the
++ * controller. The cur_tx and dirty_tx are equal under both completely
++ * empty and completely full conditions. The empty/ready indicator in
++ * the buffer descriptor determines the actual condition.
++ */
++struct fec_enet_private {
++ /* Hardware registers of the FEC device */
++ volatile fec_t *hwp;
++
++ struct net_device *netdev;
++
++ /* The saved address of a sent-in-place packet/buffer, for skfree(). */
++ unsigned char *tx_bounce[TX_RING_SIZE];
++ struct sk_buff* tx_skbuff[TX_RING_SIZE];
++ struct sk_buff* rx_skbuff[RX_RING_SIZE];
++ ushort skb_cur;
++ ushort skb_dirty;
++
++ /* CPM dual port RAM relative addresses.
++ */
++ void * cbd_mem_base; /* save the virtual base address of rx&tx buffer descripter */
++ cbd_t *rx_bd_base; /* Address of Rx and Tx buffers. */
++ cbd_t *tx_bd_base;
++ cbd_t *cur_rx, *cur_tx; /* The next free ring entry */
++ cbd_t *dirty_tx; /* The ring entries to be free()ed. */
++ struct net_device_stats stats;
++ uint tx_full;
++ spinlock_t lock;
++
++ uint phy_id;
++ uint phy_id_done;
++ uint phy_status;
++ uint phy_speed;
++ phy_info_t const *phy;
++ struct work_struct phy_task;
++
++ uint sequence_done;
++ uint mii_phy_task_queued;
++
++ uint phy_addr;
++
++ int index;
++ int opened;
++ int link;
++ int old_link;
++ int full_duplex;
++
++ struct clk *clk;
++};
++
++static int fec_enet_open(struct net_device *dev);
++static int fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev);
++static void fec_enet_mii(struct net_device *dev);
++static irqreturn_t fec_enet_interrupt(int irq, void * dev_id);
++static void fec_enet_tx(struct net_device *dev);
++static void fec_enet_rx(struct net_device *dev);
++static int fec_enet_close(struct net_device *dev);
++static struct net_device_stats *fec_enet_get_stats(struct net_device *dev);
++static void set_multicast_list(struct net_device *dev);
++static void fec_restart(struct net_device *dev, int duplex);
++static void fec_stop(struct net_device *dev);
++static void fec_set_mac_address(struct net_device *dev);
++
++static void __inline__ fec_dcache_inv_range(void * start, void * end);
++static void __inline__ fec_dcache_flush_range(void * start, void * end);
++
++/*
++ * fec_copy_threshold controls the copy when recieving ethernet frame.
++ * If ethernet header aligns 4bytes, the ip header and upper header will not aligns 4bytes.
++ * The resean is ethernet header is 14bytes.
++ * And the max size of tcp & ip header is 128bytes. Normally it is 40bytes.
++ * So I set the default value between 128 to 256.
++ */
++static int fec_copy_threshold = 192;
++
++/*
++ * fec_device records the devices created for cleanup
++ */
++struct net_device *fec_device[FEC_MAX_PORTS];
++
++/* MII processing. We keep this as simple as possible. Requests are
++ * placed on the list (if there is room). When the request is finished
++ * by the MII, an optional function may be called.
++ */
++typedef struct mii_list {
++ uint mii_regval;
++ void (*mii_func)(uint val, struct net_device *dev);
++ struct mii_list *mii_next;
++} mii_list_t;
++
++#define NMII 20
++static mii_list_t mii_cmds[NMII];
++static mii_list_t *mii_free;
++static mii_list_t *mii_head;
++static mii_list_t *mii_tail;
++
++static int mii_queue(struct net_device *dev, int request,
++ void (*func)(uint, struct net_device *));
++
++/* Make MII read/write commands for the FEC.
++*/
++#define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
++#define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | \
++ (VAL & 0xffff))
++#define mk_mii_end 0
++
++/* Transmitter timeout.
++*/
++#define TX_TIMEOUT (2*HZ)
++
++/* Register definitions for the PHY.
++*/
++
++#define MII_REG_CR 0 /* Control Register */
++#define MII_REG_SR 1 /* Status Register */
++#define MII_REG_PHYIR1 2 /* PHY Identification Register 1 */
++#define MII_REG_PHYIR2 3 /* PHY Identification Register 2 */
++#define MII_REG_ANAR 4 /* A-N Advertisement Register */
++#define MII_REG_ANLPAR 5 /* A-N Link Partner Ability Register */
++#define MII_REG_ANER 6 /* A-N Expansion Register */
++#define MII_REG_ANNPTR 7 /* A-N Next Page Transmit Register */
++#define MII_REG_ANLPRNPR 8 /* A-N Link Partner Received Next Page Reg. */
++
++/* values for phy_status */
++
++#define PHY_CONF_ANE 0x0001 /* 1 auto-negotiation enabled */
++#define PHY_CONF_LOOP 0x0002 /* 1 loopback mode enabled */
++#define PHY_CONF_SPMASK 0x00f0 /* mask for speed */
++#define PHY_CONF_10HDX 0x0010 /* 10 Mbit half duplex supported */
++#define PHY_CONF_10FDX 0x0020 /* 10 Mbit full duplex supported */
++#define PHY_CONF_100HDX 0x0040 /* 100 Mbit half duplex supported */
++#define PHY_CONF_100FDX 0x0080 /* 100 Mbit full duplex supported */
++
++#define PHY_STAT_LINK 0x0100 /* 1 up - 0 down */
++#define PHY_STAT_FAULT 0x0200 /* 1 remote fault */
++#define PHY_STAT_ANC 0x0400 /* 1 auto-negotiation complete */
++#define PHY_STAT_SPMASK 0xf000 /* mask for speed */
++#define PHY_STAT_10HDX 0x1000 /* 10 Mbit half duplex selected */
++#define PHY_STAT_10FDX 0x2000 /* 10 Mbit full duplex selected */
++#define PHY_STAT_100HDX 0x4000 /* 100 Mbit half duplex selected */
++#define PHY_STAT_100FDX 0x8000 /* 100 Mbit full duplex selected */
++
++
++static int
++fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++ struct fec_enet_private *fep;
++ volatile fec_t *fecp;
++ volatile cbd_t *bdp;
++ unsigned short status;
++
++ fep = netdev_priv(dev);
++ fecp = (volatile fec_t*)dev->base_addr;
++
++ if (!fep->link) {
++ /* Link is down or autonegotiation is in progress. */
++ return 1;
++ }
++
++ /* Fill in a Tx ring entry */
++ bdp = fep->cur_tx;
++
++ status = bdp->cbd_sc;
++#ifndef final_version
++ if (status & BD_ENET_TX_READY) {
++ /* Ooops. All transmit buffers are full. Bail out.
++ * This should not happen, since dev->tbusy should be set.
++ */
++ printk("%s: tx queue full!.\n", dev->name);
++ return 1;
++ }
++#endif
++
++ /* Clear all of the status flags.
++ */
++ status &= ~BD_ENET_TX_STATS;
++
++ /* Set buffer length and buffer pointer.
++ */
++ bdp->cbd_bufaddr = __pa(skb->data);
++ bdp->cbd_datlen = skb->len;
++
++ /*
++ * On some FEC implementations data must be aligned on
++ * 4-byte boundaries. Use bounce buffers to copy data
++ * and get it aligned. Ugh.
++ */
++ if ((bdp->cbd_bufaddr) & FEC_ALIGNMENT) {
++ unsigned int index;
++ index = bdp - fep->tx_bd_base;
++ memcpy(fep->tx_bounce[index], (void *) skb->data, skb->len);
++ bdp->cbd_bufaddr = __pa(fep->tx_bounce[index]);
++ }
++
++ /* Save skb pointer.
++ */
++ fep->tx_skbuff[fep->skb_cur] = skb;
++
++ fep->stats.tx_bytes += skb->len;
++ fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
++
++ /* Push the data cache so the CPM does not get stale memory
++ * data.
++ */
++ fec_dcache_flush_range(__va(bdp->cbd_bufaddr), __va(bdp->cbd_bufaddr) +
++ bdp->cbd_datlen);
++
++ spin_lock_irq(&fep->lock);
++
++ /* Send it on its way. Tell FEC it's ready, interrupt when done,
++ * it's the last BD of the frame, and to put the CRC on the end.
++ */
++
++ status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
++ | BD_ENET_TX_LAST | BD_ENET_TX_TC);
++ bdp->cbd_sc = status;
++
++ dev->trans_start = jiffies;
++
++ /* Trigger transmission start */
++ fecp->fec_x_des_active = 0x01000000;
++
++ /* If this was the last BD in the ring, start at the beginning again.
++ */
++ if (status & BD_ENET_TX_WRAP) {
++ bdp = fep->tx_bd_base;
++ } else {
++ bdp++;
++ }
++
++ if (bdp == fep->dirty_tx) {
++ fep->tx_full = 1;
++ netif_stop_queue(dev);
++ }
++
++ fep->cur_tx = (cbd_t *)bdp;
++
++ spin_unlock_irq(&fep->lock);
++
++ return 0;
++}
++
++static void
++fec_timeout(struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++
++ printk("%s: transmit timed out.\n", dev->name);
++ fep->stats.tx_errors++;
++#ifndef final_version
++ {
++ int i;
++ cbd_t *bdp;
++
++ printk("Ring data dump: cur_tx %lx%s, dirty_tx %lx cur_rx: %lx\n",
++ (unsigned long)fep->cur_tx, fep->tx_full ? " (full)" : "",
++ (unsigned long)fep->dirty_tx,
++ (unsigned long)fep->cur_rx);
++
++ bdp = fep->tx_bd_base;
++ printk(" tx: %u buffers\n", TX_RING_SIZE);
++ for (i = 0 ; i < TX_RING_SIZE; i++) {
++ printk(" %08x: %04x %04x %08x\n",
++ (uint) bdp,
++ bdp->cbd_sc,
++ bdp->cbd_datlen,
++ (int) bdp->cbd_bufaddr);
++ bdp++;
++ }
++
++ bdp = fep->rx_bd_base;
++ printk(" rx: %lu buffers\n", (unsigned long) RX_RING_SIZE);
++ for (i = 0 ; i < RX_RING_SIZE; i++) {
++ printk(" %08x: %04x %04x %08x\n",
++ (uint) bdp,
++ bdp->cbd_sc,
++ bdp->cbd_datlen,
++ (int) bdp->cbd_bufaddr);
++ bdp++;
++ }
++ }
++#endif
++ fec_restart(dev, fep->full_duplex);
++ netif_wake_queue(dev);
++}
++
++/* The interrupt handler.
++ * This is called from the MPC core interrupt.
++ */
++static irqreturn_t
++fec_enet_interrupt(int irq, void * dev_id)
++{
++ struct net_device *dev = dev_id;
++ volatile fec_t *fecp;
++ uint int_events;
++ int handled = 0;
++
++ fecp = (volatile fec_t*)dev->base_addr;
++ /* Get the interrupt events that caused us to be here.
++ */
++ while ((int_events = fecp->fec_ievent) != 0) {
++ fecp->fec_ievent = int_events;
++
++ /* Handle receive event in its own function.
++ */
++ if (int_events & (FEC_ENET_RXF | FEC_ENET_RXB)) {
++
++ handled = 1;
++ fec_enet_rx(dev);
++ }
++
++ /* Transmit OK, or non-fatal error. Update the buffer
++ descriptors. FEC handles all errors, we just discover
++ them as part of the transmit process.
++ */
++ if (int_events & (FEC_ENET_TXF | FEC_ENET_TXB)) {
++ handled = 1;
++ fec_enet_tx(dev);
++ }
++
++ if (int_events & FEC_ENET_MII) {
++ handled = 1;
++ fec_enet_mii(dev);
++ }
++
++ }
++ return IRQ_RETVAL(handled);
++}
++
++
++static void
++fec_enet_tx(struct net_device *dev)
++{
++ struct fec_enet_private *fep;
++ volatile cbd_t *bdp;
++ unsigned short status;
++ struct sk_buff *skb;
++
++ fep = netdev_priv(dev);
++ spin_lock(&fep->lock);
++ bdp = fep->dirty_tx;
++
++ while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
++ if (bdp == fep->cur_tx && fep->tx_full == 0) break;
++
++ skb = fep->tx_skbuff[fep->skb_dirty];
++ /* Check for errors. */
++ if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
++ BD_ENET_TX_RL | BD_ENET_TX_UN |
++ BD_ENET_TX_CSL)) {
++ fep->stats.tx_errors++;
++ if (status & BD_ENET_TX_HB) /* No heartbeat */
++ fep->stats.tx_heartbeat_errors++;
++ if (status & BD_ENET_TX_LC) /* Late collision */
++ fep->stats.tx_window_errors++;
++ if (status & BD_ENET_TX_RL) /* Retrans limit */
++ fep->stats.tx_aborted_errors++;
++ if (status & BD_ENET_TX_UN) /* Underrun */
++ fep->stats.tx_fifo_errors++;
++ if (status & BD_ENET_TX_CSL) /* Carrier lost */
++ fep->stats.tx_carrier_errors++;
++ } else {
++ fep->stats.tx_packets++;
++ }
++
++#ifndef final_version
++ if (status & BD_ENET_TX_READY)
++ printk("HEY! Enet xmit interrupt and TX_READY.\n");
++#endif
++ /* Deferred means some collisions occurred during transmit,
++ * but we eventually sent the packet OK.
++ */
++ if (status & BD_ENET_TX_DEF)
++ fep->stats.collisions++;
++
++ /* Free the sk buffer associated with this last transmit.
++ */
++ dev_kfree_skb_any(skb);
++ fep->tx_skbuff[fep->skb_dirty] = NULL;
++ fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
++
++ /* Update pointer to next buffer descriptor to be transmitted.
++ */
++ if (status & BD_ENET_TX_WRAP)
++ bdp = fep->tx_bd_base;
++ else
++ bdp++;
++
++ /* Since we have freed up a buffer, the ring is no longer
++ * full.
++ */
++ if (fep->tx_full) {
++ fep->tx_full = 0;
++ if (netif_queue_stopped(dev))
++ netif_wake_queue(dev);
++ }
++ }
++ fep->dirty_tx = (cbd_t *)bdp;
++ spin_unlock(&fep->lock);
++}
++
++
++/* During a receive, the cur_rx points to the current incoming buffer.
++ * When we update through the ring, if the next incoming buffer has
++ * not been given to the system, we just set the empty indicator,
++ * effectively tossing the packet.
++ */
++static void
++fec_enet_rx(struct net_device *dev)
++{
++ struct fec_enet_private *fep;
++ volatile fec_t *fecp;
++ volatile cbd_t *bdp;
++ unsigned short status;
++ struct sk_buff *skb;
++ ushort pkt_len;
++ __u8 *data;
++ int rx_index;
++
++#ifdef CONFIG_M532x
++ flush_cache_all();
++#endif
++
++ fep = netdev_priv(dev);
++ fecp = (volatile fec_t*)dev->base_addr;
++
++ /* First, grab all of the stats for the incoming packet.
++ * These get messed up if we get called due to a busy condition.
++ */
++ bdp = fep->cur_rx;
++
++while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
++ rx_index = bdp - fep->rx_bd_base;
++#ifndef final_version
++ /* Since we have allocated space to hold a complete frame,
++ * the last indicator should be set.
++ */
++ if ((status & BD_ENET_RX_LAST) == 0)
++ printk("FEC ENET: rcv is not +last\n");
++#endif
++
++ if (!fep->opened)
++ goto rx_processing_done;
++
++ /* Check for errors. */
++ if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
++ BD_ENET_RX_CR | BD_ENET_RX_OV)) {
++ fep->stats.rx_errors++;
++ if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
++ /* Frame too long or too short. */
++ fep->stats.rx_length_errors++;
++ }
++ if (status & BD_ENET_RX_NO) /* Frame alignment */
++ fep->stats.rx_frame_errors++;
++ if (status & BD_ENET_RX_CR) /* CRC Error */
++ fep->stats.rx_crc_errors++;
++ if (status & BD_ENET_RX_OV) /* FIFO overrun */
++ fep->stats.rx_fifo_errors++;
++ }
++
++ /* Report late collisions as a frame error.
++ * On this error, the BD is closed, but we don't know what we
++ * have in the buffer. So, just drop this frame on the floor.
++ */
++ if (status & BD_ENET_RX_CL) {
++ fep->stats.rx_errors++;
++ fep->stats.rx_frame_errors++;
++ goto rx_processing_done;
++ }
++
++ /* Process the incoming frame.
++ */
++ fep->stats.rx_packets++;
++ pkt_len = bdp->cbd_datlen;
++ fep->stats.rx_bytes += pkt_len;
++ data = (__u8*)__va(bdp->cbd_bufaddr);
++ fec_dcache_inv_range(data, data + pkt_len - 4);
++
++ /* This does 16 byte alignment, exactly what we need.
++ * The packet length includes FCS, but we don't want to
++ * include that when passing upstream as it messes up
++ * bridging applications.
++ */
++ if ((pkt_len - 4) < fec_copy_threshold) {
++ skb = dev_alloc_skb(pkt_len);
++ } else {
++ skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
++ }
++
++ if (skb == NULL) {
++ printk("%s: Memory squeeze, dropping packet.\n", dev->name);
++ fep->stats.rx_dropped++;
++ } else {
++ if ((pkt_len - 4) < fec_copy_threshold) {
++ skb_reserve(skb, 2); /*skip 2bytes, so ipheader is align 4bytes*/
++ skb_put(skb,pkt_len-4); /* Make room */
++ skb_copy_to_linear_data(skb, (unsigned char *)data,
++ pkt_len-4);
++ } else {
++ struct sk_buff *pskb = fep->rx_skbuff[rx_index];
++
++ fep->rx_skbuff[rx_index] = skb;
++ skb->data = FEC_ADDR_ALIGNMENT(skb->data);
++ bdp->cbd_bufaddr = __pa(skb->data);
++ skb_put(pskb,pkt_len-4); /* Make room */
++ skb = pskb;
++ }
++ skb->dev = dev;
++ skb->protocol=eth_type_trans(skb,dev);
++ netif_rx(skb);
++ }
++ rx_processing_done:
++
++ /* Clear the status flags for this buffer.
++ */
++ status &= ~BD_ENET_RX_STATS;
++
++ /* Mark the buffer empty.
++ */
++ status |= BD_ENET_RX_EMPTY;
++ bdp->cbd_sc = status;
++
++ /* Update BD pointer to next entry.
++ */
++ if (status & BD_ENET_RX_WRAP)
++ bdp = fep->rx_bd_base;
++ else
++ bdp++;
++
++#if 1
++ /* Doing this here will keep the FEC running while we process
++ * incoming frames. On a heavily loaded network, we should be
++ * able to keep up at the expense of system resources.
++ */
++ fecp->fec_r_des_active = 0x01000000;
++#endif
++ } /* while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) */
++ fep->cur_rx = (cbd_t *)bdp;
++
++#if 0
++ /* Doing this here will allow us to process all frames in the
++ * ring before the FEC is allowed to put more there. On a heavily
++ * loaded network, some frames may be lost. Unfortunately, this
++ * increases the interrupt overhead since we can potentially work
++ * our way back to the interrupt return only to come right back
++ * here.
++ */
++ fecp->fec_r_des_active = 0;
++#endif
++}
++
++
++/* called from interrupt context */
++static void
++fec_enet_mii(struct net_device *dev)
++{
++ struct fec_enet_private *fep;
++ volatile fec_t *ep;
++ mii_list_t *mip;
++ uint mii_reg;
++
++ fep = netdev_priv(dev);
++ ep = fep->hwp;
++ mii_reg = ep->fec_mii_data;
++
++ spin_lock(&fep->lock);
++
++ if ((mip = mii_head) == NULL) {
++ printk("MII and no head!\n");
++ goto unlock;
++ }
++
++ if (mip->mii_func != NULL)
++ (*(mip->mii_func))(mii_reg, dev);
++
++ mii_head = mip->mii_next;
++ mip->mii_next = mii_free;
++ mii_free = mip;
++
++ if ((mip = mii_head) != NULL)
++ ep->fec_mii_data = mip->mii_regval;
++
++unlock:
++ spin_unlock(&fep->lock);
++}
++
++static int
++mii_queue(struct net_device *dev, int regval, void (*func)(uint, struct net_device *))
++{
++ struct fec_enet_private *fep;
++ unsigned long flags;
++ mii_list_t *mip;
++ int retval;
++
++ /* Add PHY address to register command.
++ */
++ fep = netdev_priv(dev);
++ regval |= fep->phy_addr << 23;
++
++ retval = 0;
++
++ spin_lock_irqsave(&fep->lock,flags);
++
++ if ((mip = mii_free) != NULL) {
++ mii_free = mip->mii_next;
++ mip->mii_regval = regval;
++ mip->mii_func = func;
++ mip->mii_next = NULL;
++ if (mii_head) {
++ mii_tail->mii_next = mip;
++ mii_tail = mip;
++ }
++ else {
++ mii_head = mii_tail = mip;
++ fep->hwp->fec_mii_data = regval;
++ }
++ }
++ else {
++ retval = 1;
++ }
++
++ spin_unlock_irqrestore(&fep->lock,flags);
++
++ return(retval);
++}
++
++static void mii_do_cmd(struct net_device *dev, const phy_cmd_t *c)
++{
++ int k;
++
++ if(!c)
++ return;
++
++ for(k = 0; (c+k)->mii_data != mk_mii_end; k++) {
++ mii_queue(dev, (c+k)->mii_data, (c+k)->funct);
++ }
++}
++
++static void mii_parse_sr(uint mii_reg, struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile uint *s = &(fep->phy_status);
++ uint status;
++
++ status = *s & ~(PHY_STAT_LINK | PHY_STAT_FAULT | PHY_STAT_ANC);
++
++ if (mii_reg & 0x0004)
++ status |= PHY_STAT_LINK;
++ if (mii_reg & 0x0010)
++ status |= PHY_STAT_FAULT;
++ if (mii_reg & 0x0020)
++ status |= PHY_STAT_ANC;
++
++ *s = status;
++}
++
++static void mii_parse_cr(uint mii_reg, struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile uint *s = &(fep->phy_status);
++ uint status;
++ status = *s & ~(PHY_CONF_ANE | PHY_CONF_LOOP);
++
++
++ if (mii_reg & 0x1000)
++ status |= PHY_CONF_ANE;
++ if (mii_reg & 0x4000)
++ status |= PHY_CONF_LOOP;
++ *s = status;
++}
++
++static void mii_parse_anar(uint mii_reg, struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile uint *s = &(fep->phy_status);
++ uint status;
++ status = *s & ~(PHY_CONF_SPMASK);
++
++
++ if (mii_reg & 0x0020)
++ status |= PHY_CONF_10HDX;
++ if (mii_reg & 0x0040)
++ status |= PHY_CONF_10FDX;
++ if (mii_reg & 0x0080)
++ status |= PHY_CONF_100HDX;
++ if (mii_reg & 0x00100)
++ status |= PHY_CONF_100FDX;
++ *s = status;
++}
++
++/* ------------------------------------------------------------------------- */
++/* The Level one LXT970 is used by many boards */
++
++#define MII_LXT970_MIRROR 16 /* Mirror register */
++#define MII_LXT970_IER 17 /* Interrupt Enable Register */
++#define MII_LXT970_ISR 18 /* Interrupt Status Register */
++#define MII_LXT970_CONFIG 19 /* Configuration Register */
++#define MII_LXT970_CSR 20 /* Chip Status Register */
++
++static void mii_parse_lxt970_csr(uint mii_reg, struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile uint *s = &(fep->phy_status);
++ uint status;
++
++ status = *s & ~(PHY_STAT_SPMASK);
++ if (mii_reg & 0x0800) {
++ if (mii_reg & 0x1000)
++ status |= PHY_STAT_100FDX;
++ else
++ status |= PHY_STAT_100HDX;
++ } else {
++ if (mii_reg & 0x1000)
++ status |= PHY_STAT_10FDX;
++ else
++ status |= PHY_STAT_10HDX;
++ }
++ *s = status;
++}
++
++static phy_cmd_t const phy_cmd_lxt970_config[] = {
++ { mk_mii_read(MII_REG_CR), mii_parse_cr },
++ { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_lxt970_startup[] = { /* enable interrupts */
++ { mk_mii_write(MII_LXT970_IER, 0x0002), NULL },
++ { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_lxt970_ack_int[] = {
++ /* read SR and ISR to acknowledge */
++ { mk_mii_read(MII_REG_SR), mii_parse_sr },
++ { mk_mii_read(MII_LXT970_ISR), NULL },
++
++ /* find out the current status */
++ { mk_mii_read(MII_LXT970_CSR), mii_parse_lxt970_csr },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_lxt970_shutdown[] = { /* disable interrupts */
++ { mk_mii_write(MII_LXT970_IER, 0x0000), NULL },
++ { mk_mii_end, }
++ };
++static phy_info_t const phy_info_lxt970 = {
++ .id = 0x07810000,
++ .name = "LXT970",
++ .config = phy_cmd_lxt970_config,
++ .startup = phy_cmd_lxt970_startup,
++ .ack_int = phy_cmd_lxt970_ack_int,
++ .shutdown = phy_cmd_lxt970_shutdown
++};
++
++/* ------------------------------------------------------------------------- */
++/* The Level one LXT971 is used on some of my custom boards */
++
++/* register definitions for the 971 */
++
++#define MII_LXT971_PCR 16 /* Port Control Register */
++#define MII_LXT971_SR2 17 /* Status Register 2 */
++#define MII_LXT971_IER 18 /* Interrupt Enable Register */
++#define MII_LXT971_ISR 19 /* Interrupt Status Register */
++#define MII_LXT971_LCR 20 /* LED Control Register */
++#define MII_LXT971_TCR 30 /* Transmit Control Register */
++
++/*
++ * I had some nice ideas of running the MDIO faster...
++ * The 971 should support 8MHz and I tried it, but things acted really
++ * weird, so 2.5 MHz ought to be enough for anyone...
++ */
++
++static void mii_parse_lxt971_sr2(uint mii_reg, struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile uint *s = &(fep->phy_status);
++ uint status;
++
++ status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
++
++ if (mii_reg & 0x0400) {
++ fep->link = 1;
++ status |= PHY_STAT_LINK;
++ } else {
++ fep->link = 0;
++ }
++ if (mii_reg & 0x0080)
++ status |= PHY_STAT_ANC;
++ if (mii_reg & 0x4000) {
++ if (mii_reg & 0x0200)
++ status |= PHY_STAT_100FDX;
++ else
++ status |= PHY_STAT_100HDX;
++ } else {
++ if (mii_reg & 0x0200)
++ status |= PHY_STAT_10FDX;
++ else
++ status |= PHY_STAT_10HDX;
++ }
++ if (mii_reg & 0x0008)
++ status |= PHY_STAT_FAULT;
++
++ *s = status;
++}
++
++static phy_cmd_t const phy_cmd_lxt971_config[] = {
++ /* limit to 10MBit because my prototype board
++ * doesn't work with 100. */
++ { mk_mii_read(MII_REG_CR), mii_parse_cr },
++ { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
++ { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_lxt971_startup[] = { /* enable interrupts */
++ { mk_mii_write(MII_LXT971_IER, 0x00f2), NULL },
++ { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
++ { mk_mii_write(MII_LXT971_LCR, 0xd422), NULL }, /* LED config */
++ /* Somehow does the 971 tell me that the link is down
++ * the first read after power-up.
++ * read here to get a valid value in ack_int */
++ { mk_mii_read(MII_REG_SR), mii_parse_sr },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_lxt971_ack_int[] = {
++ /* acknowledge the int before reading status ! */
++ { mk_mii_read(MII_LXT971_ISR), NULL },
++ /* find out the current status */
++ { mk_mii_read(MII_REG_SR), mii_parse_sr },
++ { mk_mii_read(MII_LXT971_SR2), mii_parse_lxt971_sr2 },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_lxt971_shutdown[] = { /* disable interrupts */
++ { mk_mii_write(MII_LXT971_IER, 0x0000), NULL },
++ { mk_mii_end, }
++ };
++static phy_info_t const phy_info_lxt971 = {
++ .id = 0x0001378e,
++ .name = "LXT971",
++ .config = phy_cmd_lxt971_config,
++ .startup = phy_cmd_lxt971_startup,
++ .ack_int = phy_cmd_lxt971_ack_int,
++ .shutdown = phy_cmd_lxt971_shutdown
++};
++
++/* ------------------------------------------------------------------------- */
++/* The Quality Semiconductor QS6612 is used on the RPX CLLF */
++
++/* register definitions */
++
++#define MII_QS6612_MCR 17 /* Mode Control Register */
++#define MII_QS6612_FTR 27 /* Factory Test Register */
++#define MII_QS6612_MCO 28 /* Misc. Control Register */
++#define MII_QS6612_ISR 29 /* Interrupt Source Register */
++#define MII_QS6612_IMR 30 /* Interrupt Mask Register */
++#define MII_QS6612_PCR 31 /* 100BaseTx PHY Control Reg. */
++
++static void mii_parse_qs6612_pcr(uint mii_reg, struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile uint *s = &(fep->phy_status);
++ uint status;
++
++ status = *s & ~(PHY_STAT_SPMASK);
++
++ switch((mii_reg >> 2) & 7) {
++ case 1: status |= PHY_STAT_10HDX; break;
++ case 2: status |= PHY_STAT_100HDX; break;
++ case 5: status |= PHY_STAT_10FDX; break;
++ case 6: status |= PHY_STAT_100FDX; break;
++}
++
++ *s = status;
++}
++
++static phy_cmd_t const phy_cmd_qs6612_config[] = {
++ /* The PHY powers up isolated on the RPX,
++ * so send a command to allow operation.
++ */
++ { mk_mii_write(MII_QS6612_PCR, 0x0dc0), NULL },
++
++ /* parse cr and anar to get some info */
++ { mk_mii_read(MII_REG_CR), mii_parse_cr },
++ { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_qs6612_startup[] = { /* enable interrupts */
++ { mk_mii_write(MII_QS6612_IMR, 0x003a), NULL },
++ { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_qs6612_ack_int[] = {
++ /* we need to read ISR, SR and ANER to acknowledge */
++ { mk_mii_read(MII_QS6612_ISR), NULL },
++ { mk_mii_read(MII_REG_SR), mii_parse_sr },
++ { mk_mii_read(MII_REG_ANER), NULL },
++
++ /* read pcr to get info */
++ { mk_mii_read(MII_QS6612_PCR), mii_parse_qs6612_pcr },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_qs6612_shutdown[] = { /* disable interrupts */
++ { mk_mii_write(MII_QS6612_IMR, 0x0000), NULL },
++ { mk_mii_end, }
++ };
++static phy_info_t const phy_info_qs6612 = {
++ .id = 0x00181440,
++ .name = "QS6612",
++ .config = phy_cmd_qs6612_config,
++ .startup = phy_cmd_qs6612_startup,
++ .ack_int = phy_cmd_qs6612_ack_int,
++ .shutdown = phy_cmd_qs6612_shutdown
++};
++
++/* ------------------------------------------------------------------------- */
++/* AMD AM79C874 phy */
++
++/* register definitions for the 874 */
++
++#define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
++#define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
++#define MII_AM79C874_DR 18 /* Diagnostic Register */
++#define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
++#define MII_AM79C874_MCR 21 /* ModeControl Register */
++#define MII_AM79C874_DC 23 /* Disconnect Counter */
++#define MII_AM79C874_REC 24 /* Recieve Error Counter */
++
++static void mii_parse_am79c874_dr(uint mii_reg, struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile uint *s = &(fep->phy_status);
++ uint status;
++
++ status = *s & ~(PHY_STAT_SPMASK | PHY_STAT_ANC);
++
++ if (mii_reg & 0x0080)
++ status |= PHY_STAT_ANC;
++ if (mii_reg & 0x0400)
++ status |= ((mii_reg & 0x0800) ? PHY_STAT_100FDX : PHY_STAT_100HDX);
++ else
++ status |= ((mii_reg & 0x0800) ? PHY_STAT_10FDX : PHY_STAT_10HDX);
++
++ *s = status;
++}
++
++static phy_cmd_t const phy_cmd_am79c874_config[] = {
++ { mk_mii_read(MII_REG_CR), mii_parse_cr },
++ { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
++ { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_am79c874_startup[] = { /* enable interrupts */
++ { mk_mii_write(MII_AM79C874_ICSR, 0xff00), NULL },
++ { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
++ { mk_mii_read(MII_REG_SR), mii_parse_sr },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_am79c874_ack_int[] = {
++ /* find out the current status */
++ { mk_mii_read(MII_REG_SR), mii_parse_sr },
++ { mk_mii_read(MII_AM79C874_DR), mii_parse_am79c874_dr },
++ /* we only need to read ISR to acknowledge */
++ { mk_mii_read(MII_AM79C874_ICSR), NULL },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_am79c874_shutdown[] = { /* disable interrupts */
++ { mk_mii_write(MII_AM79C874_ICSR, 0x0000), NULL },
++ { mk_mii_end, }
++ };
++static phy_info_t const phy_info_am79c874 = {
++ .id = 0x00022561,
++ .name = "AM79C874",
++ .config = phy_cmd_am79c874_config,
++ .startup = phy_cmd_am79c874_startup,
++ .ack_int = phy_cmd_am79c874_ack_int,
++ .shutdown = phy_cmd_am79c874_shutdown
++};
++
++
++/* ------------------------------------------------------------------------- */
++/* Kendin KS8721BL phy */
++
++/* register definitions for the 8721 */
++
++#define MII_KS8721BL_RXERCR 21
++#define MII_KS8721BL_ICSR 27
++#define MII_KS8721BL_PHYCR 31
++
++static phy_cmd_t const phy_cmd_ks8721bl_config[] = {
++ { mk_mii_read(MII_REG_CR), mii_parse_cr },
++ { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_ks8721bl_startup[] = { /* enable interrupts */
++/* { mk_mii_write(MII_KS8721BL_ICSR, 0xff00), NULL }, */
++ { mk_mii_write(MII_REG_ANAR, 0x01E1), NULL},
++ { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
++ { mk_mii_read(MII_REG_SR), mii_parse_sr },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_ks8721bl_ack_int[] = {
++ /* find out the current status */
++ { mk_mii_read(MII_REG_SR), mii_parse_sr },
++ /* we only need to read ISR to acknowledge */
++ { mk_mii_read(MII_KS8721BL_ICSR), NULL },
++ { mk_mii_end, }
++ };
++static phy_cmd_t const phy_cmd_ks8721bl_shutdown[] = { /* disable interrupts */
++ { mk_mii_write(MII_KS8721BL_ICSR, 0x0000), NULL },
++ { mk_mii_end, }
++ };
++static phy_info_t const phy_info_ks8721bl = {
++ .id = 0x00022161,
++ .name = "KS8721BL",
++ .config = phy_cmd_ks8721bl_config,
++ .startup = phy_cmd_ks8721bl_startup,
++ .ack_int = phy_cmd_ks8721bl_ack_int,
++ .shutdown = phy_cmd_ks8721bl_shutdown
++};
++
++/* ------------------------------------------------------------------------- */
++/* register definitions for the DP83848 */
++
++#define MII_DP8384X_PHYSTST 16 /* PHY Status Register */
++
++static void mii_parse_dp8384x_sr2(uint mii_reg, struct net_device *dev)
++{
++ struct fec_enet_private *fep = dev->priv;
++ volatile uint *s = &(fep->phy_status);
++
++ *s &= ~(PHY_STAT_SPMASK | PHY_STAT_LINK | PHY_STAT_ANC);
++
++ /* Link up */
++ if (mii_reg & 0x0001) {
++ fep->link = 1;
++ *s |= PHY_STAT_LINK;
++ } else
++ fep->link = 0;
++ /* Status of link */
++ if (mii_reg & 0x0010) /* Autonegotioation complete */
++ *s |= PHY_STAT_ANC;
++ if (mii_reg & 0x0002) { /* 10MBps? */
++ if (mii_reg & 0x0004) /* Full Duplex? */
++ *s |= PHY_STAT_10FDX;
++ else
++ *s |= PHY_STAT_10HDX;
++ } else { /* 100 Mbps? */
++ if (mii_reg & 0x0004) /* Full Duplex? */
++ *s |= PHY_STAT_100FDX;
++ else
++ *s |= PHY_STAT_100HDX;
++ }
++ if (mii_reg & 0x0008)
++ *s |= PHY_STAT_FAULT;
++}
++
++static phy_info_t phy_info_dp83848= {
++ 0x020005c9,
++ "DP83848",
++
++ (const phy_cmd_t []) { /* config */
++ { mk_mii_read(MII_REG_CR), mii_parse_cr },
++ { mk_mii_read(MII_REG_ANAR), mii_parse_anar },
++ { mk_mii_read(MII_DP8384X_PHYSTST), mii_parse_dp8384x_sr2 },
++ { mk_mii_end, }
++ },
++ (const phy_cmd_t []) { /* startup - enable interrupts */
++ { mk_mii_write(MII_REG_CR, 0x1200), NULL }, /* autonegotiate */
++ { mk_mii_read(MII_REG_SR), mii_parse_sr },
++ { mk_mii_end, }
++ },
++ (const phy_cmd_t []) { /* ack_int - never happens, no interrupt */
++ { mk_mii_end, }
++ },
++ (const phy_cmd_t []) { /* shutdown */
++ { mk_mii_end, }
++ },
++};
++
++/* ------------------------------------------------------------------------- */
++
++static phy_info_t const * const phy_info[] = {
++ &phy_info_lxt970,
++ &phy_info_lxt971,
++ &phy_info_qs6612,
++ &phy_info_am79c874,
++ &phy_info_ks8721bl,
++ &phy_info_dp83848,
++ NULL
++};
++
++/* ------------------------------------------------------------------------- */
++#if !defined(CONFIG_M532x)
++#ifdef CONFIG_RPXCLASSIC
++static void
++mii_link_interrupt(void *dev_id);
++#else
++static irqreturn_t
++mii_link_interrupt(int irq, void * dev_id);
++#endif
++#endif
++
++#if defined(CONFIG_M5272)
++
++/*
++ * * do some initializtion based architecture of this chip
++ * */
++static void __inline__ fec_arch_init(void)
++{
++ return;
++}
++/*
++ * * do some cleanup based architecture of this chip
++ * */
++static void __inline__ fec_arch_exit(void)
++{
++ return;
++}
++
++/*
++ * Code specific to Coldfire 5272 setup.
++ */
++static void __inline__ fec_request_intrs(struct net_device *dev)
++{
++ volatile unsigned long *icrp;
++ static const struct idesc {
++ char *name;
++ unsigned short irq;
++ irq_handler_t handler;
++ } *idp, id[] = {
++ { "fec(RX)", 86, fec_enet_interrupt },
++ { "fec(TX)", 87, fec_enet_interrupt },
++ { "fec(OTHER)", 88, fec_enet_interrupt },
++ { "fec(MII)", 66, mii_link_interrupt },
++ { NULL },
++ };
++
++ /* Setup interrupt handlers. */
++ for (idp = id; idp->name; idp++) {
++ if (request_irq(idp->irq, idp->handler, 0, idp->name, dev) != 0)
++ printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, idp->irq);
++ }
++
++ /* Unmask interrupt at ColdFire 5272 SIM */
++ icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR3);
++ *icrp = 0x00000ddd;
++ icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
++ *icrp = (*icrp & 0x70777777) | 0x0d000000;
++}
++
++static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
++{
++ volatile fec_t *fecp;
++
++ fecp = fep->hwp;
++ fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
++ fecp->fec_x_cntrl = 0x00;
++
++ /*
++ * Set MII speed to 2.5 MHz
++ * See 5272 manual section 11.5.8: MSCR
++ */
++ fep->phy_speed = ((((MCF_CLK / 4) / (2500000 / 10)) + 5) / 10) * 2;
++ fecp->fec_mii_speed = fep->phy_speed;
++
++ fec_restart(dev, 0);
++}
++
++static void __inline__ fec_get_mac(struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile fec_t *fecp;
++ unsigned char *iap, tmpaddr[ETH_ALEN];
++
++ fecp = fep->hwp;
++
++ if (FEC_FLASHMAC) {
++ /*
++ * Get MAC address from FLASH.
++ * If it is all 1's or 0's, use the default.
++ */
++ iap = (unsigned char *)FEC_FLASHMAC;
++ if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
++ (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
++ iap = fec_mac_default;
++ if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
++ (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
++ iap = fec_mac_default;
++ } else {
++ *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
++ *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
++ iap = &tmpaddr[0];
++ }
++
++ memcpy(dev->dev_addr, iap, ETH_ALEN);
++
++ /* Adjust MAC if using default MAC address */
++ if (iap == fec_mac_default)
++ dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
++}
++
++static void __inline__ fec_enable_phy_intr(void)
++{
++}
++
++static void __inline__ fec_disable_phy_intr(void)
++{
++ volatile unsigned long *icrp;
++ icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
++ *icrp = (*icrp & 0x70777777) | 0x08000000;
++}
++
++static void __inline__ fec_phy_ack_intr(void)
++{
++ volatile unsigned long *icrp;
++ /* Acknowledge the interrupt */
++ icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
++ *icrp = (*icrp & 0x77777777) | 0x08000000;
++}
++
++static void __inline__ fec_localhw_setup(void)
++{
++}
++
++/*
++ * invalidate dcache related with the virtual memory range(start, end)
++ */
++static void __inline__ fec_dcache_inv_range(void * start, void * end)
++{
++ return ;
++}
++
++/*
++ * flush dcache related with the virtual memory range(start, end)
++ */
++static void __inline__ fec_dcache_flush_range(void * start, void * end)
++{
++ return ;
++}
++
++/*
++ * map memory space (addr, addr+size) to uncachable erea.
++ */
++static unsigned long __inline__ fec_map_uncache(unsigned long addr, int size)
++{
++ return addr;
++}
++
++/*
++ * unmap memory erea started with addr from uncachable erea.
++ */
++static void __inline__ fec_unmap_uncache(void * addr)
++{
++ return ;
++}
++
++/* ------------------------------------------------------------------------- */
++
++#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
++
++/*
++ * do some initializtion based architecture of this chip
++ */
++static void __inline__ fec_arch_init(void)
++{
++ return;
++}
++
++/*
++ * do some cleanup based architecture of this chip
++ */
++static void __inline__ fec_arch_exit(void)
++{
++ return;
++}
++
++/*
++ * Code specific to Coldfire 5230/5231/5232/5234/5235,
++ * the 5270/5271/5274/5275 and 5280/5282 setups.
++ */
++static void __inline__ fec_request_intrs(struct net_device *dev)
++{
++ struct fec_enet_private *fep;
++ int b;
++ static const struct idesc {
++ char *name;
++ unsigned short irq;
++ } *idp, id[] = {
++ { "fec(TXF)", 23 },
++ { "fec(TXB)", 24 },
++ { "fec(TXFIFO)", 25 },
++ { "fec(TXCR)", 26 },
++ { "fec(RXF)", 27 },
++ { "fec(RXB)", 28 },
++ { "fec(MII)", 29 },
++ { "fec(LC)", 30 },
++ { "fec(HBERR)", 31 },
++ { "fec(GRA)", 32 },
++ { "fec(EBERR)", 33 },
++ { "fec(BABT)", 34 },
++ { "fec(BABR)", 35 },
++ { NULL },
++ };
++
++ fep = netdev_priv(dev);
++ b = (fep->index) ? 128 : 64;
++
++ /* Setup interrupt handlers. */
++ for (idp = id; idp->name; idp++) {
++ if (request_irq(b+idp->irq, fec_enet_interrupt, 0, idp->name, dev) != 0)
++ printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
++ }
++
++ /* Unmask interrupts at ColdFire 5280/5282 interrupt controller */
++ {
++ volatile unsigned char *icrp;
++ volatile unsigned long *imrp;
++ int i, ilip;
++
++ b = (fep->index) ? MCFICM_INTC1 : MCFICM_INTC0;
++ icrp = (volatile unsigned char *) (MCF_IPSBAR + b +
++ MCFINTC_ICR0);
++ for (i = 23, ilip = 0x28; (i < 36); i++)
++ icrp[i] = ilip--;
++
++ imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
++ MCFINTC_IMRH);
++ *imrp &= ~0x0000000f;
++ imrp = (volatile unsigned long *) (MCF_IPSBAR + b +
++ MCFINTC_IMRL);
++ *imrp &= ~0xff800001;
++ }
++
++#if defined(CONFIG_M528x)
++ /* Set up gpio outputs for MII lines */
++ {
++ volatile u16 *gpio_paspar;
++ volatile u8 *gpio_pehlpar;
++
++ gpio_paspar = (volatile u16 *) (MCF_IPSBAR + 0x100056);
++ gpio_pehlpar = (volatile u16 *) (MCF_IPSBAR + 0x100058);
++ *gpio_paspar |= 0x0f00;
++ *gpio_pehlpar = 0xc0;
++ }
++#endif
++}
++
++static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
++{
++ volatile fec_t *fecp;
++
++ fecp = fep->hwp;
++ fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
++ fecp->fec_x_cntrl = 0x00;
++
++ /*
++ * Set MII speed to 2.5 MHz
++ * See 5282 manual section 17.5.4.7: MSCR
++ */
++ fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
++ fecp->fec_mii_speed = fep->phy_speed;
++
++ fec_restart(dev, 0);
++}
++
++static void __inline__ fec_get_mac(struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile fec_t *fecp;
++ unsigned char *iap, tmpaddr[ETH_ALEN];
++
++ fecp = fep->hwp;
++
++ if (FEC_FLASHMAC) {
++ /*
++ * Get MAC address from FLASH.
++ * If it is all 1's or 0's, use the default.
++ */
++ iap = FEC_FLASHMAC;
++ if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
++ (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
++ iap = fec_mac_default;
++ if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
++ (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
++ iap = fec_mac_default;
++ } else {
++ *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
++ *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
++ iap = &tmpaddr[0];
++ }
++
++ memcpy(dev->dev_addr, iap, ETH_ALEN);
++
++ /* Adjust MAC if using default MAC address */
++ if (iap == fec_mac_default)
++ dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
++}
++
++static void __inline__ fec_enable_phy_intr(void)
++{
++}
++
++static void __inline__ fec_disable_phy_intr(void)
++{
++}
++
++static void __inline__ fec_phy_ack_intr(void)
++{
++}
++
++static void __inline__ fec_localhw_setup(void)
++{
++}
++/*
++ * invalidate dcache related with the virtual memory range(start, end)
++ */
++static void __inline__ fec_dcache_inv_range(void * start, void * end)
++{
++ return ;
++}
++
++/*
++ * flush dcache related with the virtual memory range(start, end)
++ */
++static void __inline__ fec_dcache_flush_range(void * start, void * end)
++{
++ return ;
++}
++
++/*
++ * map memory space (addr, addr+size) to uncachable erea.
++ */
++static unsigned long __inline__ fec_map_uncache(unsigned long addr, int size)
++{
++ return addr;
++}
++
++/*
++ * unmap memory erea started with addr from uncachable erea.
++ */
++static void __inline__ fec_unmap_uncache(void * addr)
++{
++ return ;
++}
++
++/* ------------------------------------------------------------------------- */
++
++#elif defined(CONFIG_M520x)
++/*
++ * do some initializtion based architecture of this chip
++ */
++static void __inline__ fec_arch_init(void)
++{
++ return;
++}
++/*
++ * do some cleanup based architecture of this chip
++ */
++static void __inline__ fec_arch_exit(void)
++{
++ return;
++}
++
++/*
++ * Code specific to Coldfire 520x
++ */
++static void __inline__ fec_request_intrs(struct net_device *dev)
++{
++ struct fec_enet_private *fep;
++ int b;
++ static const struct idesc {
++ char *name;
++ unsigned short irq;
++ } *idp, id[] = {
++ { "fec(TXF)", 23 },
++ { "fec(TXB)", 24 },
++ { "fec(TXFIFO)", 25 },
++ { "fec(TXCR)", 26 },
++ { "fec(RXF)", 27 },
++ { "fec(RXB)", 28 },
++ { "fec(MII)", 29 },
++ { "fec(LC)", 30 },
++ { "fec(HBERR)", 31 },
++ { "fec(GRA)", 32 },
++ { "fec(EBERR)", 33 },
++ { "fec(BABT)", 34 },
++ { "fec(BABR)", 35 },
++ { NULL },
++ };
++
++ fep = netdev_priv(dev);
++ b = 64 + 13;
++
++ /* Setup interrupt handlers. */
++ for (idp = id; idp->name; idp++) {
++ if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
++ printk("FEC: Could not allocate %s IRQ(%d)!\n", idp->name, b+idp->irq);
++ }
++
++ /* Unmask interrupts at ColdFire interrupt controller */
++ {
++ volatile unsigned char *icrp;
++ volatile unsigned long *imrp;
++
++ icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
++ MCFINTC_ICR0);
++ for (b = 36; (b < 49); b++)
++ icrp[b] = 0x04;
++ imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 +
++ MCFINTC_IMRH);
++ *imrp &= ~0x0001FFF0;
++ }
++ *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FEC) |= 0xf0;
++ *(volatile unsigned char *)(MCF_IPSBAR + MCF_GPIO_PAR_FECI2C) |= 0x0f;
++}
++
++static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
++{
++ volatile fec_t *fecp;
++
++ fecp = fep->hwp;
++ fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
++ fecp->fec_x_cntrl = 0x00;
++
++ /*
++ * Set MII speed to 2.5 MHz
++ * See 5282 manual section 17.5.4.7: MSCR
++ */
++ fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
++ fecp->fec_mii_speed = fep->phy_speed;
++
++ fec_restart(dev, 0);
++}
++
++static void __inline__ fec_get_mac(struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile fec_t *fecp;
++ unsigned char *iap, tmpaddr[ETH_ALEN];
++
++ fecp = fep->hwp;
++
++ if (FEC_FLASHMAC) {
++ /*
++ * Get MAC address from FLASH.
++ * If it is all 1's or 0's, use the default.
++ */
++ iap = FEC_FLASHMAC;
++ if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
++ (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
++ iap = fec_mac_default;
++ if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
++ (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
++ iap = fec_mac_default;
++ } else {
++ *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
++ *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
++ iap = &tmpaddr[0];
++ }
++
++ memcpy(dev->dev_addr, iap, ETH_ALEN);
++
++ /* Adjust MAC if using default MAC address */
++ if (iap == fec_mac_default)
++ dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
++}
++
++static void __inline__ fec_enable_phy_intr(void)
++{
++}
++
++static void __inline__ fec_disable_phy_intr(void)
++{
++}
++
++static void __inline__ fec_phy_ack_intr(void)
++{
++}
++
++static void __inline__ fec_localhw_setup(void)
++{
++}
++
++/*
++ * invalidate dcache related with the virtual memory range(start, end)
++ */
++static void __inline__ fec_dcache_inv_range(void * start, void * end)
++{
++ return ;
++}
++
++/*
++ * flush dcache related with the virtual memory range(start, end)
++ */
++static void __inline__ fec_dcache_flush_range(void * start, void * end)
++{
++ return ;
++}
++
++/*
++ * map memory space (addr, addr+size) to uncachable erea.
++ */
++static unsigned long __inline__ fec_map_uncache(unsigned long addr, int size)
++{
++ return addr;
++}
++
++/*
++ * unmap memory erea started with addr from uncachable erea.
++ */
++static void __inline__ fec_unmap_uncache(void * addr)
++{
++ return ;
++}
++
++
++/* ------------------------------------------------------------------------- */
++
++#elif defined(CONFIG_M532x)
++
++/*
++ * do some initializtion based architecture of this chip
++ */
++static void __inline__ fec_arch_init(void)
++{
++ return;
++}
++
++/*
++ * do some cleanup based architecture of this chip
++ */
++static void __inline__ fec_arch_exit(void)
++{
++ return;
++}
++
++/*
++ * Code specific for M532x
++ */
++static void __inline__ fec_request_intrs(struct net_device *dev)
++{
++ struct fec_enet_private *fep;
++ int b;
++ static const struct idesc {
++ char *name;
++ unsigned short irq;
++ } *idp, id[] = {
++ { "fec(TXF)", 36 },
++ { "fec(TXB)", 37 },
++ { "fec(TXFIFO)", 38 },
++ { "fec(TXCR)", 39 },
++ { "fec(RXF)", 40 },
++ { "fec(RXB)", 41 },
++ { "fec(MII)", 42 },
++ { "fec(LC)", 43 },
++ { "fec(HBERR)", 44 },
++ { "fec(GRA)", 45 },
++ { "fec(EBERR)", 46 },
++ { "fec(BABT)", 47 },
++ { "fec(BABR)", 48 },
++ { NULL },
++ };
++
++ fep = netdev_priv(dev);
++ b = (fep->index) ? 128 : 64;
++
++ /* Setup interrupt handlers. */
++ for (idp = id; idp->name; idp++) {
++ if (request_irq(b+idp->irq,fec_enet_interrupt,0,idp->name,dev)!=0)
++ printk("FEC: Could not allocate %s IRQ(%d)!\n",
++ idp->name, b+idp->irq);
++ }
++
++ /* Unmask interrupts */
++ MCF_INTC0_ICR36 = 0x2;
++ MCF_INTC0_ICR37 = 0x2;
++ MCF_INTC0_ICR38 = 0x2;
++ MCF_INTC0_ICR39 = 0x2;
++ MCF_INTC0_ICR40 = 0x2;
++ MCF_INTC0_ICR41 = 0x2;
++ MCF_INTC0_ICR42 = 0x2;
++ MCF_INTC0_ICR43 = 0x2;
++ MCF_INTC0_ICR44 = 0x2;
++ MCF_INTC0_ICR45 = 0x2;
++ MCF_INTC0_ICR46 = 0x2;
++ MCF_INTC0_ICR47 = 0x2;
++ MCF_INTC0_ICR48 = 0x2;
++
++ MCF_INTC0_IMRH &= ~(
++ MCF_INTC_IMRH_INT_MASK36 |
++ MCF_INTC_IMRH_INT_MASK37 |
++ MCF_INTC_IMRH_INT_MASK38 |
++ MCF_INTC_IMRH_INT_MASK39 |
++ MCF_INTC_IMRH_INT_MASK40 |
++ MCF_INTC_IMRH_INT_MASK41 |
++ MCF_INTC_IMRH_INT_MASK42 |
++ MCF_INTC_IMRH_INT_MASK43 |
++ MCF_INTC_IMRH_INT_MASK44 |
++ MCF_INTC_IMRH_INT_MASK45 |
++ MCF_INTC_IMRH_INT_MASK46 |
++ MCF_INTC_IMRH_INT_MASK47 |
++ MCF_INTC_IMRH_INT_MASK48 );
++
++ /* Set up gpio outputs for MII lines */
++ MCF_GPIO_PAR_FECI2C |= (0 |
++ MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
++ MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
++ MCF_GPIO_PAR_FEC = (0 |
++ MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC |
++ MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC);
++}
++
++static void __inline__ fec_set_mii(struct net_device *dev, struct fec_enet_private *fep)
++{
++ volatile fec_t *fecp;
++
++ fecp = fep->hwp;
++ fecp->fec_r_cntrl = OPT_FRAME_SIZE | 0x04;
++ fecp->fec_x_cntrl = 0x00;
++
++ /*
++ * Set MII speed to 2.5 MHz
++ */
++ fep->phy_speed = ((((MCF_CLK / 2) / (2500000 / 10)) + 5) / 10) * 2;
++ fecp->fec_mii_speed = fep->phy_speed;
++
++ fec_restart(dev, 0);
++}
++
++static void __inline__ fec_get_mac(struct net_device *dev)
++{
++ struct fec_enet_private *fep = netdev_priv(dev);
++ volatile fec_t *fecp;
++ unsigned char *iap, tmpaddr[ETH_ALEN];
++
++ fecp = fep->hwp;
++
++ if (FEC_FLASHMAC) {
++ /*
++ * Get MAC address from FLASH.
++ * If it is all 1's or 0's, use the default.
++ */
++ iap = FEC_FLASHMAC;
++ if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
++ (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
++ iap = fec_mac_default;
++ if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
++ (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
++ iap = fec_mac_default;
++ } else {
++ *((unsigned long *) &tmpaddr[0]) = fecp->fec_addr_low;
++ *((unsigned short *) &tmpaddr[4]) = (fecp->fec_addr_high >> 16);
++ iap = &tmpaddr[0];
++ }
++
++ memcpy(dev->dev_addr, iap, ETH_ALEN);
++
++ /* Adjust MAC if using default MAC address */
++ if (iap == fec_mac_default)
++ dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
++}
++
++static void __inline__ fec_enable_phy_intr(void)
++{
++}
++
++static void __inline__ fec_disable_phy_intr(void)
++{
++}
++
++static void __inline__ fec_phy_ack_intr(void)
++{
++}
++
++static void __inline__ fec_localhw_setup(void)
++{
++}
++
++/*
++ * in...
[truncated message content] |
|
From: <ar...@us...> - 2008-04-02 08:32:22
|
Revision: 782
http://armadeus.svn.sourceforge.net/armadeus/?rev=782&view=rev
Author: artemys
Date: 2008-04-02 01:32:23 -0700 (Wed, 02 Apr 2008)
Log Message:
-----------
[BUILDROOT] Add custom uClibc config file for APF27
Modified Paths:
--------------
branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in
Added Paths:
-----------
branches/apf2/buildroot/target/device/armadeus/apf27/uClibc.config.arm
Modified: branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in 2008-04-02 08:29:50 UTC (rev 781)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/Makefile.in 2008-04-02 08:32:23 UTC (rev 782)
@@ -1,3 +1,5 @@
U-BOOT_TARGET_NAME=apx9328
LINUX_FORMAT=uImage
LINUX_KCONFIG=$(ARMADEUS_CONFIG_PATH)/linux-$(BR2_PACKAGE_LINUX_VERSION).config
+
+UCLIBC_CONFIG_FILE:=$(ARMADEUS_PATH)/$(ARMADEUS_TARGET_NAME)/uClibc.config.$(ARCH)
Added: branches/apf2/buildroot/target/device/armadeus/apf27/uClibc.config.arm
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/apf27/uClibc.config.arm (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/apf27/uClibc.config.arm 2008-04-02 08:32:23 UTC (rev 782)
@@ -0,0 +1,214 @@
+#
+# Automatically generated make config: don't edit
+# Tue Apr 1 13:52:05 2008
+#
+# TARGET_alpha is not set
+TARGET_arm=y
+# TARGET_avr32 is not set
+# TARGET_bfin is not set
+# TARGET_cris is not set
+# TARGET_e1 is not set
+# TARGET_frv is not set
+# TARGET_h8300 is not set
+# TARGET_hppa is not set
+# TARGET_i386 is not set
+# TARGET_i960 is not set
+# TARGET_ia64 is not set
+# TARGET_m68k is not set
+# TARGET_microblaze is not set
+# TARGET_mips is not set
+# TARGET_nios is not set
+# TARGET_nios2 is not set
+# TARGET_powerpc is not set
+# TARGET_sh is not set
+# TARGET_sh64 is not set
+# TARGET_sparc is not set
+# TARGET_v850 is not set
+# TARGET_vax is not set
+# TARGET_x86_64 is not set
+
+#
+# Target Architecture Features and Options
+#
+TARGET_ARCH="arm"
+FORCE_OPTIONS_FOR_ARCH=y
+CONFIG_ARM_OABI=y
+# CONFIG_ARM_EABI is not set
+# USE_BX is not set
+# CONFIG_GENERIC_ARM is not set
+# CONFIG_ARM610 is not set
+# CONFIG_ARM710 is not set
+# CONFIG_ARM7TDMI is not set
+# CONFIG_ARM720T is not set
+# CONFIG_ARM920T is not set
+# CONFIG_ARM922T is not set
+CONFIG_ARM926T=y
+# CONFIG_ARM10T is not set
+# CONFIG_ARM1136JF_S is not set
+# CONFIG_ARM1176JZ_S is not set
+# CONFIG_ARM1176JZF_S is not set
+# CONFIG_ARM_SA110 is not set
+# CONFIG_ARM_SA1100 is not set
+# CONFIG_ARM_XSCALE is not set
+# CONFIG_ARM_IWMMXT is not set
+TARGET_SUBARCH=""
+
+#
+# Using ELF file format
+#
+ARCH_ANY_ENDIAN=y
+ARCH_LITTLE_ENDIAN=y
+# ARCH_WANTS_BIG_ENDIAN is not set
+ARCH_WANTS_LITTLE_ENDIAN=y
+ARCH_HAS_MMU=y
+ARCH_USE_MMU=y
+UCLIBC_HAS_FLOATS=y
+# UCLIBC_HAS_FPU is not set
+UCLIBC_HAS_SOFT_FLOAT=y
+DO_C99_MATH=y
+KERNEL_HEADERS="/home/julien/workspace/Armadeus_SF/armadeus_apf2/buildroot/toolchain_build_arm/linux/include"
+HAVE_DOT_CONFIG=y
+
+#
+# General Library Settings
+#
+# HAVE_NO_PIC is not set
+DOPIC=y
+# HAVE_NO_SHARED is not set
+# ARCH_HAS_NO_LDSO is not set
+HAVE_SHARED=y
+# FORCE_SHAREABLE_TEXT_SEGMENTS is not set
+LDSO_LDD_SUPPORT=y
+LDSO_CACHE_SUPPORT=y
+# LDSO_PRELOAD_FILE_SUPPORT is not set
+LDSO_BASE_FILENAME="ld.so"
+# UCLIBC_STATIC_LDCONFIG is not set
+# LDSO_RUNPATH is not set
+UCLIBC_CTOR_DTOR=y
+# HAS_NO_THREADS is not set
+UCLIBC_HAS_THREADS=y
+# PTHREADS_DEBUG_SUPPORT is not set
+LINUXTHREADS_OLD=y
+UCLIBC_HAS_LFS=y
+# MALLOC is not set
+# MALLOC_SIMPLE is not set
+MALLOC_STANDARD=y
+MALLOC_GLIBC_COMPAT=y
+UCLIBC_DYNAMIC_ATEXIT=y
+# COMPAT_ATEXIT is not set
+# UCLIBC_SUSV3_LEGACY is not set
+# UCLIBC_SUSV3_LEGACY_MACROS is not set
+UCLIBC_HAS_SHADOW=y
+# UCLIBC_HAS_PROGRAM_INVOCATION_NAME is not set
+UCLIBC_HAS___PROGNAME=y
+# UNIX98PTY_ONLY is not set
+ASSUME_DEVPTS=y
+UCLIBC_HAS_TM_EXTENSIONS=y
+UCLIBC_HAS_TZ_CACHING=y
+UCLIBC_HAS_TZ_FILE=y
+UCLIBC_HAS_TZ_FILE_READ_MANY=y
+UCLIBC_TZ_FILE_PATH="/etc/TZ"
+
+#
+# Advanced Library Settings
+#
+UCLIBC_PWD_BUFFER_SIZE=256
+UCLIBC_GRP_BUFFER_SIZE=256
+
+#
+# Networking Support
+#
+UCLIBC_HAS_IPV6=y
+UCLIBC_HAS_RPC=y
+UCLIBC_HAS_FULL_RPC=y
+UCLIBC_HAS_REENTRANT_RPC=y
+# UCLIBC_USE_NETLINK is not set
+# UCLIBC_HAS_BSD_RES_CLOSE is not set
+
+#
+# String and Stdio Support
+#
+UCLIBC_HAS_STRING_GENERIC_OPT=y
+UCLIBC_HAS_STRING_ARCH_OPT=y
+UCLIBC_HAS_CTYPE_TABLES=y
+UCLIBC_HAS_CTYPE_SIGNED=y
+# UCLIBC_HAS_CTYPE_UNSAFE is not set
+UCLIBC_HAS_CTYPE_CHECKED=y
+# UCLIBC_HAS_CTYPE_ENFORCED is not set
+UCLIBC_HAS_WCHAR=y
+# UCLIBC_HAS_LOCALE is not set
+UCLIBC_HAS_HEXADECIMAL_FLOATS=y
+UCLIBC_HAS_GLIBC_CUSTOM_PRINTF=y
+UCLIBC_PRINTF_SCANF_POSITIONAL_ARGS=9
+UCLIBC_HAS_SCANF_GLIBC_A_FLAG=y
+# UCLIBC_HAS_STDIO_BUFSIZ_NONE is not set
+# UCLIBC_HAS_STDIO_BUFSIZ_256 is not set
+# UCLIBC_HAS_STDIO_BUFSIZ_512 is not set
+# UCLIBC_HAS_STDIO_BUFSIZ_1024 is not set
+# UCLIBC_HAS_STDIO_BUFSIZ_2048 is not set
+UCLIBC_HAS_STDIO_BUFSIZ_4096=y
+# UCLIBC_HAS_STDIO_BUFSIZ_8192 is not set
+UCLIBC_HAS_STDIO_BUILTIN_BUFFER_NONE=y
+# UCLIBC_HAS_STDIO_BUILTIN_BUFFER_4 is not set
+# UCLIBC_HAS_STDIO_BUILTIN_BUFFER_8 is not set
+# UCLIBC_HAS_STDIO_SHUTDOWN_ON_ABORT is not set
+UCLIBC_HAS_STDIO_GETC_MACRO=y
+UCLIBC_HAS_STDIO_PUTC_MACRO=y
+UCLIBC_HAS_STDIO_AUTO_RW_TRANSITION=y
+# UCLIBC_HAS_FOPEN_LARGEFILE_MODE is not set
+UCLIBC_HAS_FOPEN_EXCLUSIVE_MODE=y
+UCLIBC_HAS_GLIBC_CUSTOM_STREAMS=y
+UCLIBC_HAS_PRINTF_M_SPEC=y
+UCLIBC_HAS_ERRNO_MESSAGES=y
+# UCLIBC_HAS_SYS_ERRLIST is not set
+UCLIBC_HAS_SIGNUM_MESSAGES=y
+# UCLIBC_HAS_SYS_SIGLIST is not set
+UCLIBC_HAS_GNU_GETOPT=y
+UCLIBC_HAS_GNU_GETSUBOPT=y
+
+#
+# Big and Tall
+#
+UCLIBC_HAS_REGEX=y
+UCLIBC_HAS_REGEX_OLD=y
+UCLIBC_HAS_FNMATCH=y
+UCLIBC_HAS_FNMATCH_OLD=y
+# UCLIBC_HAS_WORDEXP is not set
+UCLIBC_HAS_FTW=y
+UCLIBC_HAS_GLOB=y
+UCLIBC_HAS_GNU_GLOB=y
+
+#
+# Library Installation Options
+#
+SHARED_LIB_LOADER_PREFIX="/lib"
+RUNTIME_PREFIX="/"
+DEVEL_PREFIX="/usr/"
+
+#
+# Security options
+#
+# UCLIBC_BUILD_PIE is not set
+# UCLIBC_HAS_ARC4RANDOM is not set
+# HAVE_NO_SSP is not set
+# UCLIBC_HAS_SSP is not set
+UCLIBC_BUILD_RELRO=y
+UCLIBC_BUILD_NOW=y
+# UCLIBC_BUILD_NOEXECSTACK is not set
+
+#
+# uClibc development/debugging options
+#
+CROSS_COMPILER_PREFIX="/home/julien/workspace/Armadeus_SF/armadeus_apf2/buildroot/build_arm/staging_dir/usr/bin/arm-linux-uclibc-"
+UCLIBC_EXTRA_CFLAGS=""
+# DODEBUG is not set
+# DODEBUG_PT is not set
+DOSTRIP=y
+# DOASSERTS is not set
+# SUPPORT_LD_DEBUG is not set
+# SUPPORT_LD_DEBUG_EARLY is not set
+# UCLIBC_MALLOC_DEBUGGING is not set
+WARNINGS="-Wall"
+# EXTRA_WARNINGS is not set
+# DOMULTI is not set
+# UCLIBC_MJN3_ONLY is not set
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