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[Armadeus-commitlog] SF.net SVN: armadeus:[831] trunk/buildroot/package/sdl

From: <ar...@us...> - 2008-07-17 08:11:07

Revision: 831
          http://armadeus.svn.sourceforge.net/armadeus/?rev=831&view=rev
Author:   artemys
Date:     2008-07-17 08:11:14 +0000 (Thu, 17 Jul 2008)

Log Message:
-----------
[BUILDROOT] Fixes bug 2019483 (SDL_ttf doesn't compile)

Modified Paths:
--------------
    trunk/buildroot/package/sdl/sdl_ttf.mk

Added Paths:
-----------
    trunk/buildroot/package/sdl/sdl_ttf-2.0.8-freetype-includes.patch

Added: trunk/buildroot/package/sdl/sdl_ttf-2.0.8-freetype-includes.patch
===================================================================
--- trunk/buildroot/package/sdl/sdl_ttf-2.0.8-freetype-includes.patch	                        (rev 0)
+++ trunk/buildroot/package/sdl/sdl_ttf-2.0.8-freetype-includes.patch	2008-07-17 08:11:14 UTC (rev 831)
@@ -0,0 +1,29 @@
+diff -urN -X dontdiff SDL_ttf-2.0.8/SDL_ttf.c SDL_ttf-2.0.8.mod/SDL_ttf.c
+--- SDL_ttf-2.0.8/SDL_ttf.c	2006-05-01 11:26:17.000000000 +0200
++++ SDL_ttf-2.0.8.mod/SDL_ttf.c	2008-07-12 19:56:49.000000000 +0200
+@@ -43,16 +43,6 @@
+ #include FT_FREETYPE_H
+ #include FT_OUTLINE_H
+ #include FT_TRUETYPE_IDS_H
+-/*
+-#include <freetype/freetype.h>
+-#include <freetype/ftoutln.h>
+-#include <freetype/ttnameid.h>
+-*/
+-#include <freetype/internal/ftobjs.h>
+-
+-#ifndef FT_OPEN_STREAM
+-#define FT_OPEN_STREAM ft_open_stream
+-#endif
+ 
+ #include "SDL.h"
+ #include "SDL_endian.h"
+@@ -278,7 +268,7 @@
+ 	}
+ 	memset(stream, 0, sizeof(*stream));
+ 
+-	stream->memory = library->memory;
++	stream->memory = NULL;  /* set by FT_Open_Face */
+ 	stream->read = RWread;
+ 	stream->descriptor.pointer = src;
+ 	stream->pos = (unsigned long)position;

Modified: trunk/buildroot/package/sdl/sdl_ttf.mk
===================================================================
--- trunk/buildroot/package/sdl/sdl_ttf.mk	2008-07-16 10:11:56 UTC (rev 830)
+++ trunk/buildroot/package/sdl/sdl_ttf.mk	2008-07-17 08:11:14 UTC (rev 831)
@@ -17,6 +17,7 @@
 
 $(SDL-TTF_DIR)/.unpacked: $(DL_DIR)/$(SDL-TTF_SOURCE)
 	$(SDL-TTF_CAT) $(DL_DIR)/$(SDL-TTF_SOURCE) | tar -C $(BUILD_DIR) $(TAR_OPTIONS) -
+	toolchain/patch-kernel.sh $(SDL-TTF_DIR) package/sdl sdl_ttf-$(SDL-TTF_VERSION)\*.patch
 	touch $@
 
 $(SDL-TTF_DIR)/.configured: $(SDL-TTF_DIR)/.unpacked
@@ -48,7 +49,7 @@
 
 $(TARGET_DIR)/usr/lib/libSDL_ttf.so: $(STAGING_DIR)/usr/lib/libSDL_ttf.so
 	cp -dpf $(STAGING_DIR)/usr/lib/libSDL_ttf*.so* $(TARGET_DIR)/usr/lib/
-	-$(STRIP) --strip-unneeded $(TARGET_DIR)/usr/lib/libSDL_ttf.so
+	-$(STRIPCMD) --strip-unneeded $(TARGET_DIR)/usr/lib/libSDL_ttf.so
 
 SDL_TTF sdl_ttf: uclibc sdl freetype $(TARGET_DIR)/usr/lib/libSDL_ttf.so
 


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[Armadeus-commitlog] SF.net SVN: armadeus: [830] trunk/patches

From: <ar...@us...> - 2008-07-16 10:11:49

Revision: 830
          http://armadeus.svn.sourceforge.net/armadeus/?rev=830&view=rev
Author:   artemys
Date:     2008-07-16 03:11:56 -0700 (Wed, 16 Jul 2008)

Log Message:
-----------
[BUILDROOT] Activate Socket CAN in menuconfig

Modified Paths:
--------------
    trunk/patches/004-Buildroot-defconfig.diff

Added Paths:
-----------
    trunk/patches/042-buildroot-socketcan.diff

Modified: trunk/patches/004-Buildroot-defconfig.diff
===================================================================
--- trunk/patches/004-Buildroot-defconfig.diff	2008-07-16 09:31:19 UTC (rev 829)
+++ trunk/patches/004-Buildroot-defconfig.diff	2008-07-16 10:11:56 UTC (rev 830)
@@ -175,7 +175,7 @@
  BR2_UCLIBC_CONFIG="toolchain/uClibc/uClibc-0.9.29.config"
  # BR2_ENABLE_LOCALE is not set
  # BR2_PTHREADS_NONE is not set
-@@ -42,35 +175,452 @@
+@@ -42,35 +175,453 @@
  BR2_PTHREADS_OLD=y
  # BR2_PTHREADS_NATIVE is not set
  # BR2_PTHREAD_DEBUG is not set
@@ -405,6 +405,7 @@
 +# BR2_PACKAGE_RSYNC is not set
 +# BR2_PACKAGE_SAMBA is not set
 +# BR2_PACKAGE_SOCAT is not set
++# BR2_PACKAGE_SOCKETCAN is not set
 +# BR2_PACKAGE_STUNNEL is not set
 +# BR2_PACKAGE_TCPDUMP is not set
 +# BR2_PACKAGE_DHCPDUMP is not set

Added: trunk/patches/042-buildroot-socketcan.diff
===================================================================
--- trunk/patches/042-buildroot-socketcan.diff	                        (rev 0)
+++ trunk/patches/042-buildroot-socketcan.diff	2008-07-16 10:11:56 UTC (rev 830)
@@ -0,0 +1,10 @@
+--- buildroot/package/Config.in.org	2008-07-16 11:53:26.000000000 +0200
++++ buildroot/package/Config.in	2008-07-16 11:53:59.000000000 +0200
+@@ -188,6 +188,7 @@
+ source "package/rsync/Config.in"
+ source "package/samba/Config.in"
+ source "package/socat/Config.in"
++source "package/socketcan/Config.in"
+ source "package/stunnel/Config.in"
+ source "package/tcpdump/Config.in"
+ source "package/tftpd/Config.in"


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[Armadeus-commitlog] SF.net SVN: armadeus: [829] trunk/buildroot/package

From: <ar...@us...> - 2008-07-16 09:31:10

Revision: 829
          http://armadeus.svn.sourceforge.net/armadeus/?rev=829&view=rev
Author:   artemys
Date:     2008-07-16 02:31:19 -0700 (Wed, 16 Jul 2008)

Log Message:
-----------
[BUILDROOT] Add Socket CAN package (not activated by menuconfig yet)

Added Paths:
-----------
    trunk/buildroot/package/socketcan/
    trunk/buildroot/package/socketcan/Config.in
    trunk/buildroot/package/socketcan/socketcan-svn-rev810-cross-compile.patch
    trunk/buildroot/package/socketcan/socketcan.mk

Added: trunk/buildroot/package/socketcan/Config.in
===================================================================
--- trunk/buildroot/package/socketcan/Config.in	                        (rev 0)
+++ trunk/buildroot/package/socketcan/Config.in	2008-07-16 09:31:19 UTC (rev 829)
@@ -0,0 +1,16 @@
+config BR2_PACKAGE_SOCKETCAN
+	bool "Socket CAN"
+	default n
+	help
+	  The socketcan package is an implementation of CAN protocols
+	  (Controller Area Network) for Linux.  CAN is a networking technology
+	  which has wide-spread use in automation, embedded devices, and
+	  automotive fields.
+
+	  While there have been other CAN implementations for Linux based on 
+	  character devices, Socket CAN uses the Berkeley socket API, 
+	  the Linux network stack and implements the CAN device drivers as 
+	  network interfaces.  The CAN socket API has been designed as similar
+	  as possible to the TCP/IP protocols to allow programmers, familiar 
+	  with network programming, to easily learn how to use CAN sockets.
+

Added: trunk/buildroot/package/socketcan/socketcan-svn-rev810-cross-compile.patch
===================================================================
--- trunk/buildroot/package/socketcan/socketcan-svn-rev810-cross-compile.patch	                        (rev 0)
+++ trunk/buildroot/package/socketcan/socketcan-svn-rev810-cross-compile.patch	2008-07-16 09:31:19 UTC (rev 829)
@@ -0,0 +1,33 @@
+diff -urN socketcan-svn-rev810.org/can-utils/Makefile socketcan-svn-rev810/can-utils/Makefile
+--- socketcan-svn-rev810.org/can-utils/Makefile	2008-07-16 10:52:02.000000000 +0200
++++ socketcan-svn-rev810/can-utils/Makefile	2008-07-16 11:19:21.000000000 +0200
+@@ -40,6 +40,10 @@
+ #
+ #  Send feedback to <soc...@li...>
+ 
++ifeq ($(INSTALL_DIR),)
++	INSTALL_DIR=/usr/local/bin
++endif
++
+ MAKEFLAGS = -k
+ 
+ CFLAGS    = -O2 -Wall -Wno-parentheses -I../kernel/2.6/include \
+@@ -52,11 +56,17 @@
+ 
+ all: $(PROGRAMS)
+ 
++strip: all
++	$(STRIP_CMD) $(PROGRAMS)
++
+ clean:
+ 	rm -f $(PROGRAMS) *.o
+ 
+ install:
+-	cp -f $(PROGRAMS) /usr/local/bin
++	cp -f $(PROGRAMS) $(INSTALL_DIR)
++
++uninstall:
++	cd $(INSTALL_DIR); rm -f $(PROGRAMS)
+ 
+ distclean:
+ 	rm -f $(PROGRAMS) *.o *~

Added: trunk/buildroot/package/socketcan/socketcan.mk
===================================================================
--- trunk/buildroot/package/socketcan/socketcan.mk	                        (rev 0)
+++ trunk/buildroot/package/socketcan/socketcan.mk	2008-07-16 09:31:19 UTC (rev 829)
@@ -0,0 +1,60 @@
+#############################################################
+#
+# Socket CAN
+#
+#############################################################
+SOCKETCAN_TRUNK:=http://svn.berlios.de/svnroot/repos/socketcan/trunk
+SOCKETCAN_REVISION:=810
+SOCKETCAN_NAME:=socketcan-svn-rev$(SOCKETCAN_REVISION)
+SOCKETCAN_DIR:=$(BUILD_DIR)/$(SOCKETCAN_NAME)
+SOCKETCAN_SOURCE:=$(SOCKETCAN_NAME).tar.bz2
+SOCKETCAN_CAT=$(BZCAT)
+SOCKETCAN_EXE=candump
+
+$(DL_DIR)/$(SOCKETCAN_SOURCE):
+	(cd $(BUILD_DIR); \
+		$(SVN_CO) -r $(SOCKETCAN_REVISION) $(SOCKETCAN_TRUNK) $(SOCKETCAN_NAME); \
+		tar -cvf $(SOCKETCAN_NAME).tar $(SOCKETCAN_NAME); \
+		bzip2 $(SOCKETCAN_NAME).tar; \
+		rm -rf $(SOCKETCAN_DIR); \
+		mv $(SOCKETCAN_SOURCE) $(DL_DIR)/$(SOCKETCAN_SOURCE); \
+	)
+
+$(SOCKETCAN_DIR)/.unpacked: $(DL_DIR)/$(SOCKETCAN_SOURCE)
+	$(SOCKETCAN_CAT) $(DL_DIR)/$(SOCKETCAN_SOURCE) | tar -C $(BUILD_DIR) $(TAR_OPTIONS) -
+	toolchain/patch-kernel.sh $(SOCKETCAN_DIR) package/socketcan $(SOCKETCAN_NAME)\*.patch	
+	touch $@
+
+$(SOCKETCAN_DIR)/.configured: $(SOCKETCAN_DIR)/.unpacked
+	touch $@
+
+$(SOCKETCAN_DIR)/.compiled: $(SOCKETCAN_DIR)/.configured
+	$(MAKE) CC=$(TARGET_CC) -C $(SOCKETCAN_DIR)/can-utils
+	touch $@
+
+$(TARGET_DIR)/usr/bin/$(SOCKETCAN_EXE): $(SOCKETCAN_DIR)/.compiled
+	$(MAKE) STRIP_CMD="$(STRIPCMD) $(STRIP_STRIP_UNNEEDED)" -C $(SOCKETCAN_DIR)/can-utils strip
+	$(MAKE) INSTALL_DIR=$(TARGET_DIR)/usr/bin -C $(SOCKETCAN_DIR)/can-utils install
+	touch $@
+
+SOCKETCAN socketcan: uclibc $(TARGET_DIR)/usr/bin/$(SOCKETCAN_EXE)
+
+socketcan-source: $(DL_DIR)/$(SOCKETCAN_SOURCE)
+
+socketcan-clean:
+	$(MAKE) INSTALL_DIR=$(STAGING_DIR)/usr/bin -C $(SOCKETCAN_DIR) uninstall
+	-$(MAKE) -C $(SOCKETCAN_DIR) clean
+
+socketcan-dirclean:
+	rm -rf $(SOCKETCAN_DIR)
+
+
+############################################################
+#
+# Toplevel Makefile options
+#
+############################################################
+ifeq ($(strip $(BR2_PACKAGE_SOCKETCAN)),y)
+TARGETS+=socketcan
+endif
+


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[Armadeus-commitlog] SF.net SVN: armadeus: [828] trunk/target/linux/debug/imxregs/imxregs.h

From: <ar...@us...> - 2008-07-15 08:03:12

Revision: 828
          http://armadeus.svn.sourceforge.net/armadeus/?rev=828&view=rev
Author:   artemys
Date:     2008-07-15 01:02:59 -0700 (Tue, 15 Jul 2008)

Log Message:
-----------
[TOOLS] Add watchdog & GPTimer registers access in imxregs

Modified Paths:
--------------
    trunk/target/linux/debug/imxregs/imxregs.h

Modified: trunk/target/linux/debug/imxregs/imxregs.h
===================================================================
--- trunk/target/linux/debug/imxregs/imxregs.h	2008-07-09 15:04:45 UTC (rev 827)
+++ trunk/target/linux/debug/imxregs/imxregs.h	2008-07-15 08:02:59 UTC (rev 828)
@@ -22,6 +22,23 @@
 
 static struct reg_info regs[] = 
 {
+// Watchdog
+{ "WCR",	0x00201000,  0, 0xffffffff, 'x', "Watchdog Control Register" },
+{ "WSR",	0x00201004,  0, 0xffffffff, 'x', "Watchdog Service Register" },
+{ "WSTR",	0x00201008,  0, 0xffffffff, 'x', "Watchdog Status Register" },
+// Timers
+{ "TCTL1",	0x00202000, 0, 0xffffffff, 'x', "Timer 1 Control Register" },
+{ "TPRER1",	0x00202004, 0, 0xffffffff, 'x', "Timer 1 Prescaler Register" },
+{ "TCMP1",	0x00202008, 0, 0xffffffff, 'x', "Timer 1 Compare Register" },
+{ "TCR1",	0x0020200C, 0, 0xffffffff, 'x', "Timer 1 Capture Register" },
+{ "TCN1",	0x00202010, 0, 0xffffffff, 'x', "Timer 1 Counter Register" },
+{ "TSTAT1",	0x00202014, 0, 0xffffffff, 'x', "Timer 1 Status Register" },
+{ "TCTL2",	0x00203000, 0, 0xffffffff, 'x', "Timer 2 Control Register" },
+{ "TPRER2",	0x00203004, 0, 0xffffffff, 'x', "Timer 2 Prescaler Register" },
+{ "TCMP2",	0x00203008, 0, 0xffffffff, 'x', "Timer 2 Compare Register" },
+{ "TCR2",	0x0020300C, 0, 0xffffffff, 'x', "Timer 2 Capture Register" },
+{ "TCN2",	0x00203010, 0, 0xffffffff, 'x', "Timer 2 Counter Register" },
+{ "TSTAT2",	0x00203014, 0, 0xffffffff, 'x', "Timer 2 Status Register" },
 // RTC
 { "HOURMIN",   0x00204000,  0, 0xffffffff, 'x', "RTC Hours and minutes counter register" },
 { "SECONDS",   0x00204004,  0, 0xffffffff, 'x', "RTC Seconds counter register" },


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[Armadeus-commitlog] SF.net SVN: armadeus: [827] trunk/target/linux/debug/imxregs/imxregs.c

From: <ar...@us...> - 2008-07-09 15:04:40

Revision: 827
          http://armadeus.svn.sourceforge.net/armadeus/?rev=827&view=rev
Author:   artemys
Date:     2008-07-09 08:04:45 -0700 (Wed, 09 Jul 2008)

Log Message:
-----------
[TOOLS] imxregs: say when register is not found

Modified Paths:
--------------
    trunk/target/linux/debug/imxregs/imxregs.c

Modified: trunk/target/linux/debug/imxregs/imxregs.c
===================================================================
--- trunk/target/linux/debug/imxregs/imxregs.c	2008-07-05 15:43:06 UTC (rev 826)
+++ trunk/target/linux/debug/imxregs/imxregs.c	2008-07-09 15:04:45 UTC (rev 827)
@@ -163,14 +163,18 @@
 // Show content of register with name starting with given string
 static void dumpmatching(char *name)
 {
-   int i;
+   int i, found=0;
    int n=sizeof(regs)/sizeof(struct reg_info);
 
    for (i=0; i<n; i++) 
    {
-      if (strstr(regs[i].name, name))
+      if (strstr(regs[i].name, name)) {
          dumpentry(i);
+         found = 1;
+      }
    }
+   if(!found)
+      printf("No matching register found\n");
 }
 
 //


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[Armadeus-commitlog] SF.net SVN: armadeus: [826] branches/apf2/buildroot/target/device/armadeus/ u-boot/patches/1.3.2/320-u-boot-1.3.2.imx27nand.patch

From: <th...@us...> - 2008-07-05 15:43:07

Revision: 826
          http://armadeus.svn.sourceforge.net/armadeus/?rev=826&view=rev
Author:   thom25
Date:     2008-07-05 08:43:06 -0700 (Sat, 05 Jul 2008)

Log Message:
-----------
remove bugy patch

Removed Paths:
-------------
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/320-u-boot-1.3.2.imx27nand.patch

Deleted: branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/320-u-boot-1.3.2.imx27nand.patch
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/320-u-boot-1.3.2.imx27nand.patch	2008-07-04 18:11:58 UTC (rev 825)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/320-u-boot-1.3.2.imx27nand.patch	2008-07-05 15:43:06 UTC (rev 826)
@@ -1,1656 +0,0 @@
---- u-boot-1.3.2/board/pcm038/lowlevel_init.S	2008-06-25 04:12:34.000000000 +0200
-+++ u-boot-new/board/pcm038/lowlevel_init.S	2008-06-14 22:15:02.000000000 +0200
-@@ -10,45 +10,138 @@
- 
- 
- 
--#define writel(val, reg) \
-+#define writel(reg, val) \
- 	ldr		r0,	=reg;	\
- 	ldr		r1,	=val;	\
- 	str		r1,   [r0];
- 
- #define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn)  (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
- 
-+.macro port_init_sha
-+/* PORTA */
-+    writel( DR(PORTA), CFG_DR_A_VAL)
-+    writel( OCR1(PORTA), CFG_OCR1_A_VAL)
-+    writel( OCR2(PORTA), CFG_OCR2_A_VAL)
-+    writel( ICONFA1(PORTA), CFG_ICFA1_A_VAL)
-+    writel( ICONFA2(PORTA), CFG_ICFA2_A_VAL)
-+    writel( ICONFB1(PORTA), CFG_ICFB1_A_VAL)
-+    writel( ICONFB2(PORTA), CFG_ICFB2_A_VAL)
-+    writel( ICR1(PORTA), CFG_ICR1_A_VAL)
-+    writel( ICR2(PORTA), CFG_ICR2_A_VAL)
-+    writel( IMR(PORTA), CFG_IMR_A_VAL)
-+    writel( DDIR(PORTA), CFG_DDIR_A_VAL)
-+    writel( GPR(PORTA), CFG_GPR_A_VAL)
-+    writel( PUEN(PORTA), CFG_PUEN_A_VAL)
-+    writel( GIUS(PORTA), CFG_GIUS_A_VAL)
-+/* PORTB */
-+    writel( DR(PORTB), CFG_DR_B_VAL)
-+    writel( OCR1(PORTB), CFG_OCR1_B_VAL)
-+    writel( OCR2(PORTB), CFG_OCR2_B_VAL)
-+    writel( ICONFA1(PORTB), CFG_ICFA1_B_VAL)
-+    writel( ICONFA2(PORTB), CFG_ICFA2_B_VAL)
-+    writel( ICONFB1(PORTB), CFG_ICFB1_B_VAL)
-+    writel( ICONFB2(PORTB), CFG_ICFB2_B_VAL)
-+    writel( ICR1(PORTB), CFG_ICR1_B_VAL)
-+    writel( ICR2(PORTB), CFG_ICR2_B_VAL)
-+    writel( IMR(PORTB), CFG_IMR_B_VAL)
-+    writel( DDIR(PORTB), CFG_DDIR_B_VAL)
-+    writel( GPR(PORTB), CFG_GPR_B_VAL)
-+    writel( PUEN(PORTB), CFG_PUEN_B_VAL)
-+    writel( GIUS(PORTB), CFG_GIUS_B_VAL)
-+/* PORTC */
-+    writel( DR(PORTC), CFG_DR_C_VAL)
-+    writel( OCR1(PORTC), CFG_OCR1_C_VAL)
-+    writel( OCR2(PORTC), CFG_OCR2_C_VAL)
-+    writel( ICONFA1(PORTC), CFG_ICFA1_C_VAL)
-+    writel( ICONFA2(PORTC), CFG_ICFA2_C_VAL)
-+    writel( ICONFB1(PORTC), CFG_ICFB1_C_VAL)
-+    writel( ICONFB2(PORTC), CFG_ICFB2_C_VAL)
-+    writel( ICR1(PORTC), CFG_ICR1_C_VAL)
-+    writel( ICR2(PORTC), CFG_ICR2_C_VAL)
-+    writel( IMR(PORTC), CFG_IMR_C_VAL)
-+    writel( DDIR(PORTC), CFG_DDIR_C_VAL)
-+    writel( GPR(PORTC), CFG_GPR_C_VAL)
-+    writel( PUEN(PORTC), CFG_PUEN_C_VAL)
-+    writel( GIUS(PORTC), CFG_GIUS_C_VAL)
-+/* PORTD */
-+    writel( DR(PORTD), CFG_DR_D_VAL)
-+    writel( OCR1(PORTD), CFG_OCR1_D_VAL)
-+    writel( OCR2(PORTD), CFG_OCR2_D_VAL)
-+    writel( ICONFA1(PORTD), CFG_ICFA1_D_VAL)
-+    writel( ICONFA2(PORTD), CFG_ICFA2_D_VAL)
-+    writel( ICONFB1(PORTD), CFG_ICFB1_D_VAL)
-+    writel( ICONFB2(PORTD), CFG_ICFB2_D_VAL)
-+    writel( ICR1(PORTD), CFG_ICR1_D_VAL)
-+    writel( ICR2(PORTD), CFG_ICR2_D_VAL)
-+    writel( IMR(PORTD), CFG_IMR_D_VAL)
-+    writel( DDIR(PORTD), CFG_DDIR_D_VAL)
-+    writel( GPR(PORTD), CFG_GPR_D_VAL)
-+    writel( PUEN(PORTD), CFG_PUEN_D_VAL)
-+    writel( GIUS(PORTD), CFG_GIUS_D_VAL)
-+/* PORTE */
-+    writel( DR(PORTE), CFG_DR_E_VAL)
-+    writel( OCR1(PORTE), CFG_OCR1_E_VAL)
-+    writel( OCR2(PORTE), CFG_OCR2_E_VAL)
-+    writel( ICONFA1(PORTE), CFG_ICFA1_E_VAL)
-+    writel( ICONFA2(PORTE), CFG_ICFA2_E_VAL)
-+    writel( ICONFB1(PORTE), CFG_ICFB1_E_VAL)
-+    writel( ICONFB2(PORTE), CFG_ICFB2_E_VAL)
-+    writel( ICR1(PORTE), CFG_ICR1_E_VAL)
-+    writel( ICR2(PORTE), CFG_ICR2_E_VAL)
-+    writel( IMR(PORTE), CFG_IMR_E_VAL)
-+    writel( DDIR(PORTE), CFG_DDIR_E_VAL)
-+    writel( GPR(PORTE), CFG_GPR_E_VAL)
-+    writel( PUEN(PORTE), CFG_PUEN_E_VAL)
-+    writel( GIUS(PORTE), CFG_GIUS_E_VAL)
-+/* PORTF */
-+    writel( DR(PORTF), CFG_DR_F_VAL)
-+    writel( OCR1(PORTF), CFG_OCR1_F_VAL)
-+    writel( OCR2(PORTF), CFG_OCR2_F_VAL)
-+    writel( ICONFA1(PORTF), CFG_ICFA1_F_VAL)
-+    writel( ICONFA2(PORTF), CFG_ICFA2_F_VAL)
-+    writel( ICONFB1(PORTF), CFG_ICFB1_F_VAL)
-+    writel( ICONFB2(PORTF), CFG_ICFB2_F_VAL)
-+    writel( ICR1(PORTF), CFG_ICR1_F_VAL)
-+    writel( ICR2(PORTF), CFG_ICR2_F_VAL)
-+    writel( IMR(PORTF), CFG_IMR_F_VAL)
-+    writel( DDIR(PORTF), CFG_DDIR_F_VAL)
-+    writel( GPR(PORTF), CFG_GPR_F_VAL)
-+    writel( PUEN(PORTF), CFG_PUEN_F_VAL)
-+    writel( GIUS(PORTF), CFG_GIUS_F_VAL)
-+.endm
-+
- .macro sdram_init_sha
- 	/*
- 	 * DDR on CSD0
- 	 */
--	writel(0x00000008, 0xD8001010)
--	writel(0x55555555, 0x10027828)
--	writel(0x55555555, 0x10027830)
--	writel(0x55555555, 0x10027834)
--	writel(0x00005005, 0x10027838)
--	writel(0x15555555, 0x1002783C)
--	writel(0x00000004, 0xD8001010)
--	writel(0x006ac73a, 0xD8001004)
--	writel(0x92100000, 0xD8001000)
--	writel(0x00000000, 0xA0000F00)
--	writel(0xA2100000, 0xD8001000)
--	writel(0x00000000, 0xA0000F00)
--	writel(0x00000000, 0xA0000F00)
--	writel(0x00000000, 0xA0000F00)
--	writel(0x00000000, 0xA0000F00)
--	writel(0xA2200000, 0xD8001000)
--	writel(0x00000000, 0xA0000F00)
--	writel(0x00000000, 0xA0000F00)
--	writel(0x00000000, 0xA0000F00)
--	writel(0x00000000, 0xA0000F00)
--	writel(0xb2100000, 0xD8001000)
-+	writel(0xD8001010, 0x00000008)
-+	writel(0x10027828, 0x55555555)
-+	writel(0x10027830, 0x55555555)
-+	writel(0x10027834, 0x55555555)
-+	writel(0x10027838, 0x00005005)
-+	writel(0x1002783C, 0x15555555)
-+	writel(0xD8001010, 0x00000004)
-+	writel(0xD8001004, 0x006ac73a)
-+	writel(0xD8001000, 0x92100000)
-+	writel(0xA0000F00, 0x00000000)
-+	writel(0xD8001000, 0xA2100000)
-+	writel(0xA0000F00, 0x00000000)
-+	writel(0xA0000F00, 0x00000000)
-+	writel(0xA0000F00, 0x00000000)
-+	writel(0xA0000F00, 0x00000000)
-+	writel(0xD8001000, 0xA2200000)
-+	writel(0xA0000F00, 0x00000000)
-+	writel(0xA0000F00, 0x00000000)
-+	writel(0xA0000F00, 0x00000000)
-+	writel(0xA0000F00, 0x00000000)
-+	writel(0xD8001000, 0xb2100000)
- 	ldr		r0, =0xA0000033
- 	mov		r1, #0xda
- 	strb		r1, [r0]
- 	ldr		r0, =0xA1000000
- 	mov		r1, #0xff
- 	strb		r1, [r0]
--	writel(0x82226080, 0xD8001000)
-+	writel(0xD8001000, 0x82226080)
- .endm
- 
- .macro sdram_init_mx27_manual
-@@ -87,31 +180,31 @@ NORMAL_MODE		.long 0x00000000 // system/
- 
- .macro sdram_init_uboot
- 	/* configure 16 bit nor flash on cs0 */
--	writel(0x0000CC03, 0xd8002000)
--	writel(0xa0330D01, 0xd8002004)
--	writel(0x00220800, 0xd8002008)
-+	writel(0xd8002000, 0x0000CC03)
-+	writel(0xd8002004, 0xa0330D01)
-+	writel(0xd8002008, 0x00220800)
- 
- 	/* ddr on csd0 - initial reset */
--	writel(0x00000008, 0xD8001010)
-+	writel(0xD8001010, 0x00000008)
- 
- 	/* configure ddr on csd0 - wait 5000 cycles */
--	writel(0x00000004, 0xD8001010)
--	writel(0x006ac73a, 0xD8001004)
--	writel(0x92100000, 0xD8001000)
--	writel(0x12344321, 0xA0000f00)
--	writel(0xa2100000, 0xD8001000)
--	writel(0x12344321, 0xA0000000)
--	writel(0x12344321, 0xA0000000)
--	writel(0xb2100000, 0xD8001000)
-+	writel(0xD8001010, 0x00000004)
-+	writel(0xD8001004, 0x006ac73a)
-+	writel(0xD8001000, 0x92100000)
-+	writel(0xA0000f00, 0x12344321)
-+	writel(0xD8001000, 0xa2100000)
-+	writel(0xA0000000, 0x12344321)
-+	writel(0xA0000000, 0x12344321)
-+	writel(0xD8001000, 0xb2100000)
- 	ldr		r0, =0xA0000033
- 	mov		r1, #0xda
- 	strb		r1, [r0]
- 	ldr		r0, =0xA1000000
- 	mov		r1, #0xff
- 	strb		r1, [r0]
--	writel(0x82226080, 0xD8001000)
--	writel(0xDEADBEEF, 0xA0000000)
--	writel(0x0000000c, 0xD8001010)
-+	writel(0xD8001000, 0x82226080)
-+	writel(0xA0000000, 0xDEADBEEF)
-+	writel(0xD8001010, 0x0000000c)
- .endm
- 
- .globl board_init_lowlevel
-@@ -122,10 +215,10 @@ lowlevel_init:
- 	mov	r10, lr
- 
- 	/* ahb lite ip interface */
--	writel(0x20040304, AIPI1_PSR0)
--	writel(0xDFFBFCFB, AIPI1_PSR1)
--	writel(0x00000000, AIPI2_PSR0)
--	writel(0xFFFFFFFF, AIPI2_PSR1)
-+	writel(AIPI1_PSR0, 0x20040304)
-+	writel(AIPI1_PSR1, 0xDFFBFCFB)
-+	writel(AIPI2_PSR0, 0x00000000)
-+	writel(AIPI2_PSR1, 0xFFFFFFFF)
- 
- 	/* disable mpll/spll */
- 	ldr r0, =CSCR
-@@ -140,15 +233,15 @@ lowlevel_init:
- 	 *        with 1.2 V core voltage! Find out if this is
- 	 *        documented somewhere.
- 	 */
--	writel(0x04331C23, MPCTL0)	/* MPLL = 199.5*2 MHz               */
--	writel(0x040C2403, SPCTL0)	/* SPLL = FIXME (needs review)      */
-+	writel(MPCTL0, 0x04331C23)	/* MPLL = 199.5*2 MHz               */
-+	writel(SPCTL0, 0x040C2403)	/* SPLL = FIXME (needs review)      */
- 
- 	/*
- 	 * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
- 	 * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
- 	 * System clock (HCLK) = 133 MHz
- 	 */
--	writel(0x33f38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
-+	writel(CSCR, 0x33f38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
- 
- 	/* add some delay here */
- 	mov r1, #0x1000
-@@ -156,17 +249,21 @@ lowlevel_init:
- 	bne 1b
- 
- 	/* clock gating enable */
--	writel(0x00050f08, GPCR)
-+	writel(GPCR, 0x00050f08)
- 
- 	/* peripheral clock divider */
--	writel(0x130410c3, PCDR0)	/* FIXME                            */
--	writel(0x09030908, PCDR1)	/* PERDIV1=08 @133 MHz              */
-+	writel(PCDR0, 0x130410c3)	/* FIXME                            */
-+	writel(PCDR1, 0x09030908)	/* PERDIV1=08 @133 MHz              */
- 					/* PERDIV1=04 @266 MHz              */
- 
- 	/* configure 16 bit nor flash on cs0 */
--	writel(0x0000CC03, 0xD8002000)
--	writel(0xa0330D01, 0xD8002004)
--	writel(0x00220800, 0xD8002008)
-+	writel(0xD8002000, 0x0000CC03)
-+	writel(0xD8002004, 0xa0330D01)
-+	writel(0xD8002008, 0x00220800)
-+
-+
-+    //port_init_sha
-+    writel(DR(PORTA), 0x00000000)	/* init debug port */
- 
- 	/* skip sdram initialization if we run from ram */
- 	cmp	pc, #0xa0000000
-@@ -177,6 +274,5 @@ lowlevel_init:
- 	mov	pc,r10
- 1:
- 	sdram_init_sha
--
- 	mov	pc,r10
- 
---- u-boot-1.3.2/common/cmd_nand.c	2008-03-09 16:20:02.000000000 +0100
-+++ u-boot-new/common/cmd_nand.c	2008-06-24 21:21:14.000000000 +0200
-@@ -179,6 +179,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag,
- 
- 	if (strcmp(cmd, "info") == 0) {
- 
-+        nand_init();		/* go init the NAND */
-+
- 		putc('\n');
- 		for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
- 			if (nand_info[i].name)
-@@ -327,6 +329,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag,
- 		    (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) {
- 			if (read) {
- 				/* read */
-+                printf("nand read opt\n");
-+                udelay(10000);
- 				nand_read_options_t opts;
- 				memset(&opts, 0, sizeof(opts));
- 				opts.buffer	= (u_char*) addr;
-@@ -336,6 +340,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag,
- 				ret = nand_read_opts(nand, &opts);
- 			} else {
- 				/* write */
-+                printf("nand write opt\n");
-+                udelay(10000);
- 				nand_write_options_t opts;
- 				memset(&opts, 0, sizeof(opts));
- 				opts.buffer	= (u_char*) addr;
-@@ -349,17 +355,27 @@ int do_nand(cmd_tbl_t * cmdtp, int flag,
- 			}
- 		} else if (s != NULL && !strcmp(s, ".oob")) {
- 			/* read out-of-band data */
--			if (read)
-+			if (read){
-+                printf("nand read out-of-band data\n");
-+                udelay(10000);
- 				ret = nand->read_oob(nand, off, size, (size_t *) &size,
- 						     (u_char *) addr);
--			else
-+            }
-+			else{
-+                printf("nand write out-of-band data\n");
-+                udelay(10000);
- 				ret = nand->write_oob(nand, off, size, (size_t *) &size,
- 						      (u_char *) addr);
-+            }
- 		} else {
--			if (read)
-+			if (read){
- 				ret = nand_read(nand, off, &size, (u_char *)addr);
--			else
--				ret = nand_write(nand, off, &size, (u_char *)addr);
-+            }
-+			else{
-+                 printf("nand write\n");
-+                udelay(10000);
-+				ret = nand_write(nand, off, &size, (u_char *)addr); 
-+            }
- 		}
- 
- 		printf(" %d bytes %s: %s\n", size,
---- u-boot-1.3.2/cpu/arm926ejs/imx27/interrupt.c	2008-06-25 04:12:35.000000000 +0200
-+++ u-boot-new/cpu/arm926ejs/imx27/interrupt.c	2008-06-24 03:04:14.000000000 +0200
-@@ -100,6 +100,11 @@ void set_timer (ulong t)
- {
- }
- 
-+void reset_timer(void)
-+{
-+	reset_timer_masked();
-+}
-+
- /*
-  * This function is derived from PowerPC code (read timebase as long long).
-  * On ARM it just returns the timer value.
---- u-boot-1.3.2/cpu/arm926ejs/imx27/Makefile	2008-06-25 04:12:35.000000000 +0200
-+++ u-boot-new/cpu/arm926ejs/imx27/Makefile	2008-06-23 20:04:37.000000000 +0200
-@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
- 
- LIB	= $(obj)lib$(SOC).a
- 
--COBJS	= interrupt.o serial.o generic.o fec132.o fec_imx27.o miiphy.o
-+COBJS	= interrupt.o serial.o generic.o fec132.o fec_imx27.o miiphy.o nand.o
- 
- SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
- OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
---- u-boot-1.3.2/cpu/arm926ejs/imx27/nand.c	1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-new/cpu/arm926ejs/imx27/nand.c	2008-06-24 22:58:01.000000000 +0200
-@@ -0,0 +1,975 @@
-+/*
-+ * (C) Copyright 2008 (nc) Armadeus Systems
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <common.h>
-+#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-+
-+#include <asm/errno.h>
-+#include <nand.h>
-+#include <asm/arch/imx-regs.h>
-+
-+#ifdef CFG_NFC_DEBUG
-+# define NFC_DEBUG1(fmt, args...) printf(fmt, ##args)
-+#else
-+# define NFC_DEBUG1(fmt, args...)
-+#endif
-+
-+#ifdef CONFIG_MTD_NAND_MXC_SWECC
-+static int hardware_ecc = 0;
-+#else
-+static int hardware_ecc = 1;
-+#endif
-+
-+/*struct nand_info {
-+	bool bSpareOnly;
-+	bool bStatusRequest;
-+	u16 colAddr;
-+    int is2k_Pagesize;
-+};*/
-+
-+static u8 g_bSpareOnly;
-+static u8 g_bStatusRequest;
-+static u16 g_colAddr;
-+static u8 is2k_Pagesize;
-+
-+ /* Macros to get byte and bit positions of ECC
-+ */
-+#define COLPOS(x)  ((x) >> 3)
-+#define BITPOS(x) ((x)& 0xf)
-+
-+
-+#define TROP_US_DELAY   10000
-+
-+#define MIN(x, y)		((x < y) ? x : y)
-+
-+/*
-+ * OOB placement block for use with hardware ecc generation
-+ */
-+static struct nand_oobinfo nand_hw_eccoob_8 = {
-+	.useecc = MTD_NANDECC_AUTOPLACE,
-+	.eccbytes = 5,
-+	.eccpos = {6, 7, 8, 9, 10},
-+	.oobfree = {{2, 3}, {11, 5}}
-+};
-+
-+static struct nand_oobinfo nand_hw_eccoob_16 = {
-+	.useecc = MTD_NANDECC_AUTOPLACE,
-+	.eccbytes = 5,
-+	.eccpos = {6, 7, 8, 9, 10},
-+	.oobfree = {{0, 6}, {12, 4}}
-+};
-+
-+
-+/* These really don't belong here, as they are specific to the NAND Model */
-+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-+
-+static struct nand_bbt_descr delta_bbt_descr = {
-+	.options = 0,
-+	.offs = 0,
-+	.len = 2,
-+	.pattern = scan_ff_pattern
-+};
-+
-+
-+#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
-+static int Ecc_disabled;
-+#endif
-+
-+//static struct nand_info g_nandfc_info;
-+
-+/*
-+ * not required for iMX27 NFC
-+ */
-+static void nfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
-+{
-+	return;
-+}
-+
-+/*!
-+ * This functions is used by upper layer to checks if device is ready
-+ *
-+ * @param       mtd     MTD structure for the NAND Flash
-+ *
-+ * @return  0 if device is busy else 1
-+ */
-+static int nfc_dev_ready(struct mtd_info *mtd)
-+{
-+	/* 
-+	 * NFC handles R/B internally.Therefore,this function
-+	 * always returns status as ready.
-+	 */
-+	return 1;
-+}
-+
-+static void wait_op_done(int maxRetries, u16 param)
-+{
-+	while (maxRetries-- > 0) {
-+		if (NFC_CONFIG2 & NFC_CONFIG2_INT) {
-+			NFC_CONFIG2 &= ~NFC_CONFIG2_INT;
-+			break;
-+		}
-+		udelay(1);
-+	}
-+	if (maxRetries <= 0)
-+		printf("wait_op_done (%d): INT not set\n", param);
-+}
-+
-+
-+/*!
-+ * This function issues the specified command to the NAND device and
-+ * waits for completion.
-+ *
-+ * @param       cmd     command for NAND Flash
-+ */
-+static void send_cmd(u16 cmd)
-+{
-+	NFC_DEBUG1("send_cmd(0x%x)\n", cmd);
-+
-+	NFC_FLASH_CMD = (u16) cmd;
-+	NFC_CONFIG2 = NFC_CONFIG2_FCMD;
-+
-+	/* Wait for operation to complete */
-+	wait_op_done(TROP_US_DELAY, cmd);
-+}
-+
-+/*!
-+ * This function sends an address (or partial address) to the
-+ * NAND device.  The address is used to select the source/destination for
-+ * a NAND command.
-+ *
-+ * @param       addr    address to be written to NFC.
-+  */
-+static void send_addr(u16 addr)
-+{
-+	NFC_DEBUG1("send_addr(0x%x)\n", addr);
-+
-+	NFC_FLASH_ADDR = addr;
-+	NFC_CONFIG2 = NFC_CONFIG2_FADD;
-+
-+	/* Wait for operation to complete */
-+	wait_op_done(TROP_US_DELAY, addr);
-+}
-+
-+/*!
-+ * This function requests the NANDFC to initate the transfer
-+ * of data currently in the NANDFC RAM buffer to the NAND device.
-+ *
-+ * @param	buf_id	      Specify Internal RAM Buffer number (0-3)	
-+ * @param       bSpareOnly    set 1 if only the spare area is transferred
-+ */
-+static void send_prog_page(u8 buf_id, u8 bSpareOnly)
-+{
-+	NFC_DEBUG1("send_prog_page (%d)\n", bSpareOnly);
-+
-+	/* NANDFC buffer 0 is used for page read/write */
-+
-+	NFC_BUF_ADDR = buf_id;
-+
-+	/* Configure spare or page+spare access */
-+	if (!is2k_Pagesize) {
-+		if (bSpareOnly) {
-+			NFC_CONFIG1 |= NFC_CONFIG1_SP_EN;
-+		} else {
-+			NFC_CONFIG1 &= ~(NFC_CONFIG1_SP_EN);
-+		}
-+	}
-+	NFC_CONFIG2 = NFC_CONFIG2_FDI;
-+
-+	/* Wait for operation to complete */
-+	wait_op_done(TROP_US_DELAY, bSpareOnly);
-+}
-+
-+/*!
-+ * This function will correct the single bit ECC error
-+ *
-+ * @param  buf_id	Specify Internal RAM Buffer number (0-3)	
-+ * @param  eccpos 	Ecc byte and bit position
-+ * @param  bSpareOnly  	set to 1 if only spare area needs correction
-+ */
-+
-+static void nfc_correct_error(u8 buf_id, u16 eccpos, u8 bSpareOnly)
-+{
-+	u16 col;
-+	u8 pos;
-+	volatile u16 *buf;
-+
-+	/* Get col & bit position of error
-+	   these macros works for both 8 & 16 bits */
-+	col = COLPOS(eccpos);	/* Get half-word position */
-+	pos = BITPOS(eccpos);	/* Get bit position */
-+
-+	NFC_DEBUG1("nfc_correct_error (col=%d pos=%d)\n", col, pos);
-+	/* Set the pointer for main / spare area */
-+	if (!bSpareOnly) {
-+		buf = (volatile u16 *)((ulong) (IMX_NFC_MAIN_AREA0 + (col >> 1) + (512 * buf_id)));
-+	} else {
-+		buf = (volatile u16 *)((ulong) (IMX_NFC_SPARE_AREA0 + (col >> 1) + (16 * buf_id)));
-+	}
-+
-+	/* Fix the data */
-+	*buf ^= (1 << pos);
-+}
-+
-+
-+/*!
-+ * This function will maintains state of single bit Error
-+ * in Main & spare  area
-+ *
-+ * @param buf_id	Specify Internal RAM Buffer number (0-3)	
-+ * @param spare  	set to true if only spare area needs correction
-+ */
-+static void nfc_correct_ecc(u8 buf_id, u8 spare)
-+{
-+#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
-+	static int lastErrMain = 0, lastErrSpare = 0;	/* To maintain single bit
-+							   error in previous page */
-+#endif
-+	u16 value, ecc_status;
-+	/* Read the ECC result */
-+	ecc_status = NFC_ECC_STATUS_RESULT;
-+
-+#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
-+	/* Check for Error in Mainarea */
-+	if ((ecc_status >> NFC_ECC_STAT_ERM_SHFT) == NFC_ECC_STAT_ERROR1) {
-+		/* Check for error in previous page */
-+		if (lastErrMain && !spare) {
-+			value = NFC_ECC_RSLT_MAIN_AREA;
-+			/* Correct single bit error in Mainarea
-+			   NFC will not correct the error in
-+			   current page */
-+			nfc_correct_error(buf_id, value, 0);
-+		} else {
-+			/* Set if single bit error in current page */
-+			lastErrMain = 1;
-+		}
-+	} else {
-+		/* Reset if no single bit error in current page */
-+		lastErrMain = 0;
-+	}
-+
-+	/* Check for Error in Sparearea */
-+	if ((ecc_status & NFC_ECC_STAT_ERS_MASK) == NFC_ECC_STAT_ERROR1) {
-+		/* Check for error in previous page */
-+		if (lastErrSpare) {
-+			value = NFC_ECC_RSLT_SPARE_AREA;
-+			/* Correct single bit error in Mainarea
-+			   NFC will not correct the error in
-+			   current page */&
-+			nfc_correct_error(buf_id, value, 1);
-+		} else {
-+			/* Set if single bit error in current page */
-+			lastErrSpare = 1;
-+		}
-+	} else {
-+		/* Reset if no single bit error in current page */
-+		lastErrSpare = 0;
-+	}
-+#else
-+	if (((ecc_status >> NFC_ECC_STAT_ERM_SHFT) == NFC_ECC_STAT_ERROR1)
-+	    || ((ecc_status & NFC_ECC_STAT_ERS_MASK) == NFC_ECC_STAT_ERROR1)) {
-+		if (Ecc_disabled) {
-+			if ((ecc_status >> NFC_ECC_STAT_ERM_SHFT) == NFC_ECC_STAT_ERROR1) {
-+				value = NFC_ECC_RSLT_MAIN_AREA;
-+				/* Correct single bit error in Mainarea
-+				   NFC will not correct the error in
-+				   current page */
-+				nfc_correct_error(buf_id, value, 0);
-+			}
-+			if ((ecc_status & NFC_ECC_STAT_ERS_MASK) == NFC_ECC_STAT_ERROR1) {
-+				value = NFC_ECC_RSLT_SPARE_AREA;
-+				/* Correct single bit error in Mainarea
-+				   NFC will not correct the error in
-+				   current page */
-+				nfc_correct_error(buf_id, value, 1);
-+			}
-+
-+		} else {
-+			/* Disable ECC  */
-+			NFC_CONFIG1 &= ~(NFC_CONFIG1_ECC_EN);
-+			Ecc_disabled = 1;
-+		}
-+	} else if (ecc_status == 0) {
-+		if (Ecc_disabled) {
-+			/* Enable ECC */
-+			NFC_CONFIG1 |= NFC_CONFIG1_ECC_EN;
-+			Ecc_disabled = 0;
-+		}
-+	} else {
-+		/* 2-bit Error  Do nothing */
-+	}
-+#endif				/* CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 */
-+
-+}
-+
-+
-+
-+/*!
-+ * This function requests the NANDFC to initated the transfer
-+ * of data from the NAND device into in the NANDFC ram buffer.
-+ *
-+ * @param  	buf_id		Specify Internal RAM Buffer number (0-3)	
-+ * @param       bSpareOnly    	set 1 if only the spare area is transferred
-+ */
-+static void send_read_page(u8 buf_id, u8 bSpareOnly)
-+{
-+	NFC_DEBUG1("send_read_page (%d)\n", bSpareOnly);
-+
-+	/* NANDFC buffer 0 is used for page read/write */
-+	NFC_BUF_ADDR = buf_id;
-+
-+	/* Configure spare or page+spare access */
-+	if (!is2k_Pagesize) {
-+		if (bSpareOnly) {
-+			NFC_CONFIG1 |= NFC_CONFIG1_SP_EN;
-+		} else {
-+			NFC_CONFIG1 &= ~(NFC_CONFIG1_SP_EN);
-+		}
-+	}
-+
-+	NFC_CONFIG2 = NFC_CONFIG2_FDO_PAGE;
-+
-+	/* Wait for operation to complete */
-+	wait_op_done(TROP_US_DELAY, bSpareOnly);
-+
-+	/* If there are single bit errors in
-+	   two consecutive page reads then
-+	   the error is not  corrected by the
-+	   NFC for the second page.
-+	   Correct single bit error in driver */
-+
-+	nfc_correct_ecc(buf_id, bSpareOnly);
-+}
-+
-+/*!
-+ * This function requests the NANDFC to perform a read of the
-+ * NAND device ID.
-+ */
-+static void send_read_id(struct mtd_info *mtd)
-+{
-+ 	struct nand_chip *this =  mtd->priv;
-+
-+    NFC_DEBUG1("send_read_id \n");
-+	/* NANDFC buffer 0 is used for device ID output */
-+	NFC_BUF_ADDR = 0x0;
-+
-+	/* Read ID into main buffer */
-+	NFC_CONFIG1 &= (~(NFC_CONFIG1_SP_EN));
-+	NFC_CONFIG2 = NFC_CONFIG2_FDO_ID;
-+
-+	/* Wait for operation to complete */
-+	wait_op_done(TROP_US_DELAY, 0);
-+
-+	if (this->options & NAND_BUSWIDTH_16) {
-+		volatile u16 *mainBuf = (volatile u16 *)((ulong) (IMX_NFC_MAIN_AREA0));
-+
-+		/*
-+		 * Pack the every-other-byte result for 16-bit ID reads
-+		 * into every-byte as the generic code expects and various
-+		 * chips implement.
-+		 */
-+
-+		mainBuf[0] = (mainBuf[0] & 0xff) | ((mainBuf[1] & 0xff) << 8);
-+		mainBuf[1] = (mainBuf[2] & 0xff) | ((mainBuf[3] & 0xff) << 8);
-+		mainBuf[2] = (mainBuf[4] & 0xff) | ((mainBuf[5] & 0xff) << 8);
-+	}
-+}
-+
-+
-+
-+/*!
-+ * This function writes data of length \b len to buffer \b buf. The data to be
-+ * written on NAND Flash is first copied to RAMbuffer. After the Data Input
-+ * Operation by the NFC, the data is written to NAND Flash
-+ *
-+ * @param       mtd     MTD structure for the NAND Flash
-+ * @param       buf     data to be written to NAND Flash
-+ * @param       len     number of bytes to be written
-+ */
-+static void nfc_write_buf(struct mtd_info *mtd,
-+			       const u_char * buf, int len)
-+{
-+	int i = 0;
-+    ulong p;
-+    int nbbytes_main = 0, nbbytes_spare=0;
-+    int bytes_multi = 0;
-+
-+    if (!g_bSpareOnly)
-+    {
-+        /* Main Area */
-+        nbbytes_main = mtd->oobblock - g_colAddr;
-+        if( nbbytes_main > 0 )
-+        {
-+            nbbytes_main = min(len, nbbytes_main);
-+            bytes_multi =  nbbytes_main & 0xFFFFFFFE;
-+            p = (ulong)(IMX_NFC_MAIN_AREA0)+g_colAddr;
-+            for( i=0; i<bytes_multi; i+=2 ){
-+        			*((volatile u16*)(p + i)) = *((u16*) &buf[i]);
-+             }
-+            if( nbbytes_main & 1 ){
-+                *((volatile u16*)(p + i +1)) = buf[i];
-+                i++;
-+            }
-+        }
-+    }
-+	if (g_bSpareOnly && g_colAddr < mtd->oobblock )
-+		g_colAddr += mtd->oobblock;
-+    
-+     /* Spare Area */
-+    nbbytes_spare = len - nbbytes_main;
-+    if( nbbytes_spare )
-+    {
-+        nbbytes_spare = min(mtd->oobsize - g_colAddr+mtd->oobblock, nbbytes_spare);
-+        bytes_multi =  nbbytes_spare & 0xFFFFFFFE;
-+        p = (volatile u16*)((ulong) (IMX_NFC_SPARE_AREA0));
-+        for( i=0; i<bytes_multi; i+=2 ){
-+        		*((volatile u16*)(p + i)) = *((u16*) &buf[nbbytes_main+i]);
-+        }
-+        if( nbbytes_spare & 1 )
-+             *((volatile u16*)(p + i +1)) = buf[nbbytes_main+i+1];
-+    }
-+    g_colAddr += nbbytes_main + nbbytes_spare;
-+}
-+
-+/*
-+ * These functions are quite problematic for the NFC. Luckily they are
-+ * not used in the current nand code, except for nand_command, which
-+ * we've defined our own anyway. 
-+ */
-+static void nfc_write_word(struct mtd_info *mtd, u16 word)
-+{
-+	printf("nfc_write_word: WARNING, this function does not work with the iMX27 NFC!\n");
-+}
-+static void nfc_write_byte(struct mtd_info *mtd, u_char byte)
-+{
-+	printf("nfc_write_byte: WARNING, this function does not work with the iMX27 NFC!\n");
-+}
-+
-+
-+/*!
-+ * This function id is used to read the data buffer from the NAND Flash. To
-+ * read the data from NAND Flash first the data output cycle is initiated by
-+ * the NFC, which copies the data to RAMbuffer. This data of length \b len is
-+ * then copied to buffer \b buf.
-+ *
-+ * @param       mtd     MTD structure for the NAND Flash
-+ * @param       buf     data to be read from NAND Flash
-+ * @param       len     number of bytes to be read
-+ */
-+static void nfc_read_buf(struct mtd_info *mtd, u_char * buf, int len)
-+{
-+	int i = 0;
-+    ulong p;
-+    int nbbytes_main = 0, nbbytes_spare=0;
-+    int bytes_multi = 0;
-+
-+    if (!g_bSpareOnly)
-+    {
-+        /* Main Area */
-+        nbbytes_main = mtd->oobblock - g_colAddr;
-+        if( nbbytes_main > 0 )
-+        {
-+            nbbytes_main = min(len, nbbytes_main);
-+            bytes_multi =  nbbytes_main & 0xFFFFFFFE;
-+            p = (ulong)(IMX_NFC_MAIN_AREA0)+g_colAddr;
-+            for( i=0; i<bytes_multi; i+=2 ){
-+        			*((u16*) &buf[i]) = *((volatile u16*)(p + i));
-+             }
-+            if( nbbytes_main & 1 )
-+                buf[i++] = *((volatile u16*)(p + i +1));
-+        }
-+    }
-+	if (g_bSpareOnly && g_colAddr < mtd->oobblock )
-+		g_colAddr += mtd->oobblock;
-+    
-+     /* Spare Area */
-+    nbbytes_spare = len - nbbytes_main;
-+    if( nbbytes_spare )
-+    {
-+        nbbytes_spare = min(mtd->oobsize - g_colAddr+mtd->oobblock, nbbytes_spare);
-+        bytes_multi =  nbbytes_spare & 0xFFFFFFFE;
-+        p = (volatile u16*)((ulong) (IMX_NFC_SPARE_AREA0));
-+        for( i=0; i<bytes_multi; i+=2 ){
-+        		*((u16*) &buf[nbbytes_main+i]) = *((volatile u16*)(p + i));
-+        }
-+        if( nbbytes_spare & 1 )
-+            buf[nbbytes_main+i+1] = *((volatile u16*)(p + i +1));
-+    }
-+    g_colAddr += nbbytes_main + nbbytes_spare;
-+}
-+
-+/*
-+ * read a word. Not implemented as not used in NAND code.
-+ */
-+static u16 nfc_read_word(struct mtd_info *mtd)
-+{
-+	printf("nfc_read_word: UNIMPLEMENTED.\n");
-+	return 0;
-+}
-+
-+static u16 get_dev_status(void)
-+{
-+	volatile u16 *mainBuf = (volatile u32 *)((ulong) (IMX_NFC_MAIN_AREA1));
-+	u32 store;
-+	u16 ret;
-+	/* Issue status request to NAND device */
-+
-+	/* store the main area1 first word, later do recovery */
-+	store = *((u32 *) mainBuf);
-+	/*
-+	 * NANDFC buffer 1 is used for device status to prevent
-+	 * corruption of read/write buffer on status requests.
-+	 */
-+	NFC_BUF_ADDR = 1;
-+
-+	/* Send the Read status command before reading status */
-+	send_cmd(NAND_CMD_STATUS);
-+
-+	/* Read status into main buffer */
-+	NFC_CONFIG1 &= (~(NFC_CONFIG1_SP_EN));
-+	NFC_CONFIG2 = NFC_CONFIG2_FDO_STATUS;
-+
-+	/* Wait for operation to complete */
-+	wait_op_done(TROP_US_DELAY, 0);
-+
-+	/* get status, then recovery area 1 data */
-+	ret = mainBuf[0];
-+    printf("get_dev_status %x\n", ret);
-+	*((u32 *) mainBuf) = store;
-+
-+	/* Status is placed in first word of main buffer */
-+	return ret;
-+}
-+
-+
-+/*!
-+ * This function reads byte from the NAND Flash
-+ *
-+ * @param       mtd     MTD structure for the NAND Flash
-+ *
-+ * @return    data read from the NAND Flash
-+ */
-+static u_char nfc_read_byte(struct mtd_info *mtd)
-+{
-+	u_char retVal = 0;
-+	u16 col, rdWord;
-+	volatile u16 *mainBuf = (volatile u16 *)((ulong) (IMX_NFC_MAIN_AREA0));
-+	volatile u16 *spareBuf = (volatile u16 *)((ulong) (IMX_NFC_SPARE_AREA0));
-+
-+	/* Check for status request */
-+	if (g_bStatusRequest) {
-+		return (get_dev_status() & 0xFF);
-+	}
-+
-+	/* Get column for 16-bit access */
-+	col = g_colAddr >> 1;
-+
-+	/* If we are accessing the spare region */
-+	if (g_bSpareOnly) {
-+		rdWord = spareBuf[col];
-+	} else {
-+		rdWord = mainBuf[col];
-+	}
-+
-+	/* Pick upper/lower byte of word from RAM buffer */
-+	if (g_colAddr & 0x1) {
-+		retVal = (rdWord >> 8) & 0xFF;
-+	} else {
-+		retVal = rdWord & 0xFF;
-+	}
-+    NFC_DEBUG1("\treval: %x, rdWord:%x \n",retVal, rdWord);
-+
-+	/* Update saved column address */
-+	g_colAddr++;
-+
-+	return retVal;
-+}
-+
-+/* this function is called after Programm and Erase Operations to
-+ * check for success or failure */
-+static int nfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
-+{
-+    wait_op_done(TROP_US_DELAY, 9);
-+	return 0;
-+}
-+
-+static int nfc_correct_data(struct mtd_info *mtd, u_char * dat,
-+				 u_char * read_ecc, u_char * calc_ecc)
-+{
-+	/*
-+	 * 1-Bit errors are automatically corrected in HW.  No need for
-+	 * additional correction.  2-Bit errors cannot be corrected by
-+	 * HW ECC, so we need to return failure
-+	 */
-+	u16 ecc_status = NFC_ECC_STATUS_RESULT;
-+
-+	if (((ecc_status & NFC_ECC_STAT_ERS_MASK) == NFC_ECC_STAT_ERROR2) || 
-+        ((ecc_status >> NFC_ECC_STAT_ERM_SHFT) == NFC_ECC_STAT_ERROR2)) {
-+		return -1;
-+	}
-+
-+	return 0;
-+}
-+
-+
-+/*!
-+ * This function is used by the upper layer to write command to NAND Flash for
-+ * different operations to be carried out on NAND Flash
-+ *
-+ * @param       mtd             MTD structure for the NAND Flash
-+ * @param       command         command for NAND Flash
-+ * @param       column          column offset for the page read
-+ * @param       page_addr       page to be read from NAND Flash
-+ */
-+static void nfc_cmdfunc(struct mtd_info *mtd, unsigned command,
-+			int column, int page_addr)
-+{
-+	NFC_DEBUG1("nfc_cmdfunc (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
-+	      command, column, page_addr);
-+
-+	if ((FMCR & FMCR_NF_FMS) == FMCR_NF_FMS)
-+		is2k_Pagesize = 1;
-+
-+	/*
-+	 * Reset command state information
-+	 */
-+	g_bStatusRequest = 0;
-+
-+	/*
-+	 * Command pre-processing step
-+	 */
-+	switch (command) {
-+
-+	case NAND_CMD_STATUS:
-+		g_colAddr = 0;
-+		g_bStatusRequest = 1;
-+		break;
-+
-+	case NAND_CMD_READ0:
-+		g_colAddr = column;
-+		g_bSpareOnly = 0;
-+		break;
-+
-+	case NAND_CMD_READOOB:
-+		g_colAddr = column;
-+		g_bSpareOnly = 1;
-+		if (is2k_Pagesize)
-+			command = NAND_CMD_READ0;	/* only READ0 is valid */
-+		break;
-+
-+	case NAND_CMD_SEQIN:
-+		if (column >= mtd->oobblock) {
-+			if (is2k_Pagesize) {
-+				/** 			 
-+				  * FIXME: before send SEQIN command for write OOB,
-+				  * We must read one page out. 			 
-+				  * For K9F1GXX has no READ1 command to set current HW 			 
-+				  * pointer to spare area, we must write the whole page including OOB together.			 
-+				  */
-+				/* call itself to read a page */
-+				nfc_cmdfunc(mtd, NAND_CMD_READ0, 0,
-+						 page_addr);
-+			}
-+			g_colAddr = column - mtd->oobblock;
-+			g_bSpareOnly = 1;
-+			/* Set program pointer to spare region */
-+			if (!is2k_Pagesize)
-+				send_cmd(NAND_CMD_READOOB);
-+		} else {
-+			g_bSpareOnly = 0;
-+			g_colAddr = column;
-+			/* Set program pointer to page start */
-+			if (!is2k_Pagesize)
-+				send_cmd(NAND_CMD_READ0);
-+		}
-+		break;
-+
-+	case NAND_CMD_PAGEPROG:
-+#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
-+		if (Ecc_disabled) {
-+			/* Enable Ecc for page writes */
-+			NFC_CONFIG1 |= NFC_CONFIG1_ECC_EN;
-+		}
-+#endif
-+
-+		send_prog_page(0, g_bSpareOnly);
-+
-+		if (is2k_Pagesize) {
-+			/* data in 4 areas datas */
-+			send_prog_page(1, g_bSpareOnly);
-+			send_prog_page(2, g_bSpareOnly);
-+			send_prog_page(3, g_bSpareOnly);
-+		}
-+
-+		break;
-+
-+   	case NAND_CMD_ERASE1:break;
-+    default: break;
-+	}
-+
-+	/*
-+	 * Write out the command to the device.
-+	 */
-+	send_cmd(command);
-+
-+	/*
-+	 * Write out column address, if necessary
-+	 */
-+	if (column != -1) {
-+		/*
-+		 * MXC NANDFC can only perform full page+spare or
-+		 * spare-only read/write.  When the upper layers
-+		 * layers perform a read/write buf operation,
-+		 * we will used the saved column adress to index into
-+		 * the full page.
-+		 */
-+		send_addr(0);
-+		if (is2k_Pagesize)
-+			send_addr(0);	/* another col addr cycle for 2k page */
-+	}
-+
-+	/*
-+	 * Write out page address, if necessary
-+	 */
-+	if (page_addr != -1) {
-+		send_addr(page_addr & 0xff);	/* paddr_0 - p_addr_7 */
-+
-+		if (is2k_Pagesize) {
-+			send_addr((page_addr >> 8) & 0xFF);
-+			if (mtd->size >= 0x42000000) {
-+				send_addr((page_addr >> 16) & 0xff);
-+			}
-+		} else {
-+			/* One more address cycle for higher density devices */
-+			if (mtd->size >= 0x4000000) {
-+				send_addr((page_addr >> 8) & 0xff);	/* paddr_8 - paddr_15 */
-+				send_addr((page_addr >> 16) & 0xff);
-+			} else
-+				send_addr((page_addr >> 8) & 0xff);	/* paddr_8 - paddr_15 */
-+		}
-+	}
-+
-+	/*
-+	 * Command post-processing step
-+	 */
-+	switch (command) {
-+
-+	case NAND_CMD_RESET:
-+		break;
-+
-+	case NAND_CMD_READOOB:
-+	case NAND_CMD_READ0:
-+		if (is2k_Pagesize) {
-+			/* send read confirm command */
-+			send_cmd(NAND_CMD_READSTART);
-+			/* read for each AREA */
-+			send_read_page(0, g_bSpareOnly);
-+			send_read_page(1, g_bSpareOnly);
-+			send_read_page(2, g_bSpareOnly);
-+			send_read_page(3, g_bSpareOnly);
-+		} else {
-+			send_read_page(0, g_bSpareOnly);
-+		}
-+		break;
-+
-+	case NAND_CMD_READID:
-+		send_read_id(mtd);
-+		break;
-+
-+	case NAND_CMD_PAGEPROG:
-+#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
-+		if (Ecc_disabled) {
-+			/* Disble Ecc after page writes */
-+			NFC_CONFIG1 &= ~(NFC_CONFIG1_ECC_EN);
-+		}
-+#endif
-+		break;
-+
-+	case NAND_CMD_STATUS:
-+		break;
-+
-+	case NAND_CMD_ERASE2:
-+		break;
-+	}
-+}
-+
-+/*!
-+ * This function is used by upper layer for select and deselect of the NAND
-+ * chip
-+ *
-+ * @param       mtd     MTD structure for the NAND Flash
-+ * @param       chip    val indicating select or deselect
-+ */
-+static void nfc_select_chip(struct mtd_info *mtd, int chip)
-+{
-+#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
-+	if (chip > 0) {
-+		NFC_DEBUG1("ERROR:  Illegal chip select (chip = %d)\n", chip);
-+		return;
-+	}
-+
-+	if (chip == -1) {
-+		NFC_CONFIG1 &= (~(NFC_CONFIG1_CEn));
-+		return;
-+	}
-+
-+	NFC_CONFIG1 |= NFC_CONFIG1_CEn;
-+#endif
-+    NFC_DEBUG1("nfc_select_chip: %d)\n", chip);
-+	switch (chip) {
-+	case -1:
-+		/* Disable the NFC clock */
-+        PCCR1 &= ~PCCR1_NFC_BAUDEN;
-+		break;
-+	case 0:
-+		/* Enable the NFC clock */
-+        PCCR1 |= PCCR1_NFC_BAUDEN;
-+		break;
-+
-+	default:
-+		break;
-+	}
-+}
-+
-+
-+static void nfc_enable_hwecc(struct mtd_info *mtd, int mode)
-+{
-+	/*
-+	 * If HW ECC is enabled, we turn it on during init.  There is
-+	 * no need to enable again here.
-+	 */
-+}
-+
-+static int nfc_calculate_ecc(struct mtd_info *mtd, const u_char * dat,
-+				  u_char * ecc_code)
-+{
-+	/*
-+	 * Just return success.  HW ECC does not read/write the NFC spare
-+	 * buffer.  Only the FLASH spare area contains the calcuated ECC.
-+	 */
-+	return 0;
-+}
-+
-+/*!
-+ * This function is used by the upper layer to verify the data in NAND Flash
-+ * with the data in the \b buf.
-+ *
-+ * @param       mtd     MTD structure for the NAND Flash
-+ * @param       buf     data to be verified
-+ * @param       len     length of the data to be verified
-+ *
-+ * @return      -EFAULT if error else 0
-+ *
-+ */
-+static int nfc_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
-+{
-+	return -EFAULT;
-+}
-+
-+
-+
-+/*
-+ * Board-specific NAND initialization. The following members of the
-+ * argument are board-specific (per include/linux/mtd/nand_new.h):
-+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
-+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
-+ * - hwcontrol: hardwarespecific function for accesing control-lines
-+ * - dev_ready: hardwarespecific function for  accesing device ready/busy line
-+ * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
-+ *   only be provided if a hardware ECC is available
-+ * - eccmode: mode of ecc, see defines
-+ * - chip_delay: chip dependent delay for transfering data from array to
-+ *   read regs (tR)
-+ * - options: various chip options. They can partly be set to inform
-+ *   nand_scan about special functionality. See the defines for further
-+ *   explanation
-+ * Members with a "?" were not set in the merged testing-NAND branch,
-+ * so they are not set here either.
-+ */
-+int board_nand_init(struct nand_chip *nand)
-+{
-+    g_colAddr = 0;
-+
-+    //memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info));
-+    //nand->priv = g_nandfc_info;
-+
-+	/* 50 us command delay time */
-+	nand->chip_delay = 5;
-+
-+	nand->hwcontrol = nfc_hwcontrol;
-+	//nand->options = NAND_BUSWIDTH_16;
-+	nand->waitfunc = nfc_wait;    /////// tdb
-+	nand->read_byte = nfc_read_byte;
-+	nand->write_byte = nfc_write_byte;
-+	nand->read_word = nfc_read_word;
-+	nand->write_word = nfc_write_word;
-+	nand->read_buf = nfc_read_buf;
-+	nand->write_buf = nfc_write_buf;
-+    nand->dev_ready =nfc_dev_ready;
-+    nand->select_chip = nfc_select_chip;
-+    nand->verify_buf = nfc_verify_buf;
-+
-+	nand->cmdfunc = nfc_cmdfunc;
-+	nand->badblock_pattern = &delta_bbt_descr;
-+
-+	if (hardware_ecc) {
-+		nand->calculate_ecc = nfc_calculate_ecc; //void
-+		nand->enable_hwecc = nfc_enable_hwecc;  // void
-+		nand->correct_data = nfc_correct_data;
-+		nand->eccsize = 512;
-+		nand->eccbytes = 3;
-+    	nand->eccmode = NAND_ECC_HW3_512;
-+		NFC_CONFIG1 |= NFC_CONFIG1_ECC_EN;
-+	} else {
-+		nand->eccmode = NAND_ECC_SOFT;
-+	}
-+
-+	/* NAND bus width determines access funtions used by upper layer */
-+	//if (flash->width == 2) {
-+	//	nand->options |= NAND_BUSWIDTH_16 | NAND_USE_FLASH_BBT;
-+	//	nand->autooob = &nand_hw_eccoob_16;
-+	//} else {
-+		nand->options |= 0;//NAND_USE_FLASH_BBT;
-+        nand->autooob = &nand_hw_eccoob_8;
-+	//}
-+
-+	/* preset operation */
-+	/* Unlock the internal RAM Buffer */
-+	NFC_CONFIG = NFC_CONFIG_UNLOCKED;
-+
-+	/* Blocks to be unlocked */
-+	NFC_UNLOCKSTART_BLKADDR = 0x0;
-+	NFC_UNLOCKEND_BLKADDR = 0x4000;
-+
-+	/* Unlock Block Command for given address range */
-+	NFC_WRPROT = NFC_WRPROT_UNLOCKBLK;
-+
-+
-+
-+	is2k_Pagesize = 0;
-+
-+
-+	return 0;
-+}
-+
-+#endif
-+
-+
---- u-boot-1.3.2/include/asm-arm/arch-imx27/imx-regs.h	2008-06-25 04:12:35.000000000 +0200
-+++ u-boot-new/include/asm-arm/arch-imx27/imx-regs.h	2008-06-24 07:26:49.000000000 +0200
-@@ -62,8 +62,13 @@
- #define IMX_PLL_BASE               (0x27000 + IMX_IO_BASE)
- #define IMX_SYSTEM_CTL_BASE        (0x27800 + IMX_IO_BASE)
- 
--#define IMX_ESD_BASE               (0xd8001000)
--#define IMX_WEIM_BASE              (0xd8002000)
-+#define IMX_NFC_BASE               (0xD8000000)
-+#define IMX_NFC_MAIN_AREA0         (0xD8000000)          
-+#define IMX_NFC_MAIN_AREA1         (0xD8000200)  
-+#define IMX_NFC_SPARE_AREA0        (0xD8000800)          
-+#define IMX_ESD_BASE               (0xD8001000)
-+#define IMX_WEIM_BASE              (0xD8002000)
-+
- 
- /* AIPI */
- #define AIPI1_PSR0	__REG(IMX_AIPI1_BASE + 0x00)
-@@ -72,7 +77,34 @@
- #define AIPI2_PSR1	__REG(IMX_AIPI2_BASE + 0x04)
- 
- /* System Control */
-+#define FMCR	__REG(IMX_SYSTEM_CTL_BASE + 0x14)
- #define GPCR	__REG(IMX_SYSTEM_CTL_BASE + 0x18)
-+#define WBCR	__REG(IMX_SYSTEM_CTL_BASE + 0x1C)
-+#define DSCR1	__REG(IMX_SYSTEM_CTL_BASE + 0x20)
-+#define DSCR2	__REG(IMX_SYSTEM_CTL_BASE + 0x24)
-+#define DSCR3	__REG(IMX_SYSTEM_CTL_BASE + 0x28)
-+#define DSCR4	__REG(IMX_SYSTEM_CTL_BASE + 0x2C)
-+#define DSCR5	__REG(IMX_SYSTEM_CTL_BASE + 0x30)
-+#define DSCR6	__REG(IMX_SYSTEM_CTL_BASE + 0x34)
-+#define DSCR7	__REG(IMX_SYSTEM_CTL_BASE + 0x38)
-+#define DSCR8	__REG(IMX_SYSTEM_CTL_BASE + 0x3C)
-+#define DSCR9	__REG(IMX_SYSTEM_CTL_BASE + 0x40)
-+#define DSCR10	__REG(IMX_SYSTEM_CTL_BASE + 0x44)
-+#define DSCR11	__REG(IMX_SYSTEM_CTL_BASE + 0x48)
-+#define DSCR12	__REG(IMX_SYSTEM_CTL_BASE + 0x4C)
-+#define DSCR13	__REG(IMX_SYSTEM_CTL_BASE + 0x50)
-+#define PSCR	__REG(IMX_SYSTEM_CTL_BASE + 0x54)
-+#define PMCR	__REG(IMX_SYSTEM_CTL_BASE + 0x58)
-+#define DCVR0	__REG(IMX_SYSTEM_CTL_BASE + 0x60)
-+#define DCVR1	__REG(IMX_SYSTEM_CTL_BASE + 0x64)
-+#define DCVR2	__REG(IMX_SYSTEM_CTL_BASE + 0x68)
-+#define DCVR3	__REG(IMX_SYSTEM_CTL_BASE + 0x6C)
-+
-+/* System Control bit definition*/
-+#define FMCR_NF_FMS         (1<<5)
-+#define FMCR_NF_16BIT_SEL   (1<<4)	
-+
-+
- 
- /* Chip Select Registers */
- #define CS0U __REG(IMX_WEIM_BASE + 0x00) /* Chip Select 0 Upper Register    */
-@@ -317,6 +349,13 @@
-  *  i.MX1 and i.MXL: 0 <= x <= 3
-  *  i.MX27         : 0 <= x <= 5
-  */
-+#define PORTA 0
-+#define PORTB 1
-+#define PORTC 2
-+#define PORTD 3
-+#define PORTE 4
-+#define PORTF 5
-+
- #define DDIR(x)    __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8)
- #define OCR1(x)    __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8)
- #define OCR2(x)    __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8)
-@@ -340,12 +379,12 @@
- #define GPIO_PORT_SHIFT 5
- #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
- 
--#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
--#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
--#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
--#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
--#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
--#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
-+#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT)
-+#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT)
-+#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT)
-+#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT)
-+#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT)
-+#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT)
- 
- #define GPIO_OUT   (1 << 8)
- #define GPIO_IN    (0 << 8)
-@@ -398,4 +437,58 @@
- #define I2SR_IIF 	(1<<1)		/* I2C interrupt */
- #define I2SR_RXAK 	(1<<0)		/* I2C Received Acknowledge */
- 
-+/*
-+ * NFC module
-+ */
-+#define NFC_BUFSIZE             __REG16(IMX_NFC_BASE + 0xE00) /* Internal SRAM Size */
-+#define NFC_BLCK_ADD_LOCK       __REG16(IMX_NFC_BASE + 0xE02) /* NAND Flash Block
-+                                                             Address for Lock Check */
-+#define NFC_BUF_ADDR            __REG16(IMX_NFC_BASE + 0xE04) /* Buffer Number for Page Data Transfer To/
-+                                                                From Flash Memory */
-+#define NFC_FLASH_ADDR          __REG16(IMX_NFC_BASE + 0xE06) /* NAND Flash Address */
-+#define NFC_FLASH_CMD           __REG16(IMX_NFC_BASE + 0xE08) /* NAND Flash Command */
-+#define NFC_CONFIG              __REG16(IMX_NFC_BASE + 0xE0A) /* NFC Internal Buffer Lock Control */
-+#define NFC_ECC_STATUS_RESULT   __REG16(IMX_NFC_BASE + 0xE0C) /* Controller Status/Result of Flash Operation */
-+#define NFC_ECC_RSLT_MAIN_AREA  __REG16(IMX_NFC_BASE + 0xE0E) /* ECC Error Position of Main Area Data Error */
-+#define NFC_ECC_RSLT_SPARE_AREA __REG16(IMX_NFC_BASE + 0xE10) /* ECC Error Position of Spare Area Data Error */
-+#define NFC_WRPROT              __REG16(IMX_NFC_BASE + 0xE12) /* Nand Flash Write Protection */
-+#define NFC_UNLOCKSTART_BLKADDR __REG16(IMX_NFC_BASE + 0xE14) /* Start Address for Write Protection Unlock */
-+#define NFC_UNLOCKEND_BLKADDR   __REG16(IMX_NFC_BASE + 0xE16) /* End Address for Write Protection Unlock */
-+#define NFC_WRPR_STAT           __REG16(IMX_NFC_BASE + 0xE18) /* Current Nand Flash Write Protection Status */
-+#define NFC_CONFIG1             __REG16(IMX_NFC_BASE + 0xE1A) /* Nand Flash Operation Configuration 1 */
-+#define NFC_CONFIG2             __REG16(IMX_NFC_BASE + 0xE1C) /* Nand Flash Operation Configuration 2 */
-+
-+/* NFC_ECC_STATUS_RESULT Status Register Bit Fields */
-+#define NFC_ECC_STAT_ERM_SHFT 	(2)		    /* ERM shift */
-+#define NFC_ECC_STAT_ERS_MASK 	(0x03)		/* ERS mask  */
-+#define NFC_ECC_STAT_ERROR1 	(1<<0)		/* correctable error */
-+#define NFC_ECC_STAT_ERROR2 	(1<<1)		/* non correctable error */
-+
-+/* NFC_CONFIG Control Register Bit Fields */
-+#define NFC_CONFIG_UNLOCKED     (1<<1)		/* unlocked */
-+#define NFC_CONFIG_LOCKED       (1<<0)		/* locked */
-+/* NFC_WRPROT Control Register Bit Fields */
-+#define NFC_WRPROT_UNLOCKBLK    (4<<0)		/* unlock block according to given address range */
-+#define NFC_WRPROT_LOCKALL 	    (2<<0)		/* lock all */
-+#define NFC_WRPROT_LOCKTIGHT    (1<<0)		/* lock-tight locked blocks */
-+/* NFC_WRPR_STAT Status Register Bit Fields */
-+#define NFC_WRPR_US 	(1<<2)		/* Unlocked status	*/
-+#define NFC_WRPR_LS 	(1<<1)		/* Locked status */
-+#define NFC_WRPR_LTS 	(1<<0)		/* Lock-tight Status */
-+/* NFC_CONFIG1 Control Register Bit Fields */
-+#define NFC_CONFIG1_CEn 	(1<<7)		/* Flash force CE */
-+#define NFC_CONFIG1_RST 	(1<<6)		/* Reset */
-+#define NFC_CONFIG1_BIG 	(1<<5)		/* Big Endian Mode */
-+#define NFC_CONFIG1_INT_MSK (1<<4)		/* Mask Interrupt Bit	*/
-+#define NFC_CONFIG1_ECC_EN 	(1<<3)		/* ECC operation enable */
-+#define NFC_CONFIG1_SP_EN 	(1<<2)		/* Flash spare enable */
-+/* NFC_CONFIG2 Control Register Bit Fields */
-+#define NFC_CONFIG2_INT	        (1<<15)		/* Interrupt */
-+#define NFC_CONFIG2_FDO_STATUS	(4<<3)		/* Flash status output */
-+#define NFC_CONFIG2_FDO_ID	    (2<<3)		/* Flash ID output */
-+#define NFC_CONFIG2_FDO_PAGE    (1<<3)		/* Flash data output */
-+#define NFC_CONFIG2_FDI         (1<<2)		/* Flash data input	*/
-+#define NFC_CONFIG2_FADD 	    (1<<1)		/* Flash address input */
-+#define NFC_CONFIG2_FCMD 	    (1<<0)		/* Flash command input */
- #endif				/* _IMX_REGS_H */
-+
---- u-boot-1.3.2/include/configs/pcm038.h	2008-06-25 04:12:35.000000000 +0200
-+++ u-boot-new/include/configs/pcm038.h	2008-06-24 22:12:48.000000000 +0200
-@@ -78,7 +78,7 @@
-  * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
-  * functionality or size of u-boot code.
-  */
--/*#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		\
-+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		\
- 				| CFG_CMD_NET		\
- 				| CFG_CMD_PING		\
- 				| CFG_CMD_DHCP		\
-@@ -86,11 +86,12 @@
- 				| CFG_CMD_I2C		\
- 				| CFG_CMD_DATE		\
- 				| CFG_CMD_EEPROM	\
-+                | CFG_CMD_NAND      \
- 				| CONFIG_CMD_ALL	\
- 				)
- 
--#include <cmd_confdefs.h>
--*/
-+//#include <cmd_confdefs.h>
-+
- #include <config_cmd_default.h>
- #define CONFIG_CMD_PING
- #define CONFIG_CMD_DHCP
-@@ -128,7 +129,8 @@
- #define CONFIG_DOS_PARTITION
- /*#define CONFIG_ISO_PARTITION
- */
--#undef CONFIG_CMD_NAND
-+#define CONFIG_CMD_NAND
-+#define CONFIG_NEW_NAND_CODE
- #undef CONFIG_CMD_ONENAND
- #undef CONFIG_CMD_PCMCIA
- #undef CONFIG_CMD_USB
-@@ -149,7 +151,7 @@
- /* eval_board=evk9328
-  * Boot options. Setting delay to -1 stops autostart count down.
-  */
--#define CONFIG_BOOTDELAY	20
-+#define CONFIG_BOOTDELAY	-1
- 
- #define CONFIG_BOOTARGS \
- 	CONFIG_CONSOLE " root=/dev/mtdblock3 rootfstype=jffs2 "CONFIG_MTDPARTS
-@@ -277,6 +279,17 @@
- #define CONFIG_STACKSIZE_FIQ	(4<<10)		/* FIQ stack                  */
- #endif
- 
-+
-+/*=====================*/
-+/* Flash & Environment */
-+/*=====================*/
-+#define CFG_MAX_NAND_DEVICE	1
-+#define NAND_MAX_CHIPS		1
-+#define CFG_NAND_BASE		(0xD8000000)
-+//#define CONFIG_MTD_NAND_VERIFY_WRITE 1
-+//#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
-+/*=====================*/
-+
- /*
- * Clocks configuration
- */
-@@ -730,18 +743,15 @@
- /*
-  * Default configuration for GPIOs and peripherals
-  */
--#define CFG_DDIR_A_VAL		0x00000000
--#define CFG_OCR1_A_VAL		0x00000000
--#define CFG_OCR2_A_VAL		0x00000000
-+#define CFG_DDIR_A_VAL		0x00FFFFC0  /* for debug */
-+#define CFG_OCR1_A_VAL		0xFFFFF000  /* for debug */
-+#define CFG_OCR2_A_VAL		0x0000FFFF
- #define CFG_ICFA1_A_VAL		0xFFFFFFFF
- #define CFG_ICFA2_A_VAL		0xFFFFFFFF
- #define CFG_ICFB1_A_VAL		0xFFFFFFFF
- #define CFG_ICFB2_A_VAL		0xFFFFFFFF
- #define CFG_DR_A_VAL		0x00000000
--
--/* Setup for PA23 which is Reset Default PA23 but has to become
--   CS5 */
--#define CFG_GIUS_A_VAL		0x00007FF8
-+#define CFG_GIUS_A_VAL		0xFFFFFFFF
- #define CFG_ICR1_A_VAL		0x00000000
- #define CFG_ICR2_A_VAL		0x00000000
- #define CFG_IMR_A_VAL		0x00000000
-@@ -756,7 +766,7 @@
- #define CFG_ICFB1_B_VAL		0xFFFFFFFF
- #define CFG_ICFB2_B_VAL		0xFFFFFFFF
- #define CFG_DR_B_VAL		0x00000000
--#define CFG_GIUS_B_VAL		0xFFFFFFFF
-+#define CFG_GIUS_B_VAL		0xFF3FFFF3
- #define CFG_ICR1_B_VAL		0x00000000
- #define CFG_ICR2_B_VAL		0x00000000
- #define CFG_IMR_B_VAL		0x00000000
-@@ -771,12 +781,12 @@
- #define CFG_ICFB1_C_VAL		0xFFFFFFFF
- #define CFG_ICFB2_C_VAL		0xFFFFFFFF
- #define CFG_DR_C_VAL		0x00000000
--#define CFG_GIUS_C_VAL		0x0007FFFF
-+#define CFG_GIUS_C_VAL		0xFFFFFFFF
- #define CFG_ICR1_C_VAL		0x00000000
- #define CFG_ICR2_C_VAL		0x00000000
- #define CFG_IMR_C_VAL		0x00000000
- #define CFG_GPR_C_VAL		0x00000000
--#define CFG_PUEN_C_VAL		0xF913FFFF
-+#define CFG_PUEN_C_VAL		0xFFFFFFFF
- 
- #define CFG_DDIR_D_VAL		0x00000000
- #define CFG_OCR1_D_VAL		0x00000000
-@@ -786,13 +796,43 @@
- #define CFG_ICFB1_D_VAL		0xFFFFFFFF
- #define CFG_ICFB2_D_VAL		0xFFFFFFFF
- #define CFG_DR_D_VAL		0x00000000
--#define CFG_GIUS_D_VAL		0xFFFFFFFF
-+#define CFG_GIUS_D_VAL		0xFFFE0000
- #define CFG_ICR1_D_VAL		0x00000000
- #define CFG_ICR2_D_VAL		0x00000000
- #define CFG_IMR_D_VAL		0x00000000
- #define CFG_GPR_D_VAL		0x00000000
- #define CFG_PUEN_D_VAL		0xFFFFFFFF
- 
-+#define CFG_DDIR_E_VAL		0x00000000
-+#define CFG_OCR1_E_VAL		0x00000000
-+#define CFG_OCR2_E_VAL		0x00000000
-+#define CFG_ICFA1_E_VAL		0xFFFFFFFF
-+#define CFG_ICFA2_E_VAL		0xFFFFFFFF
-+#define CFG_ICFB1_E_VAL		0xFFFFFFFF
-+#define CFG_ICFB2_E_VAL		0xFFFFFFFF
-+#define CFG_DR_E_VAL		0x00000000
-+#define CFG_GIUS_E_VAL		0xFFFC0F27
-+#define CFG_ICR1_E_VAL		0x00000000
-+#define CFG_ICR2_E_VAL		0x00000000
-+#define CFG_IMR_E_VAL		0x00000000
-+#define CFG_GPR_E_VAL		0x00000000
-+#define CFG_PUEN_E_VAL		0xFFFFFFFF
-+
-+#define CFG_DDIR_F_VAL		0x00000000
-+#define CFG_OCR1_F_VAL		0x00000000
-+#define CFG_OCR2_F_VAL		0x00000000
-+#define CFG_ICFA1_F_VAL		0xFFFFFFFF
-+#define CFG_ICFA2_F_VAL		0xFFFFFFFF
-+#define CFG_ICFB1_F_VAL		0xFFFFFFFF
-+#define CFG_ICFB2_F_VAL		0xFFFFFFFF
-+#define CFG_DR_F_VAL		0x00000000
-+#define CFG_GIUS_F_VAL		0xFF000000
-+#define CFG_ICR1_F_VAL		0x00000000
-+#define CFG_ICR2_F_VAL		0x00000000
-+#define CFG_IMR_F_VAL		0x00000000
-+#define CFG_GPR_F_VAL		0x00000000
-+#define CFG_PUEN_F_VAL		0xFFFFFFFF
-+
- #define CFG_GPCR_VAL		0x000003AB
- 
- /* FMCR Bit 1 becomes 0 to make CS3 if we have only one sdram bank*/
---- u-boot-1.3.2/lib_arm/board.c	2008-06-25 04:12:35.000000000 +0200
-+++ u-boot-new/lib_arm/board.c	2008-06-24 12:21:12.000000000 +0200
-@@ -342,7 +342,7 @@ void start_armboot (void)
- 
- #if defined(CONFIG_CMD_NAND)
- 	puts ("NAND:  ");
--	nand_init();		/* go init the NAND */
-+	//nand_init();		/* go init the NAND */
- #endif
- 
- #if defined(CONFIG_CMD_ONENAND)


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[Armadeus-commitlog] SF.net SVN: armadeus: [825] trunk/target/demos/armanoid/Makefile

From: <ar...@us...> - 2008-07-04 18:11:49

Revision: 825
          http://armadeus.svn.sourceforge.net/armadeus/?rev=825&view=rev
Author:   artemys
Date:     2008-07-04 11:11:58 -0700 (Fri, 04 Jul 2008)

Log Message:
-----------
[DEMOS] Correct Armanoid Makefile to let it handle TARGET=arm

Modified Paths:
--------------
    trunk/target/demos/armanoid/Makefile

Modified: trunk/target/demos/armanoid/Makefile
===================================================================
--- trunk/target/demos/armanoid/Makefile	2008-06-28 13:11:33 UTC (rev 824)
+++ trunk/target/demos/armanoid/Makefile	2008-07-04 18:11:58 UTC (rev 825)
@@ -1,26 +1,26 @@
 
-ifeq ($(TARGET),)
-	BUILDROOT_DIR:=../../../buildroot/
-	BUILD_DIR_EXT:=$(shell ls $(BUILDROOT_DIR) | grep -e "^build_arm*")
-	BUILD_DIR:=$(BUILDROOT_DIR)/$(BUILD_DIR_EXT)
-
-	SDL_DIR:=$(BUILD_DIR)/SDL-1.2.11/
-	STAGING_DIR:=$(BUILD_DIR)/staging_dir/
-	ROOT_DIR:=$(BUILDROOT_DIR)/project_$(BUILD_DIR_EXT)/armadeus/root/
-        INSTALL_DIR:=$(ROOT_DIR)/usr/games/
-	INSTALL_DATA_DIR:=$(ROOT_DIR)/usr/share/games/armanoid/
-
-	CC:=$(STAGING_DIR)/bin/arm-linux-gcc
-	DEFINES="TARGET"
-	CFLAGS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --cflags)
-	LIBS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --libs)
-else
+ifeq ($(TARGET),x86)
 	INSTALL_DIR="/usr/games/"
 	INSTALL_DATA_DIR="/usr/share/games/armanoid/"
 	CFLAGS=`/usr/bin/sdl-config --cflags`
 	LIBS=`/usr/bin/sdl-config --libs`
 	CC=gcc
 	DEFINES="HOST"
+else
+        BUILDROOT_DIR:=../../../buildroot/
+        BUILD_DIR_EXT:=$(shell ls $(BUILDROOT_DIR) | grep -e "^build_arm*")
+        BUILD_DIR:=$(BUILDROOT_DIR)/$(BUILD_DIR_EXT)
+
+        SDL_DIR:=$(BUILD_DIR)/SDL-1.2.11/
+        STAGING_DIR:=$(BUILD_DIR)/staging_dir/
+        ROOT_DIR:=$(BUILDROOT_DIR)/project_$(BUILD_DIR_EXT)/armadeus/root/
+        INSTALL_DIR:=$(ROOT_DIR)/usr/games/
+        INSTALL_DATA_DIR:=$(ROOT_DIR)/usr/share/games/armanoid/
+
+        CC:=$(STAGING_DIR)/bin/arm-linux-gcc
+        DEFINES="TARGET"
+        CFLAGS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --cflags)
+        LIBS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --libs)
 endif
 
 CFLAGS+="-g"


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[Armadeus-commitlog] SF.net SVN: armadeus: [824] trunk/buildroot/target/device/armadeus/rootfs/ target_skeleton/etc

From: <ar...@us...> - 2008-06-28 13:11:25

Revision: 824
          http://armadeus.svn.sourceforge.net/armadeus/?rev=824&view=rev
Author:   artemys
Date:     2008-06-28 06:11:33 -0700 (Sat, 28 Jun 2008)

Log Message:
-----------
[BUILDROOT] Add fr & de keyboard maps to rootfs skeleton

Added Paths:
-----------
    trunk/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/i18n/
    trunk/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/i18n/de.kmap
    trunk/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/i18n/fr.kmap

Added: trunk/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/i18n/de.kmap
===================================================================
(Binary files differ)


Property changes on: trunk/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/i18n/de.kmap
___________________________________________________________________
Name: svn:mime-type
   + application/octet-stream

Added: trunk/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/i18n/fr.kmap
===================================================================
(Binary files differ)


Property changes on: trunk/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/i18n/fr.kmap
___________________________________________________________________
Name: svn:mime-type
   + application/octet-stream


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[Armadeus-commitlog] SF.net SVN: armadeus: [823] branches/apf2/buildroot/target/device/armadeus/ u-boot/patches/1.3.2/320-u-boot-1.3.2.imx27nand.patch

From: <th...@us...> - 2008-06-27 12:10:31

Revision: 823
          http://armadeus.svn.sourceforge.net/armadeus/?rev=823&view=rev
Author:   thom25
Date:     2008-06-27 05:10:38 -0700 (Fri, 27 Jun 2008)

Log Message:
-----------
[UBOOT] first NAND support. tests needed 

Added Paths:
-----------
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/320-u-boot-1.3.2.imx27nand.patch

Added: branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/320-u-boot-1.3.2.imx27nand.patch
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/320-u-boot-1.3.2.imx27nand.patch	                        (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/320-u-boot-1.3.2.imx27nand.patch	2008-06-27 12:10:38 UTC (rev 823)
@@ -0,0 +1,1656 @@
+--- u-boot-1.3.2/board/pcm038/lowlevel_init.S	2008-06-25 04:12:34.000000000 +0200
++++ u-boot-new/board/pcm038/lowlevel_init.S	2008-06-14 22:15:02.000000000 +0200
+@@ -10,45 +10,138 @@
+ 
+ 
+ 
+-#define writel(val, reg) \
++#define writel(reg, val) \
+ 	ldr		r0,	=reg;	\
+ 	ldr		r1,	=val;	\
+ 	str		r1,   [r0];
+ 
+ #define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn)  (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
+ 
++.macro port_init_sha
++/* PORTA */
++    writel( DR(PORTA), CFG_DR_A_VAL)
++    writel( OCR1(PORTA), CFG_OCR1_A_VAL)
++    writel( OCR2(PORTA), CFG_OCR2_A_VAL)
++    writel( ICONFA1(PORTA), CFG_ICFA1_A_VAL)
++    writel( ICONFA2(PORTA), CFG_ICFA2_A_VAL)
++    writel( ICONFB1(PORTA), CFG_ICFB1_A_VAL)
++    writel( ICONFB2(PORTA), CFG_ICFB2_A_VAL)
++    writel( ICR1(PORTA), CFG_ICR1_A_VAL)
++    writel( ICR2(PORTA), CFG_ICR2_A_VAL)
++    writel( IMR(PORTA), CFG_IMR_A_VAL)
++    writel( DDIR(PORTA), CFG_DDIR_A_VAL)
++    writel( GPR(PORTA), CFG_GPR_A_VAL)
++    writel( PUEN(PORTA), CFG_PUEN_A_VAL)
++    writel( GIUS(PORTA), CFG_GIUS_A_VAL)
++/* PORTB */
++    writel( DR(PORTB), CFG_DR_B_VAL)
++    writel( OCR1(PORTB), CFG_OCR1_B_VAL)
++    writel( OCR2(PORTB), CFG_OCR2_B_VAL)
++    writel( ICONFA1(PORTB), CFG_ICFA1_B_VAL)
++    writel( ICONFA2(PORTB), CFG_ICFA2_B_VAL)
++    writel( ICONFB1(PORTB), CFG_ICFB1_B_VAL)
++    writel( ICONFB2(PORTB), CFG_ICFB2_B_VAL)
++    writel( ICR1(PORTB), CFG_ICR1_B_VAL)
++    writel( ICR2(PORTB), CFG_ICR2_B_VAL)
++    writel( IMR(PORTB), CFG_IMR_B_VAL)
++    writel( DDIR(PORTB), CFG_DDIR_B_VAL)
++    writel( GPR(PORTB), CFG_GPR_B_VAL)
++    writel( PUEN(PORTB), CFG_PUEN_B_VAL)
++    writel( GIUS(PORTB), CFG_GIUS_B_VAL)
++/* PORTC */
++    writel( DR(PORTC), CFG_DR_C_VAL)
++    writel( OCR1(PORTC), CFG_OCR1_C_VAL)
++    writel( OCR2(PORTC), CFG_OCR2_C_VAL)
++    writel( ICONFA1(PORTC), CFG_ICFA1_C_VAL)
++    writel( ICONFA2(PORTC), CFG_ICFA2_C_VAL)
++    writel( ICONFB1(PORTC), CFG_ICFB1_C_VAL)
++    writel( ICONFB2(PORTC), CFG_ICFB2_C_VAL)
++    writel( ICR1(PORTC), CFG_ICR1_C_VAL)
++    writel( ICR2(PORTC), CFG_ICR2_C_VAL)
++    writel( IMR(PORTC), CFG_IMR_C_VAL)
++    writel( DDIR(PORTC), CFG_DDIR_C_VAL)
++    writel( GPR(PORTC), CFG_GPR_C_VAL)
++    writel( PUEN(PORTC), CFG_PUEN_C_VAL)
++    writel( GIUS(PORTC), CFG_GIUS_C_VAL)
++/* PORTD */
++    writel( DR(PORTD), CFG_DR_D_VAL)
++    writel( OCR1(PORTD), CFG_OCR1_D_VAL)
++    writel( OCR2(PORTD), CFG_OCR2_D_VAL)
++    writel( ICONFA1(PORTD), CFG_ICFA1_D_VAL)
++    writel( ICONFA2(PORTD), CFG_ICFA2_D_VAL)
++    writel( ICONFB1(PORTD), CFG_ICFB1_D_VAL)
++    writel( ICONFB2(PORTD), CFG_ICFB2_D_VAL)
++    writel( ICR1(PORTD), CFG_ICR1_D_VAL)
++    writel( ICR2(PORTD), CFG_ICR2_D_VAL)
++    writel( IMR(PORTD), CFG_IMR_D_VAL)
++    writel( DDIR(PORTD), CFG_DDIR_D_VAL)
++    writel( GPR(PORTD), CFG_GPR_D_VAL)
++    writel( PUEN(PORTD), CFG_PUEN_D_VAL)
++    writel( GIUS(PORTD), CFG_GIUS_D_VAL)
++/* PORTE */
++    writel( DR(PORTE), CFG_DR_E_VAL)
++    writel( OCR1(PORTE), CFG_OCR1_E_VAL)
++    writel( OCR2(PORTE), CFG_OCR2_E_VAL)
++    writel( ICONFA1(PORTE), CFG_ICFA1_E_VAL)
++    writel( ICONFA2(PORTE), CFG_ICFA2_E_VAL)
++    writel( ICONFB1(PORTE), CFG_ICFB1_E_VAL)
++    writel( ICONFB2(PORTE), CFG_ICFB2_E_VAL)
++    writel( ICR1(PORTE), CFG_ICR1_E_VAL)
++    writel( ICR2(PORTE), CFG_ICR2_E_VAL)
++    writel( IMR(PORTE), CFG_IMR_E_VAL)
++    writel( DDIR(PORTE), CFG_DDIR_E_VAL)
++    writel( GPR(PORTE), CFG_GPR_E_VAL)
++    writel( PUEN(PORTE), CFG_PUEN_E_VAL)
++    writel( GIUS(PORTE), CFG_GIUS_E_VAL)
++/* PORTF */
++    writel( DR(PORTF), CFG_DR_F_VAL)
++    writel( OCR1(PORTF), CFG_OCR1_F_VAL)
++    writel( OCR2(PORTF), CFG_OCR2_F_VAL)
++    writel( ICONFA1(PORTF), CFG_ICFA1_F_VAL)
++    writel( ICONFA2(PORTF), CFG_ICFA2_F_VAL)
++    writel( ICONFB1(PORTF), CFG_ICFB1_F_VAL)
++    writel( ICONFB2(PORTF), CFG_ICFB2_F_VAL)
++    writel( ICR1(PORTF), CFG_ICR1_F_VAL)
++    writel( ICR2(PORTF), CFG_ICR2_F_VAL)
++    writel( IMR(PORTF), CFG_IMR_F_VAL)
++    writel( DDIR(PORTF), CFG_DDIR_F_VAL)
++    writel( GPR(PORTF), CFG_GPR_F_VAL)
++    writel( PUEN(PORTF), CFG_PUEN_F_VAL)
++    writel( GIUS(PORTF), CFG_GIUS_F_VAL)
++.endm
++
+ .macro sdram_init_sha
+ 	/*
+ 	 * DDR on CSD0
+ 	 */
+-	writel(0x00000008, 0xD8001010)
+-	writel(0x55555555, 0x10027828)
+-	writel(0x55555555, 0x10027830)
+-	writel(0x55555555, 0x10027834)
+-	writel(0x00005005, 0x10027838)
+-	writel(0x15555555, 0x1002783C)
+-	writel(0x00000004, 0xD8001010)
+-	writel(0x006ac73a, 0xD8001004)
+-	writel(0x92100000, 0xD8001000)
+-	writel(0x00000000, 0xA0000F00)
+-	writel(0xA2100000, 0xD8001000)
+-	writel(0x00000000, 0xA0000F00)
+-	writel(0x00000000, 0xA0000F00)
+-	writel(0x00000000, 0xA0000F00)
+-	writel(0x00000000, 0xA0000F00)
+-	writel(0xA2200000, 0xD8001000)
+-	writel(0x00000000, 0xA0000F00)
+-	writel(0x00000000, 0xA0000F00)
+-	writel(0x00000000, 0xA0000F00)
+-	writel(0x00000000, 0xA0000F00)
+-	writel(0xb2100000, 0xD8001000)
++	writel(0xD8001010, 0x00000008)
++	writel(0x10027828, 0x55555555)
++	writel(0x10027830, 0x55555555)
++	writel(0x10027834, 0x55555555)
++	writel(0x10027838, 0x00005005)
++	writel(0x1002783C, 0x15555555)
++	writel(0xD8001010, 0x00000004)
++	writel(0xD8001004, 0x006ac73a)
++	writel(0xD8001000, 0x92100000)
++	writel(0xA0000F00, 0x00000000)
++	writel(0xD8001000, 0xA2100000)
++	writel(0xA0000F00, 0x00000000)
++	writel(0xA0000F00, 0x00000000)
++	writel(0xA0000F00, 0x00000000)
++	writel(0xA0000F00, 0x00000000)
++	writel(0xD8001000, 0xA2200000)
++	writel(0xA0000F00, 0x00000000)
++	writel(0xA0000F00, 0x00000000)
++	writel(0xA0000F00, 0x00000000)
++	writel(0xA0000F00, 0x00000000)
++	writel(0xD8001000, 0xb2100000)
+ 	ldr		r0, =0xA0000033
+ 	mov		r1, #0xda
+ 	strb		r1, [r0]
+ 	ldr		r0, =0xA1000000
+ 	mov		r1, #0xff
+ 	strb		r1, [r0]
+-	writel(0x82226080, 0xD8001000)
++	writel(0xD8001000, 0x82226080)
+ .endm
+ 
+ .macro sdram_init_mx27_manual
+@@ -87,31 +180,31 @@ NORMAL_MODE		.long 0x00000000 // system/
+ 
+ .macro sdram_init_uboot
+ 	/* configure 16 bit nor flash on cs0 */
+-	writel(0x0000CC03, 0xd8002000)
+-	writel(0xa0330D01, 0xd8002004)
+-	writel(0x00220800, 0xd8002008)
++	writel(0xd8002000, 0x0000CC03)
++	writel(0xd8002004, 0xa0330D01)
++	writel(0xd8002008, 0x00220800)
+ 
+ 	/* ddr on csd0 - initial reset */
+-	writel(0x00000008, 0xD8001010)
++	writel(0xD8001010, 0x00000008)
+ 
+ 	/* configure ddr on csd0 - wait 5000 cycles */
+-	writel(0x00000004, 0xD8001010)
+-	writel(0x006ac73a, 0xD8001004)
+-	writel(0x92100000, 0xD8001000)
+-	writel(0x12344321, 0xA0000f00)
+-	writel(0xa2100000, 0xD8001000)
+-	writel(0x12344321, 0xA0000000)
+-	writel(0x12344321, 0xA0000000)
+-	writel(0xb2100000, 0xD8001000)
++	writel(0xD8001010, 0x00000004)
++	writel(0xD8001004, 0x006ac73a)
++	writel(0xD8001000, 0x92100000)
++	writel(0xA0000f00, 0x12344321)
++	writel(0xD8001000, 0xa2100000)
++	writel(0xA0000000, 0x12344321)
++	writel(0xA0000000, 0x12344321)
++	writel(0xD8001000, 0xb2100000)
+ 	ldr		r0, =0xA0000033
+ 	mov		r1, #0xda
+ 	strb		r1, [r0]
+ 	ldr		r0, =0xA1000000
+ 	mov		r1, #0xff
+ 	strb		r1, [r0]
+-	writel(0x82226080, 0xD8001000)
+-	writel(0xDEADBEEF, 0xA0000000)
+-	writel(0x0000000c, 0xD8001010)
++	writel(0xD8001000, 0x82226080)
++	writel(0xA0000000, 0xDEADBEEF)
++	writel(0xD8001010, 0x0000000c)
+ .endm
+ 
+ .globl board_init_lowlevel
+@@ -122,10 +215,10 @@ lowlevel_init:
+ 	mov	r10, lr
+ 
+ 	/* ahb lite ip interface */
+-	writel(0x20040304, AIPI1_PSR0)
+-	writel(0xDFFBFCFB, AIPI1_PSR1)
+-	writel(0x00000000, AIPI2_PSR0)
+-	writel(0xFFFFFFFF, AIPI2_PSR1)
++	writel(AIPI1_PSR0, 0x20040304)
++	writel(AIPI1_PSR1, 0xDFFBFCFB)
++	writel(AIPI2_PSR0, 0x00000000)
++	writel(AIPI2_PSR1, 0xFFFFFFFF)
+ 
+ 	/* disable mpll/spll */
+ 	ldr r0, =CSCR
+@@ -140,15 +233,15 @@ lowlevel_init:
+ 	 *        with 1.2 V core voltage! Find out if this is
+ 	 *        documented somewhere.
+ 	 */
+-	writel(0x04331C23, MPCTL0)	/* MPLL = 199.5*2 MHz               */
+-	writel(0x040C2403, SPCTL0)	/* SPLL = FIXME (needs review)      */
++	writel(MPCTL0, 0x04331C23)	/* MPLL = 199.5*2 MHz               */
++	writel(SPCTL0, 0x040C2403)	/* SPLL = FIXME (needs review)      */
+ 
+ 	/*
+ 	 * ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
+ 	 * AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
+ 	 * System clock (HCLK) = 133 MHz
+ 	 */
+-	writel(0x33f38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
++	writel(CSCR, 0x33f38107 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
+ 
+ 	/* add some delay here */
+ 	mov r1, #0x1000
+@@ -156,17 +249,21 @@ lowlevel_init:
+ 	bne 1b
+ 
+ 	/* clock gating enable */
+-	writel(0x00050f08, GPCR)
++	writel(GPCR, 0x00050f08)
+ 
+ 	/* peripheral clock divider */
+-	writel(0x130410c3, PCDR0)	/* FIXME                            */
+-	writel(0x09030908, PCDR1)	/* PERDIV1=08 @133 MHz              */
++	writel(PCDR0, 0x130410c3)	/* FIXME                            */
++	writel(PCDR1, 0x09030908)	/* PERDIV1=08 @133 MHz              */
+ 					/* PERDIV1=04 @266 MHz              */
+ 
+ 	/* configure 16 bit nor flash on cs0 */
+-	writel(0x0000CC03, 0xD8002000)
+-	writel(0xa0330D01, 0xD8002004)
+-	writel(0x00220800, 0xD8002008)
++	writel(0xD8002000, 0x0000CC03)
++	writel(0xD8002004, 0xa0330D01)
++	writel(0xD8002008, 0x00220800)
++
++
++    //port_init_sha
++    writel(DR(PORTA), 0x00000000)	/* init debug port */
+ 
+ 	/* skip sdram initialization if we run from ram */
+ 	cmp	pc, #0xa0000000
+@@ -177,6 +274,5 @@ lowlevel_init:
+ 	mov	pc,r10
+ 1:
+ 	sdram_init_sha
+-
+ 	mov	pc,r10
+ 
+--- u-boot-1.3.2/common/cmd_nand.c	2008-03-09 16:20:02.000000000 +0100
++++ u-boot-new/common/cmd_nand.c	2008-06-24 21:21:14.000000000 +0200
+@@ -179,6 +179,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag,
+ 
+ 	if (strcmp(cmd, "info") == 0) {
+ 
++        nand_init();		/* go init the NAND */
++
+ 		putc('\n');
+ 		for (i = 0; i < CFG_MAX_NAND_DEVICE; i++) {
+ 			if (nand_info[i].name)
+@@ -327,6 +329,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag,
+ 		    (!strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i"))) {
+ 			if (read) {
+ 				/* read */
++                printf("nand read opt\n");
++                udelay(10000);
+ 				nand_read_options_t opts;
+ 				memset(&opts, 0, sizeof(opts));
+ 				opts.buffer	= (u_char*) addr;
+@@ -336,6 +340,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag,
+ 				ret = nand_read_opts(nand, &opts);
+ 			} else {
+ 				/* write */
++                printf("nand write opt\n");
++                udelay(10000);
+ 				nand_write_options_t opts;
+ 				memset(&opts, 0, sizeof(opts));
+ 				opts.buffer	= (u_char*) addr;
+@@ -349,17 +355,27 @@ int do_nand(cmd_tbl_t * cmdtp, int flag,
+ 			}
+ 		} else if (s != NULL && !strcmp(s, ".oob")) {
+ 			/* read out-of-band data */
+-			if (read)
++			if (read){
++                printf("nand read out-of-band data\n");
++                udelay(10000);
+ 				ret = nand->read_oob(nand, off, size, (size_t *) &size,
+ 						     (u_char *) addr);
+-			else
++            }
++			else{
++                printf("nand write out-of-band data\n");
++                udelay(10000);
+ 				ret = nand->write_oob(nand, off, size, (size_t *) &size,
+ 						      (u_char *) addr);
++            }
+ 		} else {
+-			if (read)
++			if (read){
+ 				ret = nand_read(nand, off, &size, (u_char *)addr);
+-			else
+-				ret = nand_write(nand, off, &size, (u_char *)addr);
++            }
++			else{
++                 printf("nand write\n");
++                udelay(10000);
++				ret = nand_write(nand, off, &size, (u_char *)addr); 
++            }
+ 		}
+ 
+ 		printf(" %d bytes %s: %s\n", size,
+--- u-boot-1.3.2/cpu/arm926ejs/imx27/interrupt.c	2008-06-25 04:12:35.000000000 +0200
++++ u-boot-new/cpu/arm926ejs/imx27/interrupt.c	2008-06-24 03:04:14.000000000 +0200
+@@ -100,6 +100,11 @@ void set_timer (ulong t)
+ {
+ }
+ 
++void reset_timer(void)
++{
++	reset_timer_masked();
++}
++
+ /*
+  * This function is derived from PowerPC code (read timebase as long long).
+  * On ARM it just returns the timer value.
+--- u-boot-1.3.2/cpu/arm926ejs/imx27/Makefile	2008-06-25 04:12:35.000000000 +0200
++++ u-boot-new/cpu/arm926ejs/imx27/Makefile	2008-06-23 20:04:37.000000000 +0200
+@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
+ 
+ LIB	= $(obj)lib$(SOC).a
+ 
+-COBJS	= interrupt.o serial.o generic.o fec132.o fec_imx27.o miiphy.o
++COBJS	= interrupt.o serial.o generic.o fec132.o fec_imx27.o miiphy.o nand.o
+ 
+ SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+ OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+--- u-boot-1.3.2/cpu/arm926ejs/imx27/nand.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-new/cpu/arm926ejs/imx27/nand.c	2008-06-24 22:58:01.000000000 +0200
+@@ -0,0 +1,975 @@
++/*
++ * (C) Copyright 2008 (nc) Armadeus Systems
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
++
++#include <asm/errno.h>
++#include <nand.h>
++#include <asm/arch/imx-regs.h>
++
++#ifdef CFG_NFC_DEBUG
++# define NFC_DEBUG1(fmt, args...) printf(fmt, ##args)
++#else
++# define NFC_DEBUG1(fmt, args...)
++#endif
++
++#ifdef CONFIG_MTD_NAND_MXC_SWECC
++static int hardware_ecc = 0;
++#else
++static int hardware_ecc = 1;
++#endif
++
++/*struct nand_info {
++	bool bSpareOnly;
++	bool bStatusRequest;
++	u16 colAddr;
++    int is2k_Pagesize;
++};*/
++
++static u8 g_bSpareOnly;
++static u8 g_bStatusRequest;
++static u16 g_colAddr;
++static u8 is2k_Pagesize;
++
++ /* Macros to get byte and bit positions of ECC
++ */
++#define COLPOS(x)  ((x) >> 3)
++#define BITPOS(x) ((x)& 0xf)
++
++
++#define TROP_US_DELAY   10000
++
++#define MIN(x, y)		((x < y) ? x : y)
++
++/*
++ * OOB placement block for use with hardware ecc generation
++ */
++static struct nand_oobinfo nand_hw_eccoob_8 = {
++	.useecc = MTD_NANDECC_AUTOPLACE,
++	.eccbytes = 5,
++	.eccpos = {6, 7, 8, 9, 10},
++	.oobfree = {{2, 3}, {11, 5}}
++};
++
++static struct nand_oobinfo nand_hw_eccoob_16 = {
++	.useecc = MTD_NANDECC_AUTOPLACE,
++	.eccbytes = 5,
++	.eccpos = {6, 7, 8, 9, 10},
++	.oobfree = {{0, 6}, {12, 4}}
++};
++
++
++/* These really don't belong here, as they are specific to the NAND Model */
++static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
++
++static struct nand_bbt_descr delta_bbt_descr = {
++	.options = 0,
++	.offs = 0,
++	.len = 2,
++	.pattern = scan_ff_pattern
++};
++
++
++#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++static int Ecc_disabled;
++#endif
++
++//static struct nand_info g_nandfc_info;
++
++/*
++ * not required for iMX27 NFC
++ */
++static void nfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
++{
++	return;
++}
++
++/*!
++ * This functions is used by upper layer to checks if device is ready
++ *
++ * @param       mtd     MTD structure for the NAND Flash
++ *
++ * @return  0 if device is busy else 1
++ */
++static int nfc_dev_ready(struct mtd_info *mtd)
++{
++	/* 
++	 * NFC handles R/B internally.Therefore,this function
++	 * always returns status as ready.
++	 */
++	return 1;
++}
++
++static void wait_op_done(int maxRetries, u16 param)
++{
++	while (maxRetries-- > 0) {
++		if (NFC_CONFIG2 & NFC_CONFIG2_INT) {
++			NFC_CONFIG2 &= ~NFC_CONFIG2_INT;
++			break;
++		}
++		udelay(1);
++	}
++	if (maxRetries <= 0)
++		printf("wait_op_done (%d): INT not set\n", param);
++}
++
++
++/*!
++ * This function issues the specified command to the NAND device and
++ * waits for completion.
++ *
++ * @param       cmd     command for NAND Flash
++ */
++static void send_cmd(u16 cmd)
++{
++	NFC_DEBUG1("send_cmd(0x%x)\n", cmd);
++
++	NFC_FLASH_CMD = (u16) cmd;
++	NFC_CONFIG2 = NFC_CONFIG2_FCMD;
++
++	/* Wait for operation to complete */
++	wait_op_done(TROP_US_DELAY, cmd);
++}
++
++/*!
++ * This function sends an address (or partial address) to the
++ * NAND device.  The address is used to select the source/destination for
++ * a NAND command.
++ *
++ * @param       addr    address to be written to NFC.
++  */
++static void send_addr(u16 addr)
++{
++	NFC_DEBUG1("send_addr(0x%x)\n", addr);
++
++	NFC_FLASH_ADDR = addr;
++	NFC_CONFIG2 = NFC_CONFIG2_FADD;
++
++	/* Wait for operation to complete */
++	wait_op_done(TROP_US_DELAY, addr);
++}
++
++/*!
++ * This function requests the NANDFC to initate the transfer
++ * of data currently in the NANDFC RAM buffer to the NAND device.
++ *
++ * @param	buf_id	      Specify Internal RAM Buffer number (0-3)	
++ * @param       bSpareOnly    set 1 if only the spare area is transferred
++ */
++static void send_prog_page(u8 buf_id, u8 bSpareOnly)
++{
++	NFC_DEBUG1("send_prog_page (%d)\n", bSpareOnly);
++
++	/* NANDFC buffer 0 is used for page read/write */
++
++	NFC_BUF_ADDR = buf_id;
++
++	/* Configure spare or page+spare access */
++	if (!is2k_Pagesize) {
++		if (bSpareOnly) {
++			NFC_CONFIG1 |= NFC_CONFIG1_SP_EN;
++		} else {
++			NFC_CONFIG1 &= ~(NFC_CONFIG1_SP_EN);
++		}
++	}
++	NFC_CONFIG2 = NFC_CONFIG2_FDI;
++
++	/* Wait for operation to complete */
++	wait_op_done(TROP_US_DELAY, bSpareOnly);
++}
++
++/*!
++ * This function will correct the single bit ECC error
++ *
++ * @param  buf_id	Specify Internal RAM Buffer number (0-3)	
++ * @param  eccpos 	Ecc byte and bit position
++ * @param  bSpareOnly  	set to 1 if only spare area needs correction
++ */
++
++static void nfc_correct_error(u8 buf_id, u16 eccpos, u8 bSpareOnly)
++{
++	u16 col;
++	u8 pos;
++	volatile u16 *buf;
++
++	/* Get col & bit position of error
++	   these macros works for both 8 & 16 bits */
++	col = COLPOS(eccpos);	/* Get half-word position */
++	pos = BITPOS(eccpos);	/* Get bit position */
++
++	NFC_DEBUG1("nfc_correct_error (col=%d pos=%d)\n", col, pos);
++	/* Set the pointer for main / spare area */
++	if (!bSpareOnly) {
++		buf = (volatile u16 *)((ulong) (IMX_NFC_MAIN_AREA0 + (col >> 1) + (512 * buf_id)));
++	} else {
++		buf = (volatile u16 *)((ulong) (IMX_NFC_SPARE_AREA0 + (col >> 1) + (16 * buf_id)));
++	}
++
++	/* Fix the data */
++	*buf ^= (1 << pos);
++}
++
++
++/*!
++ * This function will maintains state of single bit Error
++ * in Main & spare  area
++ *
++ * @param buf_id	Specify Internal RAM Buffer number (0-3)	
++ * @param spare  	set to true if only spare area needs correction
++ */
++static void nfc_correct_ecc(u8 buf_id, u8 spare)
++{
++#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++	static int lastErrMain = 0, lastErrSpare = 0;	/* To maintain single bit
++							   error in previous page */
++#endif
++	u16 value, ecc_status;
++	/* Read the ECC result */
++	ecc_status = NFC_ECC_STATUS_RESULT;
++
++#ifdef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++	/* Check for Error in Mainarea */
++	if ((ecc_status >> NFC_ECC_STAT_ERM_SHFT) == NFC_ECC_STAT_ERROR1) {
++		/* Check for error in previous page */
++		if (lastErrMain && !spare) {
++			value = NFC_ECC_RSLT_MAIN_AREA;
++			/* Correct single bit error in Mainarea
++			   NFC will not correct the error in
++			   current page */
++			nfc_correct_error(buf_id, value, 0);
++		} else {
++			/* Set if single bit error in current page */
++			lastErrMain = 1;
++		}
++	} else {
++		/* Reset if no single bit error in current page */
++		lastErrMain = 0;
++	}
++
++	/* Check for Error in Sparearea */
++	if ((ecc_status & NFC_ECC_STAT_ERS_MASK) == NFC_ECC_STAT_ERROR1) {
++		/* Check for error in previous page */
++		if (lastErrSpare) {
++			value = NFC_ECC_RSLT_SPARE_AREA;
++			/* Correct single bit error in Mainarea
++			   NFC will not correct the error in
++			   current page */&
++			nfc_correct_error(buf_id, value, 1);
++		} else {
++			/* Set if single bit error in current page */
++			lastErrSpare = 1;
++		}
++	} else {
++		/* Reset if no single bit error in current page */
++		lastErrSpare = 0;
++	}
++#else
++	if (((ecc_status >> NFC_ECC_STAT_ERM_SHFT) == NFC_ECC_STAT_ERROR1)
++	    || ((ecc_status & NFC_ECC_STAT_ERS_MASK) == NFC_ECC_STAT_ERROR1)) {
++		if (Ecc_disabled) {
++			if ((ecc_status >> NFC_ECC_STAT_ERM_SHFT) == NFC_ECC_STAT_ERROR1) {
++				value = NFC_ECC_RSLT_MAIN_AREA;
++				/* Correct single bit error in Mainarea
++				   NFC will not correct the error in
++				   current page */
++				nfc_correct_error(buf_id, value, 0);
++			}
++			if ((ecc_status & NFC_ECC_STAT_ERS_MASK) == NFC_ECC_STAT_ERROR1) {
++				value = NFC_ECC_RSLT_SPARE_AREA;
++				/* Correct single bit error in Mainarea
++				   NFC will not correct the error in
++				   current page */
++				nfc_correct_error(buf_id, value, 1);
++			}
++
++		} else {
++			/* Disable ECC  */
++			NFC_CONFIG1 &= ~(NFC_CONFIG1_ECC_EN);
++			Ecc_disabled = 1;
++		}
++	} else if (ecc_status == 0) {
++		if (Ecc_disabled) {
++			/* Enable ECC */
++			NFC_CONFIG1 |= NFC_CONFIG1_ECC_EN;
++			Ecc_disabled = 0;
++		}
++	} else {
++		/* 2-bit Error  Do nothing */
++	}
++#endif				/* CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2 */
++
++}
++
++
++
++/*!
++ * This function requests the NANDFC to initated the transfer
++ * of data from the NAND device into in the NANDFC ram buffer.
++ *
++ * @param  	buf_id		Specify Internal RAM Buffer number (0-3)	
++ * @param       bSpareOnly    	set 1 if only the spare area is transferred
++ */
++static void send_read_page(u8 buf_id, u8 bSpareOnly)
++{
++	NFC_DEBUG1("send_read_page (%d)\n", bSpareOnly);
++
++	/* NANDFC buffer 0 is used for page read/write */
++	NFC_BUF_ADDR = buf_id;
++
++	/* Configure spare or page+spare access */
++	if (!is2k_Pagesize) {
++		if (bSpareOnly) {
++			NFC_CONFIG1 |= NFC_CONFIG1_SP_EN;
++		} else {
++			NFC_CONFIG1 &= ~(NFC_CONFIG1_SP_EN);
++		}
++	}
++
++	NFC_CONFIG2 = NFC_CONFIG2_FDO_PAGE;
++
++	/* Wait for operation to complete */
++	wait_op_done(TROP_US_DELAY, bSpareOnly);
++
++	/* If there are single bit errors in
++	   two consecutive page reads then
++	   the error is not  corrected by the
++	   NFC for the second page.
++	   Correct single bit error in driver */
++
++	nfc_correct_ecc(buf_id, bSpareOnly);
++}
++
++/*!
++ * This function requests the NANDFC to perform a read of the
++ * NAND device ID.
++ */
++static void send_read_id(struct mtd_info *mtd)
++{
++ 	struct nand_chip *this =  mtd->priv;
++
++    NFC_DEBUG1("send_read_id \n");
++	/* NANDFC buffer 0 is used for device ID output */
++	NFC_BUF_ADDR = 0x0;
++
++	/* Read ID into main buffer */
++	NFC_CONFIG1 &= (~(NFC_CONFIG1_SP_EN));
++	NFC_CONFIG2 = NFC_CONFIG2_FDO_ID;
++
++	/* Wait for operation to complete */
++	wait_op_done(TROP_US_DELAY, 0);
++
++	if (this->options & NAND_BUSWIDTH_16) {
++		volatile u16 *mainBuf = (volatile u16 *)((ulong) (IMX_NFC_MAIN_AREA0));
++
++		/*
++		 * Pack the every-other-byte result for 16-bit ID reads
++		 * into every-byte as the generic code expects and various
++		 * chips implement.
++		 */
++
++		mainBuf[0] = (mainBuf[0] & 0xff) | ((mainBuf[1] & 0xff) << 8);
++		mainBuf[1] = (mainBuf[2] & 0xff) | ((mainBuf[3] & 0xff) << 8);
++		mainBuf[2] = (mainBuf[4] & 0xff) | ((mainBuf[5] & 0xff) << 8);
++	}
++}
++
++
++
++/*!
++ * This function writes data of length \b len to buffer \b buf. The data to be
++ * written on NAND Flash is first copied to RAMbuffer. After the Data Input
++ * Operation by the NFC, the data is written to NAND Flash
++ *
++ * @param       mtd     MTD structure for the NAND Flash
++ * @param       buf     data to be written to NAND Flash
++ * @param       len     number of bytes to be written
++ */
++static void nfc_write_buf(struct mtd_info *mtd,
++			       const u_char * buf, int len)
++{
++	int i = 0;
++    ulong p;
++    int nbbytes_main = 0, nbbytes_spare=0;
++    int bytes_multi = 0;
++
++    if (!g_bSpareOnly)
++    {
++        /* Main Area */
++        nbbytes_main = mtd->oobblock - g_colAddr;
++        if( nbbytes_main > 0 )
++        {
++            nbbytes_main = min(len, nbbytes_main);
++            bytes_multi =  nbbytes_main & 0xFFFFFFFE;
++            p = (ulong)(IMX_NFC_MAIN_AREA0)+g_colAddr;
++            for( i=0; i<bytes_multi; i+=2 ){
++        			*((volatile u16*)(p + i)) = *((u16*) &buf[i]);
++             }
++            if( nbbytes_main & 1 ){
++                *((volatile u16*)(p + i +1)) = buf[i];
++                i++;
++            }
++        }
++    }
++	if (g_bSpareOnly && g_colAddr < mtd->oobblock )
++		g_colAddr += mtd->oobblock;
++    
++     /* Spare Area */
++    nbbytes_spare = len - nbbytes_main;
++    if( nbbytes_spare )
++    {
++        nbbytes_spare = min(mtd->oobsize - g_colAddr+mtd->oobblock, nbbytes_spare);
++        bytes_multi =  nbbytes_spare & 0xFFFFFFFE;
++        p = (volatile u16*)((ulong) (IMX_NFC_SPARE_AREA0));
++        for( i=0; i<bytes_multi; i+=2 ){
++        		*((volatile u16*)(p + i)) = *((u16*) &buf[nbbytes_main+i]);
++        }
++        if( nbbytes_spare & 1 )
++             *((volatile u16*)(p + i +1)) = buf[nbbytes_main+i+1];
++    }
++    g_colAddr += nbbytes_main + nbbytes_spare;
++}
++
++/*
++ * These functions are quite problematic for the NFC. Luckily they are
++ * not used in the current nand code, except for nand_command, which
++ * we've defined our own anyway. 
++ */
++static void nfc_write_word(struct mtd_info *mtd, u16 word)
++{
++	printf("nfc_write_word: WARNING, this function does not work with the iMX27 NFC!\n");
++}
++static void nfc_write_byte(struct mtd_info *mtd, u_char byte)
++{
++	printf("nfc_write_byte: WARNING, this function does not work with the iMX27 NFC!\n");
++}
++
++
++/*!
++ * This function id is used to read the data buffer from the NAND Flash. To
++ * read the data from NAND Flash first the data output cycle is initiated by
++ * the NFC, which copies the data to RAMbuffer. This data of length \b len is
++ * then copied to buffer \b buf.
++ *
++ * @param       mtd     MTD structure for the NAND Flash
++ * @param       buf     data to be read from NAND Flash
++ * @param       len     number of bytes to be read
++ */
++static void nfc_read_buf(struct mtd_info *mtd, u_char * buf, int len)
++{
++	int i = 0;
++    ulong p;
++    int nbbytes_main = 0, nbbytes_spare=0;
++    int bytes_multi = 0;
++
++    if (!g_bSpareOnly)
++    {
++        /* Main Area */
++        nbbytes_main = mtd->oobblock - g_colAddr;
++        if( nbbytes_main > 0 )
++        {
++            nbbytes_main = min(len, nbbytes_main);
++            bytes_multi =  nbbytes_main & 0xFFFFFFFE;
++            p = (ulong)(IMX_NFC_MAIN_AREA0)+g_colAddr;
++            for( i=0; i<bytes_multi; i+=2 ){
++        			*((u16*) &buf[i]) = *((volatile u16*)(p + i));
++             }
++            if( nbbytes_main & 1 )
++                buf[i++] = *((volatile u16*)(p + i +1));
++        }
++    }
++	if (g_bSpareOnly && g_colAddr < mtd->oobblock )
++		g_colAddr += mtd->oobblock;
++    
++     /* Spare Area */
++    nbbytes_spare = len - nbbytes_main;
++    if( nbbytes_spare )
++    {
++        nbbytes_spare = min(mtd->oobsize - g_colAddr+mtd->oobblock, nbbytes_spare);
++        bytes_multi =  nbbytes_spare & 0xFFFFFFFE;
++        p = (volatile u16*)((ulong) (IMX_NFC_SPARE_AREA0));
++        for( i=0; i<bytes_multi; i+=2 ){
++        		*((u16*) &buf[nbbytes_main+i]) = *((volatile u16*)(p + i));
++        }
++        if( nbbytes_spare & 1 )
++            buf[nbbytes_main+i+1] = *((volatile u16*)(p + i +1));
++    }
++    g_colAddr += nbbytes_main + nbbytes_spare;
++}
++
++/*
++ * read a word. Not implemented as not used in NAND code.
++ */
++static u16 nfc_read_word(struct mtd_info *mtd)
++{
++	printf("nfc_read_word: UNIMPLEMENTED.\n");
++	return 0;
++}
++
++static u16 get_dev_status(void)
++{
++	volatile u16 *mainBuf = (volatile u32 *)((ulong) (IMX_NFC_MAIN_AREA1));
++	u32 store;
++	u16 ret;
++	/* Issue status request to NAND device */
++
++	/* store the main area1 first word, later do recovery */
++	store = *((u32 *) mainBuf);
++	/*
++	 * NANDFC buffer 1 is used for device status to prevent
++	 * corruption of read/write buffer on status requests.
++	 */
++	NFC_BUF_ADDR = 1;
++
++	/* Send the Read status command before reading status */
++	send_cmd(NAND_CMD_STATUS);
++
++	/* Read status into main buffer */
++	NFC_CONFIG1 &= (~(NFC_CONFIG1_SP_EN));
++	NFC_CONFIG2 = NFC_CONFIG2_FDO_STATUS;
++
++	/* Wait for operation to complete */
++	wait_op_done(TROP_US_DELAY, 0);
++
++	/* get status, then recovery area 1 data */
++	ret = mainBuf[0];
++    printf("get_dev_status %x\n", ret);
++	*((u32 *) mainBuf) = store;
++
++	/* Status is placed in first word of main buffer */
++	return ret;
++}
++
++
++/*!
++ * This function reads byte from the NAND Flash
++ *
++ * @param       mtd     MTD structure for the NAND Flash
++ *
++ * @return    data read from the NAND Flash
++ */
++static u_char nfc_read_byte(struct mtd_info *mtd)
++{
++	u_char retVal = 0;
++	u16 col, rdWord;
++	volatile u16 *mainBuf = (volatile u16 *)((ulong) (IMX_NFC_MAIN_AREA0));
++	volatile u16 *spareBuf = (volatile u16 *)((ulong) (IMX_NFC_SPARE_AREA0));
++
++	/* Check for status request */
++	if (g_bStatusRequest) {
++		return (get_dev_status() & 0xFF);
++	}
++
++	/* Get column for 16-bit access */
++	col = g_colAddr >> 1;
++
++	/* If we are accessing the spare region */
++	if (g_bSpareOnly) {
++		rdWord = spareBuf[col];
++	} else {
++		rdWord = mainBuf[col];
++	}
++
++	/* Pick upper/lower byte of word from RAM buffer */
++	if (g_colAddr & 0x1) {
++		retVal = (rdWord >> 8) & 0xFF;
++	} else {
++		retVal = rdWord & 0xFF;
++	}
++    NFC_DEBUG1("\treval: %x, rdWord:%x \n",retVal, rdWord);
++
++	/* Update saved column address */
++	g_colAddr++;
++
++	return retVal;
++}
++
++/* this function is called after Programm and Erase Operations to
++ * check for success or failure */
++static int nfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
++{
++    wait_op_done(TROP_US_DELAY, 9);
++	return 0;
++}
++
++static int nfc_correct_data(struct mtd_info *mtd, u_char * dat,
++				 u_char * read_ecc, u_char * calc_ecc)
++{
++	/*
++	 * 1-Bit errors are automatically corrected in HW.  No need for
++	 * additional correction.  2-Bit errors cannot be corrected by
++	 * HW ECC, so we need to return failure
++	 */
++	u16 ecc_status = NFC_ECC_STATUS_RESULT;
++
++	if (((ecc_status & NFC_ECC_STAT_ERS_MASK) == NFC_ECC_STAT_ERROR2) || 
++        ((ecc_status >> NFC_ECC_STAT_ERM_SHFT) == NFC_ECC_STAT_ERROR2)) {
++		return -1;
++	}
++
++	return 0;
++}
++
++
++/*!
++ * This function is used by the upper layer to write command to NAND Flash for
++ * different operations to be carried out on NAND Flash
++ *
++ * @param       mtd             MTD structure for the NAND Flash
++ * @param       command         command for NAND Flash
++ * @param       column          column offset for the page read
++ * @param       page_addr       page to be read from NAND Flash
++ */
++static void nfc_cmdfunc(struct mtd_info *mtd, unsigned command,
++			int column, int page_addr)
++{
++	NFC_DEBUG1("nfc_cmdfunc (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
++	      command, column, page_addr);
++
++	if ((FMCR & FMCR_NF_FMS) == FMCR_NF_FMS)
++		is2k_Pagesize = 1;
++
++	/*
++	 * Reset command state information
++	 */
++	g_bStatusRequest = 0;
++
++	/*
++	 * Command pre-processing step
++	 */
++	switch (command) {
++
++	case NAND_CMD_STATUS:
++		g_colAddr = 0;
++		g_bStatusRequest = 1;
++		break;
++
++	case NAND_CMD_READ0:
++		g_colAddr = column;
++		g_bSpareOnly = 0;
++		break;
++
++	case NAND_CMD_READOOB:
++		g_colAddr = column;
++		g_bSpareOnly = 1;
++		if (is2k_Pagesize)
++			command = NAND_CMD_READ0;	/* only READ0 is valid */
++		break;
++
++	case NAND_CMD_SEQIN:
++		if (column >= mtd->oobblock) {
++			if (is2k_Pagesize) {
++				/** 			 
++				  * FIXME: before send SEQIN command for write OOB,
++				  * We must read one page out. 			 
++				  * For K9F1GXX has no READ1 command to set current HW 			 
++				  * pointer to spare area, we must write the whole page including OOB together.			 
++				  */
++				/* call itself to read a page */
++				nfc_cmdfunc(mtd, NAND_CMD_READ0, 0,
++						 page_addr);
++			}
++			g_colAddr = column - mtd->oobblock;
++			g_bSpareOnly = 1;
++			/* Set program pointer to spare region */
++			if (!is2k_Pagesize)
++				send_cmd(NAND_CMD_READOOB);
++		} else {
++			g_bSpareOnly = 0;
++			g_colAddr = column;
++			/* Set program pointer to page start */
++			if (!is2k_Pagesize)
++				send_cmd(NAND_CMD_READ0);
++		}
++		break;
++
++	case NAND_CMD_PAGEPROG:
++#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++		if (Ecc_disabled) {
++			/* Enable Ecc for page writes */
++			NFC_CONFIG1 |= NFC_CONFIG1_ECC_EN;
++		}
++#endif
++
++		send_prog_page(0, g_bSpareOnly);
++
++		if (is2k_Pagesize) {
++			/* data in 4 areas datas */
++			send_prog_page(1, g_bSpareOnly);
++			send_prog_page(2, g_bSpareOnly);
++			send_prog_page(3, g_bSpareOnly);
++		}
++
++		break;
++
++   	case NAND_CMD_ERASE1:break;
++    default: break;
++	}
++
++	/*
++	 * Write out the command to the device.
++	 */
++	send_cmd(command);
++
++	/*
++	 * Write out column address, if necessary
++	 */
++	if (column != -1) {
++		/*
++		 * MXC NANDFC can only perform full page+spare or
++		 * spare-only read/write.  When the upper layers
++		 * layers perform a read/write buf operation,
++		 * we will used the saved column adress to index into
++		 * the full page.
++		 */
++		send_addr(0);
++		if (is2k_Pagesize)
++			send_addr(0);	/* another col addr cycle for 2k page */
++	}
++
++	/*
++	 * Write out page address, if necessary
++	 */
++	if (page_addr != -1) {
++		send_addr(page_addr & 0xff);	/* paddr_0 - p_addr_7 */
++
++		if (is2k_Pagesize) {
++			send_addr((page_addr >> 8) & 0xFF);
++			if (mtd->size >= 0x42000000) {
++				send_addr((page_addr >> 16) & 0xff);
++			}
++		} else {
++			/* One more address cycle for higher density devices */
++			if (mtd->size >= 0x4000000) {
++				send_addr((page_addr >> 8) & 0xff);	/* paddr_8 - paddr_15 */
++				send_addr((page_addr >> 16) & 0xff);
++			} else
++				send_addr((page_addr >> 8) & 0xff);	/* paddr_8 - paddr_15 */
++		}
++	}
++
++	/*
++	 * Command post-processing step
++	 */
++	switch (command) {
++
++	case NAND_CMD_RESET:
++		break;
++
++	case NAND_CMD_READOOB:
++	case NAND_CMD_READ0:
++		if (is2k_Pagesize) {
++			/* send read confirm command */
++			send_cmd(NAND_CMD_READSTART);
++			/* read for each AREA */
++			send_read_page(0, g_bSpareOnly);
++			send_read_page(1, g_bSpareOnly);
++			send_read_page(2, g_bSpareOnly);
++			send_read_page(3, g_bSpareOnly);
++		} else {
++			send_read_page(0, g_bSpareOnly);
++		}
++		break;
++
++	case NAND_CMD_READID:
++		send_read_id(mtd);
++		break;
++
++	case NAND_CMD_PAGEPROG:
++#ifndef CONFIG_MTD_NAND_MXC_ECC_CORRECTION_OPTION2
++		if (Ecc_disabled) {
++			/* Disble Ecc after page writes */
++			NFC_CONFIG1 &= ~(NFC_CONFIG1_ECC_EN);
++		}
++#endif
++		break;
++
++	case NAND_CMD_STATUS:
++		break;
++
++	case NAND_CMD_ERASE2:
++		break;
++	}
++}
++
++/*!
++ * This function is used by upper layer for select and deselect of the NAND
++ * chip
++ *
++ * @param       mtd     MTD structure for the NAND Flash
++ * @param       chip    val indicating select or deselect
++ */
++static void nfc_select_chip(struct mtd_info *mtd, int chip)
++{
++#ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
++	if (chip > 0) {
++		NFC_DEBUG1("ERROR:  Illegal chip select (chip = %d)\n", chip);
++		return;
++	}
++
++	if (chip == -1) {
++		NFC_CONFIG1 &= (~(NFC_CONFIG1_CEn));
++		return;
++	}
++
++	NFC_CONFIG1 |= NFC_CONFIG1_CEn;
++#endif
++    NFC_DEBUG1("nfc_select_chip: %d)\n", chip);
++	switch (chip) {
++	case -1:
++		/* Disable the NFC clock */
++        PCCR1 &= ~PCCR1_NFC_BAUDEN;
++		break;
++	case 0:
++		/* Enable the NFC clock */
++        PCCR1 |= PCCR1_NFC_BAUDEN;
++		break;
++
++	default:
++		break;
++	}
++}
++
++
++static void nfc_enable_hwecc(struct mtd_info *mtd, int mode)
++{
++	/*
++	 * If HW ECC is enabled, we turn it on during init.  There is
++	 * no need to enable again here.
++	 */
++}
++
++static int nfc_calculate_ecc(struct mtd_info *mtd, const u_char * dat,
++				  u_char * ecc_code)
++{
++	/*
++	 * Just return success.  HW ECC does not read/write the NFC spare
++	 * buffer.  Only the FLASH spare area contains the calcuated ECC.
++	 */
++	return 0;
++}
++
++/*!
++ * This function is used by the upper layer to verify the data in NAND Flash
++ * with the data in the \b buf.
++ *
++ * @param       mtd     MTD structure for the NAND Flash
++ * @param       buf     data to be verified
++ * @param       len     length of the data to be verified
++ *
++ * @return      -EFAULT if error else 0
++ *
++ */
++static int nfc_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
++{
++	return -EFAULT;
++}
++
++
++
++/*
++ * Board-specific NAND initialization. The following members of the
++ * argument are board-specific (per include/linux/mtd/nand_new.h):
++ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
++ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
++ * - hwcontrol: hardwarespecific function for accesing control-lines
++ * - dev_ready: hardwarespecific function for  accesing device ready/busy line
++ * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
++ *   only be provided if a hardware ECC is available
++ * - eccmode: mode of ecc, see defines
++ * - chip_delay: chip dependent delay for transfering data from array to
++ *   read regs (tR)
++ * - options: various chip options. They can partly be set to inform
++ *   nand_scan about special functionality. See the defines for further
++ *   explanation
++ * Members with a "?" were not set in the merged testing-NAND branch,
++ * so they are not set here either.
++ */
++int board_nand_init(struct nand_chip *nand)
++{
++    g_colAddr = 0;
++
++    //memset((char *)&g_nandfc_info, 0, sizeof(g_nandfc_info));
++    //nand->priv = g_nandfc_info;
++
++	/* 50 us command delay time */
++	nand->chip_delay = 5;
++
++	nand->hwcontrol = nfc_hwcontrol;
++	//nand->options = NAND_BUSWIDTH_16;
++	nand->waitfunc = nfc_wait;    /////// tdb
++	nand->read_byte = nfc_read_byte;
++	nand->write_byte = nfc_write_byte;
++	nand->read_word = nfc_read_word;
++	nand->write_word = nfc_write_word;
++	nand->read_buf = nfc_read_buf;
++	nand->write_buf = nfc_write_buf;
++    nand->dev_ready =nfc_dev_ready;
++    nand->select_chip = nfc_select_chip;
++    nand->verify_buf = nfc_verify_buf;
++
++	nand->cmdfunc = nfc_cmdfunc;
++	nand->badblock_pattern = &delta_bbt_descr;
++
++	if (hardware_ecc) {
++		nand->calculate_ecc = nfc_calculate_ecc; //void
++		nand->enable_hwecc = nfc_enable_hwecc;  // void
++		nand->correct_data = nfc_correct_data;
++		nand->eccsize = 512;
++		nand->eccbytes = 3;
++    	nand->eccmode = NAND_ECC_HW3_512;
++		NFC_CONFIG1 |= NFC_CONFIG1_ECC_EN;
++	} else {
++		nand->eccmode = NAND_ECC_SOFT;
++	}
++
++	/* NAND bus width determines access funtions used by upper layer */
++	//if (flash->width == 2) {
++	//	nand->options |= NAND_BUSWIDTH_16 | NAND_USE_FLASH_BBT;
++	//	nand->autooob = &nand_hw_eccoob_16;
++	//} else {
++		nand->options |= 0;//NAND_USE_FLASH_BBT;
++        nand->autooob = &nand_hw_eccoob_8;
++	//}
++
++	/* preset operation */
++	/* Unlock the internal RAM Buffer */
++	NFC_CONFIG = NFC_CONFIG_UNLOCKED;
++
++	/* Blocks to be unlocked */
++	NFC_UNLOCKSTART_BLKADDR = 0x0;
++	NFC_UNLOCKEND_BLKADDR = 0x4000;
++
++	/* Unlock Block Command for given address range */
++	NFC_WRPROT = NFC_WRPROT_UNLOCKBLK;
++
++
++
++	is2k_Pagesize = 0;
++
++
++	return 0;
++}
++
++#endif
++
++
+--- u-boot-1.3.2/include/asm-arm/arch-imx27/imx-regs.h	2008-06-25 04:12:35.000000000 +0200
++++ u-boot-new/include/asm-arm/arch-imx27/imx-regs.h	2008-06-24 07:26:49.000000000 +0200
+@@ -62,8 +62,13 @@
+ #define IMX_PLL_BASE               (0x27000 + IMX_IO_BASE)
+ #define IMX_SYSTEM_CTL_BASE        (0x27800 + IMX_IO_BASE)
+ 
+-#define IMX_ESD_BASE               (0xd8001000)
+-#define IMX_WEIM_BASE              (0xd8002000)
++#define IMX_NFC_BASE               (0xD8000000)
++#define IMX_NFC_MAIN_AREA0         (0xD8000000)          
++#define IMX_NFC_MAIN_AREA1         (0xD8000200)  
++#define IMX_NFC_SPARE_AREA0        (0xD8000800)          
++#define IMX_ESD_BASE               (0xD8001000)
++#define IMX_WEIM_BASE              (0xD8002000)
++
+ 
+ /* AIPI */
+ #define AIPI1_PSR0	__REG(IMX_AIPI1_BASE + 0x00)
+@@ -72,7 +77,34 @@
+ #define AIPI2_PSR1	__REG(IMX_AIPI2_BASE + 0x04)
+ 
+ /* System Control */
++#define FMCR	__REG(IMX_SYSTEM_CTL_BASE + 0x14)
+ #define GPCR	__REG(IMX_SYSTEM_CTL_BASE + 0x18)
++#define WBCR	__REG(IMX_SYSTEM_CTL_BASE + 0x1C)
++#define DSCR1	__REG(IMX_SYSTEM_CTL_BASE + 0x20)
++#define DSCR2	__REG(IMX_SYSTEM_CTL_BASE + 0x24)
++#define DSCR3	__REG(IMX_SYSTEM_CTL_BASE + 0x28)
++#define DSCR4	__REG(IMX_SYSTEM_CTL_BASE + 0x2C)
++#define DSCR5	__REG(IMX_SYSTEM_CTL_BASE + 0x30)
++#define DSCR6	__REG(IMX_SYSTEM_CTL_BASE + 0x34)
++#define DSCR7	__REG(IMX_SYSTEM_CTL_BASE + 0x38)
++#define DSCR8	__REG(IMX_SYSTEM_CTL_BASE + 0x3C)
++#define DSCR9	__REG(IMX_SYSTEM_CTL_BASE + 0x40)
++#define DSCR10	__REG(IMX_SYSTEM_CTL_BASE + 0x44)
++#define DSCR11	__REG(IMX_SYSTEM_CTL_BASE + 0x48)
++#define DSCR12	__REG(IMX_SYSTEM_CTL_BASE + 0x4C)
++#define DSCR13	__REG(IMX_SYSTEM_CTL_BASE + 0x50)
++#define PSCR	__REG(IMX_SYSTEM_CTL_BASE + 0x54)
++#define PMCR	__REG(IMX_SYSTEM_CTL_BASE + 0x58)
++#define DCVR0	__REG(IMX_SYSTEM_CTL_BASE + 0x60)
++#define DCVR1	__REG(IMX_SYSTEM_CTL_BASE + 0x64)
++#define DCVR2	__REG(IMX_SYSTEM_CTL_BASE + 0x68)
++#define DCVR3	__REG(IMX_SYSTEM_CTL_BASE + 0x6C)
++
++/* System Control bit definition*/
++#define FMCR_NF_FMS         (1<<5)
++#define FMCR_NF_16BIT_SEL   (1<<4)	
++
++
+ 
+ /* Chip Select Registers */
+ #define CS0U __REG(IMX_WEIM_BASE + 0x00) /* Chip Select 0 Upper Register    */
+@@ -317,6 +349,13 @@
+  *  i.MX1 and i.MXL: 0 <= x <= 3
+  *  i.MX27         : 0 <= x <= 5
+  */
++#define PORTA 0
++#define PORTB 1
++#define PORTC 2
++#define PORTD 3
++#define PORTE 4
++#define PORTF 5
++
+ #define DDIR(x)    __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8)
+ #define OCR1(x)    __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8)
+ #define OCR2(x)    __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8)
+@@ -340,12 +379,12 @@
+ #define GPIO_PORT_SHIFT 5
+ #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+ 
+-#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
+-#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
+-#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
+-#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
+-#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
+-#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
++#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT)
++#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT)
++#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT)
++#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT)
++#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT)
++#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT)
+ 
+ #define GPIO_OUT   (1 << 8)
+ #define GPIO_IN    (0 << 8)
+@@ -398,4 +437,58 @@
+ #define I2SR_IIF 	(1<<1)		/* I2C interrupt */
+ #define I2SR_RXAK 	(1<<0)		/* I2C Received Acknowledge */
+ 
++/*
++ * NFC module
++ */
++#define NFC_BUFSIZE             __REG16(IMX_NFC_BASE + 0xE00) /* Internal SRAM Size */
++#define NFC_BLCK_ADD_LOCK       __REG16(IMX_NFC_BASE + 0xE02) /* NAND Flash Block
++                                                             Address for Lock Check */
++#define NFC_BUF_ADDR            __REG16(IMX_NFC_BASE + 0xE04) /* Buffer Number for Page Data Transfer To/
++                                                                From Flash Memory */
++#define NFC_FLASH_ADDR          __REG16(IMX_NFC_BASE + 0xE06) /* NAND Flash Address */
++#define NFC_FLASH_CMD           __REG16(IMX_NFC_BASE + 0xE08) /* NAND Flash Command */
++#define NFC_CONFIG              __REG16(IMX_NFC_BASE + 0xE0A) /* NFC Internal Buffer Lock Control */
++#define NFC_ECC_STATUS_RESULT   __REG16(IMX_NFC_BASE + 0xE0C) /* Controller Status/Result of Flash Operation */
++#define NFC_ECC_RSLT_MAIN_AREA  __REG16(IMX_NFC_BASE + 0xE0E) /* ECC Error Position of Main Area Data Error */
++#define NFC_ECC_RSLT_SPARE_AREA __REG16(IMX_NFC_BASE + 0xE10) /* ECC Error Position of Spare Area Data Error */
++#define NFC_WRPROT              __REG16(IMX_NFC_BASE + 0xE12) /* Nand Flash Write Protection */
++#define NFC_UNLOCKSTART_BLKADDR __REG16(IMX_NFC_BASE + 0xE14) /* Start Address for Write Protection Unlock */
++#define NFC_UNLOCKEND_BLKADDR   __REG16(IMX_NFC_BASE + 0xE16) /* End Address for Write Protection Unlock */
++#define NFC_WRPR_STAT           __REG16(IMX_NFC_BASE + 0xE18) /* Current Nand Flash Write Protection Status */
++#define NFC_CONFIG1             __REG16(IMX_NFC_BASE + 0xE1A) /* Nand Flash Operation Configuration 1 */
++#define NFC_CONFIG2             __REG16(IMX_NFC_BASE + 0xE1C) /* Nand Flash Operation Configuration 2 */
++
++/* NFC_ECC_STATUS_RESULT Status Register Bit Fields */
++#define NFC_ECC_STAT_ERM_SHFT 	(2)		    /* ERM shift */
++#define NFC_ECC_STAT_ERS_MASK 	(0x03)		/* ERS mask  */
++#define NFC_ECC_STAT_ERROR1 	(1<<0)		/* correctable error */
++#define NFC_ECC_STAT_ERROR2 	(1<<1)		/* non correctable error */
++
++/* NFC_CONFIG Control Register Bit Fields */
++#define NFC_CONFIG_UNLOCKED     (1<<1)		/* unlocked */
++#define NFC_CONFIG_LOCKED       (1<<0)		/* locked */
++/* NFC_WRPROT Control Register Bit Fields */
++#define NFC_WRPROT_UNLOCKBLK    (4<<0)		/* unlock block according to given address range */
++#define NFC_WRPROT_LOCKALL 	    (2<<0)		/* lock all */
++#define NFC_WRPROT_LOCKTIGHT    (1<<0)		/* lock-tight locked blocks */
++/* NFC_WRPR_STAT Status Register Bit Fields */
++#define NFC_WRPR_US 	(1<<2)		/* Unlocked status	*/
++#define NFC_WRPR_LS 	(1<<1)		/* Locked status */
++#define NFC_WRPR_LTS 	(1<<0)		/* Lock-tight Status */
++/* NFC_CONFIG1 Control Register Bit Fields */
++#define NFC_CONFIG1_CEn 	(1<<7)		/* Flash force CE */
++#define NFC_CONFIG1_RST 	(1<<6)		/* Reset */
++#define NFC_CONFIG1_BIG 	(1<<5)		/* Big Endian Mode */
++#define NFC_CONFIG1_INT_MSK (1<<4)		/* Mask Interrupt Bit	*/
++#define NFC_CONFIG1_ECC_EN 	(1<<3)		/* ECC operation enable */
++#define NFC_CONFIG1_SP_EN 	(1<<2)		/* Flash spare enable */
++/* NFC_CONFIG2 Control Register Bit Fields */
++#define NFC_CONFIG2_INT	        (1<<15)		/* Interrupt */
++#define NFC_CONFIG2_FDO_STATUS	(4<<3)		/* Flash status output */
++#define NFC_CONFIG2_FDO_ID	    (2<<3)		/* Flash ID output */
++#define NFC_CONFIG2_FDO_PAGE    (1<<3)		/* Flash data output */
++#define NFC_CONFIG2_FDI         (1<<2)		/* Flash data input	*/
++#define NFC_CONFIG2_FADD 	    (1<<1)		/* Flash address input */
++#define NFC_CONFIG2_FCMD 	    (1<<0)		/* Flash command input */
+ #endif				/* _IMX_REGS_H */
++
+--- u-boot-1.3.2/include/configs/pcm038.h	2008-06-25 04:12:35.000000000 +0200
++++ u-boot-new/include/configs/pcm038.h	2008-06-24 22:12:48.000000000 +0200
+@@ -78,7 +78,7 @@
+  * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
+  * functionality or size of u-boot code.
+  */
+-/*#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		\
++#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		\
+ 				| CFG_CMD_NET		\
+ 				| CFG_CMD_PING		\
+ 				| CFG_CMD_DHCP		\
+@@ -86,11 +86,12 @@
+ 				| CFG_CMD_I2C		\
+ 				| CFG_CMD_DATE		\
+ 				| CFG_CMD_EEPROM	\
++                | CFG_CMD_NAND      \
+ 				| CONFIG_CMD_ALL	\
+ 				)
+ 
+-#include <cmd_confdefs.h>
+-*/
++//#include <cmd_confdefs.h>
++
+ #include <config_cmd_default.h>
+ #define CONFIG_CMD_PING
+ #define CONFIG_CMD_DHCP
+@@ -128,7 +129,8 @@
+ #define CONFIG_DOS_PARTITION
+ /*#define CONFIG_ISO_PARTITION
+ */
+-#undef CONFIG_CMD_NAND
++#define CONFIG_CMD_NAND
++#define CONFIG_NEW_NAND_CODE
+ #undef CONFIG_CMD_ONENAND
+ #undef CONFIG_CMD_PCMCIA
+ #undef CONFIG_CMD_USB
+@@ -149,7 +151,7 @@
+ /* eval_board=evk9328
+  * Boot options. Setting delay to -1 stops autostart count down.
+  */
+-#define CONFIG_BOOTDELAY	20
++#define CONFIG_BOOTDELAY	-1
+ 
+ #define CONFIG_BOOTARGS \
+ 	CONFIG_CONSOLE " root=/dev/mtdblock3 rootfstype=jffs2 "CONFIG_MTDPARTS
+@@ -277,6 +279,17 @@
+ #define CONFIG_STACKSIZE_FIQ	(4<<10)		/* FIQ stack                  */
+ #endif
+ 
++
++/*=====================*/
++/* Flash & Environment */
++/*=====================*/
++#define CFG_MAX_NAND_DEVICE	1
++#define NAND_MAX_CHIPS		1
++#define CFG_NAND_BASE		(0xD8000000)
++//#define CONFIG_MTD_NAND_VERIFY_WRITE 1
++//#define CFG_NAND_SELECT_DEVICE  1	/* nand driver supports mutipl. chips */
++/*=====================*/
++
+ /*
+ * Clocks configuration
+ */
+@@ -730,18 +743,15 @@
+ /*
+  * Default configuration for GPIOs and peripherals
+  */
+-#define CFG_DDIR_A_VAL		0x00000000
+-#define CFG_OCR1_A_VAL		0x00000000
+-#define CFG_OCR2_A_VAL		0x00000000
++#define CFG_DDIR_A_VAL		0x00FFFFC0  /* for debug */
++#define CFG_OCR1_A_VAL		0xFFFFF000  /* for debug */
++#define CFG_OCR2_A_VAL		0x0000FFFF
+ #define CFG_ICFA1_A_VAL		0xFFFFFFFF
+ #define CFG_ICFA2_A_VAL		0xFFFFFFFF
+ #define CFG_ICFB1_A_VAL		0xFFFFFFFF
+ #define CFG_ICFB2_A_VAL		0xFFFFFFFF
+ #define CFG_DR_A_VAL		0x00000000
+-
+-/* Setup for PA23 which is Reset Default PA23 but has to become
+-   CS5 */
+-#define CFG_GIUS_A_VAL		0x00007FF8
++#define CFG_GIUS_A_VAL		0xFFFFFFFF
+ #define CFG_ICR1_A_VAL		0x00000000
+ #define CFG_ICR2_A_VAL		0x00000000
+ #define CFG_IMR_A_VAL		0x00000000
+@@ -756,7 +766,7 @@
+ #define CFG_ICFB1_B_VAL		0xFFFFFFFF
+ #define CFG_ICFB2_B_VAL		0xFFFFFFFF
+ #define CFG_DR_B_VAL		0x00000000
+-#define CFG_GIUS_B_VAL		0xFFFFFFFF
++#define CFG_GIUS_B_VAL		0xFF3FFFF3
+ #define CFG_ICR1_B_VAL		0x00000000
+ #define CFG_ICR2_B_VAL		0x00000000
+ #define CFG_IMR_B_VAL		0x00000000
+@@ -771,12 +781,12 @@
+ #define CFG_ICFB1_C_VAL		0xFFFFFFFF
+ #define CFG_ICFB2_C_VAL		0xFFFFFFFF
+ #define CFG_DR_C_VAL		0x00000000
+-#define CFG_GIUS_C_VAL		0x0007FFFF
++#define CFG_GIUS_C_VAL		0xFFFFFFFF
+ #define CFG_ICR1_C_VAL		0x00000000
+ #define CFG_ICR2_C_VAL		0x00000000
+ #define CFG_IMR_C_VAL		0x00000000
+ #define CFG_GPR_C_VAL		0x00000000
+-#define CFG_PUEN_C_VAL		0xF913FFFF
++#define CFG_PUEN_C_VAL		0xFFFFFFFF
+ 
+ #define CFG_DDIR_D_VAL		0x00000000
+ #define CFG_OCR1_D_VAL		0x00000000
+@@ -786,13 +796,43 @@
+ #define CFG_ICFB1_D_VAL		0xFFFFFFFF
+ #define CFG_ICFB2_D_VAL		0xFFFFFFFF
+ #define CFG_DR_D_VAL		0x00000000
+-#define CFG_GIUS_D_VAL		0xFFFFFFFF
++#define CFG_GIUS_D_VAL		0xFFFE0000
+ #define CFG_ICR1_D_VAL		0x00000000
+ #define CFG_ICR2_D_VAL		0x00000000
+ #define CFG_IMR_D_VAL		0x00000000
+ #define CFG_GPR_D_VAL		0x00000000
+ #define CFG_PUEN_D_VAL		0xFFFFFFFF
+ 
++#define CFG_DDIR_E_VAL		0x00000000
++#define CFG_OCR1_E_VAL		0x00000000
++#define CFG_OCR2_E_VAL		0x00000000
++#define CFG_ICFA1_E_VAL		0xFFFFFFFF
++#define CFG_ICFA2_E_VAL		0xFFFFFFFF
++#define CFG_ICFB1_E_VAL		0xFFFFFFFF
++#define CFG_ICFB2_E_VAL		0xFFFFFFFF
++#define CFG_DR_E_VAL		0x00000000
++#define CFG_GIUS_E_VAL		0xFFFC0F27
++#define CFG_ICR1_E_VAL		0x00000000
++#define CFG_ICR2_E_VAL		0x00000000
++#define CFG_IMR_E_VAL		0x00000000
++#define CFG_GPR_E_VAL		0x00000000
++#define CFG_PUEN_E_VAL		0xFFFFFFFF
++
++#define CFG_DDIR_F_VAL		0x00000000
++#define CFG_OCR1_F_VAL		0x00000000
++#define CFG_OCR2_F_VAL		0x00000000
++#define CFG_ICFA1_F_VAL		0xFFFFFFFF
++#define CFG_ICFA2_F_VAL		0xFFFFFFFF
++#define CFG_ICFB1_F_VAL		0xFFFFFFFF
++#define CFG_ICFB2_F_VAL		0xFFFFFFFF
++#define CFG_DR_F_VAL		0x00000000
++#define CFG_GIUS_F_VAL		0xFF000000
++#define CFG_ICR1_F_VAL		0x00000000
++#define CFG_ICR2_F_VAL		0x00000000
++#define CFG_IMR_F_VAL		0x00000000
++#define CFG_GPR_F_VAL		0x00000000
++#define CFG_PUEN_F_VAL		0xFFFFFFFF
++
+ #define CFG_GPCR_VAL		0x000003AB
+ 
+ /* FMCR Bit 1 becomes 0 to make CS3 if we have only one sdram bank*/
+--- u-boot-1.3.2/lib_arm/board.c	2008-06-25 04:12:35.000000000 +0200
++++ u-boot-new/lib_arm/board.c	2008-06-24 12:21:12.000000000 +0200
+@@ -342,7 +342,7 @@ void start_armboot (void)
+ 
+ #if defined(CONFIG_CMD_NAND)
+ 	puts ("NAND:  ");
+-	nand_init();		/* go init the NAND */
++	//nand_init();		/* go init the NAND */
+ #endif
+ 
+ #if defined(CONFIG_CMD_ONENAND)


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[Armadeus-commitlog] SF.net SVN: armadeus: [822] branches/apf2/buildroot/target/device/armadeus/ u-boot/u-boot.mk

From: <jo...@us...> - 2008-06-08 14:22:41

Revision: 822
          http://armadeus.svn.sourceforge.net/armadeus/?rev=822&view=rev
Author:   jorasse
Date:     2008-06-08 07:22:20 -0700 (Sun, 08 Jun 2008)

Log Message:
-----------
[u-boot] select location of mkimage tool according to u-boot version.

Modified Paths:
--------------
    branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk

Modified: branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk	2008-06-08 14:04:22 UTC (rev 821)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk	2008-06-08 14:22:20 UTC (rev 822)
@@ -130,7 +130,11 @@
 
 ###-----
 u-boot: $(BINARIES_DIR)/u-boot.bin $(BINARIES_DIR)/u-boot.brec
+ifneq ($(BR2_TARGET_U-BOOT_NG),)
 	ln -fs $(U-BOOT_DIR)/scripts/mkimage $(STAGING_DIR)/bin/mkimage
+else #U-BOOT 1.x
+	ln -fs $(U-BOOT_DIR)/tools/mkimage $(STAGING_DIR)/bin/mkimage
+endif
 
 ###-----
 u-boot-clean:


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[Armadeus-commitlog] SF.net SVN: armadeus: [821] branches/apf2/buildroot/target/device/armadeus/ u-boot

From: <jo...@us...> - 2008-06-08 14:04:23

Revision: 821
          http://armadeus.svn.sourceforge.net/armadeus/?rev=821&view=rev
Author:   jorasse
Date:     2008-06-08 07:04:22 -0700 (Sun, 08 Jun 2008)

Log Message:
-----------
[u-boot] Upgraded to u-boot release 1.3.2.
Added freescale imx27 cpu to u-boot (serial, timer, gpio... ).
Added preliminary version of imx27 ethernet fec driver (not yet functionnal).
Please note the nand flash and nand boot are not supported.

Modified Paths:
--------------
    branches/apf2/buildroot/target/device/armadeus/u-boot/Config.in
    branches/apf2/buildroot/target/device/armadeus/u-boot/u-boot.mk

Added Paths:
-----------
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/100-apx9328.patch
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/101-u-boot-apx9328.patch
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/110-apx-tools.patch
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/120-apx-example.patch
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/140-apx-dm9000.patch
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/150-u-boot-imx.patch
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/200-u-boot-spartan.patch
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/220-u-boot-1.3.2.patch
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/300-u-boot-1.3.2.imx27.patch
    branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/310-u-boot-1.3.2.imx27fec.patch

Modified: branches/apf2/buildroot/target/device/armadeus/u-boot/Config.in
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/Config.in	2008-06-06 21:33:08 UTC (rev 820)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/Config.in	2008-06-08 14:04:22 UTC (rev 821)
@@ -7,6 +7,10 @@
 
 if BR2_TARGET_U-BOOT
 
+config BR2_TARGET_U-BOOT_NG
+	bool "U-Boot 2.x Next Generation"
+	default y
+
 config BR2_TARGET_U-BOOT_CHANGE_NETWORK_PARAMETERS
 	bool "specify U-Boot default network parameters"
 	default n

Added: branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/100-apx9328.patch
===================================================================
--- branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/100-apx9328.patch	                        (rev 0)
+++ branches/apf2/buildroot/target/device/armadeus/u-boot/patches/1.3.2/100-apx9328.patch	2008-06-08 14:04:22 UTC (rev 821)
@@ -0,0 +1,2257 @@
+diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/apx9328.c u-boot-1.1.6/board/apx9328/apx9328.c
+--- ref/u-boot-1.1.6/board/apx9328/apx9328.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/board/apx9328/apx9328.c	2006-11-26 20:28:03.000000000 +0100
+@@ -0,0 +1,75 @@
++/*
++ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++#include <common.h>
++#include <asm/arch/imx-regs.h>
++#include "apx9328fpga.h"
++
++extern void imx_gpio_mode (int gpio_mode);
++
++int
++board_init (void)
++{
++	DECLARE_GLOBAL_DATA_PTR;
++
++	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
++	gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
++
++	return 0;
++}
++
++int
++dram_init (void)
++{
++	DECLARE_GLOBAL_DATA_PTR;
++
++#if ( CONFIG_NR_DRAM_BANKS > 0 )
++	gd->bd->bi_dram[0].start = CFG_SDRAM_1_BASE;
++	gd->bd->bi_dram[0].size = CFG_SDRAM_1_SIZE;
++#endif
++#if ( CONFIG_NR_DRAM_BANKS > 1 )
++	gd->bd->bi_dram[1].start = CFG_SDRAM_2_BASE;
++	gd->bd->bi_dram[1].size = CFG_SDRAM_2_SIZE;
++#endif
++
++	return 0;
++}
++
++/*
++ * Miscellaneous intialization
++ */
++int
++misc_init_r (void)
++{
++#if (CONFIG_FPGA)
++	APX9328_init_fpga ();
++#endif
++
++#if (CONFIG_DRIVER_DM9000)
++	imx_gpio_mode (GPIO_PORTB | GPIO_GPIO | GPIO_IN | 14);
++#endif
++	return 0;
++}
++
++void
++show_boot_progress (int status)
++{
++	return;
++}
+diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/apx9328fpga.c u-boot-1.1.6/board/apx9328/apx9328fpga.c
+--- ref/u-boot-1.1.6/board/apx9328/apx9328fpga.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/board/apx9328/apx9328fpga.c	2006-11-26 20:28:03.000000000 +0100
+@@ -0,0 +1,100 @@
++/*
++ * (C) Copyright 2005
++ * Nicolas Colombin <th...@us...>
++ * Eric Jarrige <jo...@us...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++/*
++ * Spartan 3 FPGA configuration support for the APX9328 daughter board
++ */
++
++#include <common.h>
++#include <spartan3.h>
++#include <command.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include "apx9328fpga.h"
++
++#if (CONFIG_FPGA)
++#if 0
++#define FPGA_DEBUG
++#endif
++
++#ifdef FPGA_DEBUG
++#define	PRINTF(fmt,args...)	printf (fmt ,##args)
++#else
++#define	PRINTF(fmt,args...)
++#endif
++
++/* Note that these are pointers to code that is in Flash.  They will be
++ * relocated at runtime.
++ * Spartan3 code is used to download our Spartan 3 :) code is compatible. 
++ * Just take care about the file size  
++*/
++Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
++	fpga_pre_fn,
++	fpga_pgm_fn,
++	fpga_clk_fn,
++	fpga_init_fn,
++	fpga_done_fn,
++	fpga_wr_fn,
++};
++
++Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
++	{Xilinx_Spartan3,
++	 slave_serial,
++	 XILINX_XC3S400_SIZE,
++	 (void *) &fpga_fns,
++	 0}
++};
++
++/*
++ * Initialize the fpga.  Return 1 on success, 0 on failure.
++ */
++int
++APX9328_init_fpga (void)
++{
++	char *autoload = getenv ("firmware_autoload");
++	DECLARE_GLOBAL_DATA_PTR;
++
++	int i,lout=1;
++
++	PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
++		__FUNCTION__, __LINE__, gd->reloc_off);
++	fpga_init (gd->reloc_off);
++
++	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
++		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
++		fpga_add (fpga_xilinx, &fpga[i]);
++	}
++
++	if (( autoload ) && (0 == strcmp(autoload, "1"))) {
++		if (FPGA_SUCCESS != fpga_load( 0, (void *)CONFIG_FIRMWARE_ADDR, 
++				(size_t) CONFIG_FIRMWARE_LEN )) {
++			lout = 0;
++			printf("Firmware not loaded!\n");
++		}
++	}
++	return 1;
++}
++
++#endif /* CONFIG_FPGA */
+diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/apx9328fpga.h u-boot-1.1.6/board/apx9328/apx9328fpga.h
+--- ref/u-boot-1.1.6/board/apx9328/apx9328fpga.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/board/apx9328/apx9328fpga.h	2006-11-26 20:28:03.000000000 +0100
+@@ -0,0 +1,31 @@
++/*
++ * (C) Copyright 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++/*
++ * Spartan 3 FPGA configuration support for the APX9328 daughter board
++ */
++ 
++#include "fpga.h"
++extern int APX9328_init_fpga (void);
+diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/config.mk u-boot-1.1.6/board/apx9328/config.mk
+--- ref/u-boot-1.1.6/board/apx9328/config.mk	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/board/apx9328/config.mk	2006-11-26 20:28:03.000000000 +0100
+@@ -0,0 +1,10 @@
++#
++# This config file is used for compilation of armadeus sources
++#
++# You might change location of U-Boot in memory by setting right TEXT_BASE.
++# This allows for example having one copy located at the end of ram and stored
++# in flash device and later on while developing use other location to test
++# the code in RAM device only.
++#
++
++TEXT_BASE = 0x0BF80000
+diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/fpga.c u-boot-1.1.6/board/apx9328/fpga.c
+--- ref/u-boot-1.1.6/board/apx9328/fpga.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/board/apx9328/fpga.c	2006-11-26 20:28:03.000000000 +0100
+@@ -0,0 +1,140 @@
++/*
++ * (C) Copyright 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++#include <common.h>
++
++#if (CONFIG_FPGA)
++
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include <config.h>
++
++extern void imx_gpio_mode (int gpio_mode);
++
++
++#define GPIO_PORT(x)  ((x >> 5) & 3)
++#define GPIO_SET(x)   (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
++#define GPIO_CLEAR(x) (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
++#define GPIO_WRITE(x,y) ( y ? GPIO_SET(x) : GPIO_CLEAR(x) )
++#define GPIO_READ(x)  ((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK))))
++
++#if 0
++#define FPGA_DEBUG
++#endif
++
++#ifdef FPGA_DEBUG
++#define	PRINTF(fmt,args...)	printf (fmt ,##args)
++#else
++#define	PRINTF(fmt,args...)
++#endif
++
++/*
++ * Port bit numbers for the serial slave controls
++ */
++#define FPGA_INIT	CFG_FPGA_INIT
++#define FPGA_DONE	CFG_FPGA_DONE
++#define FPGA_DIN	CFG_FPGA_DATA
++#define FPGA_PROGRAM	CFG_FPGA_PRG
++#define FPGA_CLOCK	CFG_FPGA_CLK
++
++/* Note that these are pointers to code that is in Flash.  They will be
++ * relocated at runtime.
++ * Spartan2 code is used to download our Spartan 3 :) code is compatible. 
++ * Just take care about the file size  
++*/
++
++/*
++ * nitialize GPIO port B before download
++ */
++int
++fpga_pre_fn (int cookie)
++{
++	PRINTF ("%s:%d: FPGA PRE ", __FUNCTION__, __LINE__);
++
++	// Initialize GPIO pins
++	imx_gpio_mode (FPGA_INIT | GPIO_GPIO | GPIO_IN );
++	imx_gpio_mode (FPGA_DONE | GPIO_GPIO | GPIO_IN );
++	imx_gpio_mode (FPGA_DIN  | GPIO_GPIO | GPIO_OUT );
++	imx_gpio_mode (FPGA_PROGRAM | GPIO_GPIO | GPIO_OUT );
++	imx_gpio_mode (FPGA_CLOCK | GPIO_GPIO | GPIO_OUT );
++	return cookie;
++}
++
++/*
++ * Set the FPGA's active-low program line to the specified level
++ */
++int
++fpga_pgm_fn (int assert, int flush, int cookie)
++{
++	PRINTF ("%s:%d: FPGA PROGRAM %s", __FUNCTION__, __LINE__, 
++					assert?"high":"low");
++	GPIO_WRITE( FPGA_PROGRAM, !assert);
++	return assert;
++}
++
++/*
++ * Set the FPGA's active-high clock line to the specified level
++ */
++int
++fpga_clk_fn (int assert_clk, int flush, int cookie)
++{
++	PRINTF ("%s:%d: FPGA CLOCK %s", __FUNCTION__, __LINE__, 
++					assert_clk?"high":"low");
++	GPIO_WRITE( FPGA_CLOCK, assert_clk);
++	return assert_clk;
++}
++
++/*
++ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
++ * asserted (low).
++ */
++int
++fpga_init_fn (int cookie)
++{
++	PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
++	return(!GPIO_READ(FPGA_INIT));
++}
++
++/*
++ * Test the state of the active-high FPGA DONE pin
++ */
++int
++fpga_done_fn (int cookie)
++{
++	PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
++	return(GPIO_READ(FPGA_DONE));
++}
++
++/*
++ * Set the FPGA's data line to the specified level
++ */
++int
++fpga_wr_fn (int assert_write, int flush, int cookie)
++{
++	PRINTF ("%s:%d: DATA write... ", __FUNCTION__, __LINE__);
++	GPIO_WRITE( FPGA_DIN, assert_write);
++	return assert_write;
++}
++
++#endif /* CONFIG_FPGA */
+diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/fpga.h u-boot-1.1.6/board/apx9328/fpga.h
+--- ref/u-boot-1.1.6/board/apx9328/fpga.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/board/apx9328/fpga.h	2006-11-26 20:28:03.000000000 +0100
+@@ -0,0 +1,30 @@
++/*
++ * (C) Copyright 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++extern int fpga_pre_fn (int cookie);
++extern int fpga_pgm_fn (int assert_pgm, int flush, int cookie);
++extern int fpga_init_fn (int cookie);
++extern int fpga_done_fn (int cookie);
++extern int fpga_clk_fn (int assert_clk, int flush, int cookie);
++extern int fpga_wr_fn (int assert_write, int flush, int cookie);
+diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/i2c.c u-boot-1.1.6/board/apx9328/i2c.c
+--- ref/u-boot-1.1.6/board/apx9328/i2c.c	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/board/apx9328/i2c.c	2006-11-26 20:28:03.000000000 +0100
+@@ -0,0 +1,327 @@
++/*
++ * Eric Jarrige <jo...@us...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ *
++ */
++
++#include <common.h>
++
++#ifdef CONFIG_HARD_I2C
++
++#include <asm/io.h>
++#include <asm/arch/imx-regs.h>
++#include <i2c.h>
++
++/*#define       DEBUG_I2C*/
++
++extern void imx_gpio_mode (int gpio_mode);
++
++/*-----------------------------------------------------------------------
++ * Definitions
++ */
++
++#define I2C_ACK		0	/* level to ack a byte */
++#define I2C_NOACK	1	/* level to noack a byte */
++
++
++#ifdef DEBUG_I2C
++#define PRINTD(fmt,args...)	do {	\
++	DECLARE_GLOBAL_DATA_PTR;	\
++	if (gd->have_console)		\
++		printf (fmt ,##args);	\
++	} while (0)
++#else
++#define PRINTD(fmt,args...)
++#endif
++
++/*-----------------------------------------------------------------------
++ * Local functions
++ */
++
++/*-----------------------------------------------------------------------
++ * START: High -> Low on SDA while SCL is High
++ * after check for a bus free
++ */
++static void
++imxi2c_send_start (void)
++{
++	while ((I2SR & I2SR_IBB)) ;
++	I2CR |= I2CR_MSTA;
++	I2SR &= ~I2SR_IIF;
++}
++
++/*-----------------------------------------------------------------------
++ * STOP: Low -> High on SDA while SCL is High
++ * after the end of previous transfer
++ */
++static void
++imxi2c_send_stop (void)
++{
++	while (!(I2SR & I2SR_ICF)) ;
++	I2CR &= ~I2CR_MSTA;
++}
++
++/*-----------------------------------------------------------------------
++ * Send 8 bits and look for an acknowledgement.
++ */
++static int
++imxi2c_write_byte (uchar data)
++{
++	while (!(I2SR & I2SR_ICF)) ;	/* Wait end of transfer */
++
++	I2CR |= I2CR_MTX;
++	I2SR &= ~I2SR_IIF;
++	I2DR = data;
++
++	while (!(I2SR & I2SR_IIF)) ;	/* checking IIF before ICF seems required */
++
++	I2SR &= ~I2SR_IIF;
++
++	while (!(I2SR & I2SR_ICF)) ;	/* Wait end of transfer */
++
++	return (I2SR & I2SR_RXAK);	/* not a nack is an ack */
++}
++
++/*-----------------------------------------------------------------------
++ * if ack == I2C_ACK, ACK the byte so can continue reading, else
++ * send I2C_NOACK to end the read.
++ */
++static uchar
++imxi2c_read_byte (int ack)
++{
++	int data;
++
++	while (!(I2SR & I2SR_ICF)) ;
++	I2CR &= ~I2CR_MTX;
++
++	if (ack)
++	{
++		I2CR |= I2CR_TXAK;
++	}
++	else
++	{
++		I2CR &= ~I2CR_TXAK;
++	}
++
++	data = I2DR;
++	return (data);
++}
++
++/* ------------------------------------------------------------------------
++ * API Functions
++ * ------------------------------------------------------------------------
++ */
++
++/*-----------------------------------------------------------------------
++ * i2c_init compute the i2c divider to reach the requested speed
++ * see mxl reference manual
++ */
++void
++i2c_init (int speed, int slaveaddr)
++{
++	int hclk_dividers[] = {
++		30, 32, 36, 42, 48, 52, 60, 72,
++		80, 88, 104, 128, 144, 160, 192, 240,
++		288, 320, 384, 480, 576, 640, 768, 960,
++		1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840,
++		22, 24, 26, 26, 32, 36, 40, 44,
++		48, 56, 64, 72, 80, 96, 112, 128,
++		160, 192, 224, 256, 320, 384, 448, 512,
++		640, 768, 896, 1024, 1280, 1536, 1792, 2048
++	};
++	int refDiv = get_HCLK () / speed;
++	int i, tmpIC;
++
++	imx_gpio_mode (PA15_PF_I2C_SDA);
++	imx_gpio_mode (PA16_PF_I2C_SCL);
++
++	tmpIC = (sizeof (hclk_dividers) / sizeof (int)) - 1;
++	for (i = tmpIC; i >= 0; i--)
++	{
++		if ((hclk_dividers[i] >= refDiv)
++		    && (hclk_dividers[i] < hclk_dividers[tmpIC]))
++		{
++			tmpIC = i;
++		}
++	}
++	
++	IFDR = tmpIC;
++	IADR = slaveaddr << 1;
++
++	if (I2SR & I2SR_IBB)
++		imxi2c_send_stop ();
++
++	I2CR |= I2CR_IEN;
++}
++
++/*-----------------------------------------------------------------------
++ * Probe to see if a chip is present. Also good for checking for the
++ * completion of EEPROM writes since the chip stops responding until
++ * the write completes (typically 10mSec).
++ * probe sends a read command to probe a an address
++ */
++int
++i2c_probe (uchar addr)
++{
++	int rc;
++
++	imxi2c_send_start ();
++	rc = imxi2c_write_byte ((addr << 1) | 0);
++	imxi2c_send_stop ();
++
++	return (rc ? 1 : 0);
++}
++
++/*-----------------------------------------------------------------------
++ * Read bytes
++ */
++int
++i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
++{
++	int shift;
++	PRINTD ("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
++		chip, addr, alen, buffer, len);
++
++#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
++	/*
++	 * EEPROM chips that implement "address overflow" are ones
++	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
++	 * address and the extra bits end up in the "chip address"
++	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
++	 * four 256 byte chips.
++	 *
++	 * Note that we consider the length of the address field to
++	 * still be one byte because the extra address bits are
++	 * hidden in the chip address.
++	 */
++	chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
++
++	PRINTD ("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
++		chip, addr);
++#endif
++
++	/*
++	 * Do the addressing portion of a write cycle to set the
++	 * chip's address pointer. If the address length is zero,
++	 * don't do the normal write cycle to set the address pointer,
++	 * there is no address pointer in this chip.
++	 */
++	imxi2c_send_start ();
++	if (alen > 0)
++	{
++		if (imxi2c_write_byte (chip << 1))
++		{		/* write cycle */
++			imxi2c_send_stop ();
++			PRINTD ("i2c_read, no chip responded %02X\n", chip);
++			return (1);
++		}
++		shift = (alen - 1) * 8;
++		while (alen-- > 0)
++		{
++			if (imxi2c_write_byte (addr >> shift))
++			{
++				PRINTD ("i2c_read, address not <ACK>ed\n");
++				return (1);
++			}
++			shift -= 8;
++		}
++		imxi2c_send_stop ();	/* reportedly some chips need a full stop */
++		imxi2c_send_start ();
++	}
++	/*
++	 * Send the chip address again, this time for a read cycle.
++	 * Then read the data. On the last byte, we do a NACK instead
++	 * of an ACK(len == 0) to terminate the read.
++	 */
++	imxi2c_write_byte ((chip << 1) | 1);	/* read cycle */
++	imxi2c_read_byte (len <= 2);
++	while (len-- > 1)
++	{
++		*buffer++ = imxi2c_read_byte (len == 1);
++	}
++	imxi2c_send_stop ();
++	*buffer++ = imxi2c_read_byte (0);
++	return (0);
++}
++
++/*-----------------------------------------------------------------------
++ * Write bytes
++ */
++int
++i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
++{
++	int shift, failures = 0;
++
++	PRINTD ("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
++		chip, addr, alen, buffer, len);
++
++	imxi2c_send_start ();
++	if (imxi2c_write_byte (chip << 1))
++	{			/* write cycle */
++		imxi2c_send_stop ();
++		PRINTD ("i2c_write, no chip responded %02X\n", chip);
++		return (1);
++	}
++	shift = (alen - 1) * 8;
++	while (alen-- > 0)
++	{
++		if (imxi2c_write_byte (addr >> shift))
++		{
++			PRINTD ("i2c_write, address not <ACK>ed\n");
++			return (1);
++		}
++		shift -= 8;
++	}
++
++	while (len-- > 0)
++	{
++		if (imxi2c_write_byte (*buffer++))
++		{
++			failures++;
++		}
++	}
++	imxi2c_send_stop ();
++	return (failures);
++}
++
++/*-----------------------------------------------------------------------
++ * Read a register
++ */
++uchar
++i2c_reg_read (uchar i2c_addr, uchar reg)
++{
++	char buf;
++
++	i2c_read (i2c_addr, reg, 1, &buf, 1);
++
++	return (buf);
++}
++
++/*-----------------------------------------------------------------------
++ * Write a register
++ */
++void
++i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
++{
++	i2c_write (i2c_addr, reg, 1, &val, 1);
++}
++
++#endif /* CONFIG_HARD_I2C */
+diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/lowlevel_init.S u-boot-1.1.6/board/apx9328/lowlevel_init.S
+--- ref/u-boot-1.1.6/board/apx9328/lowlevel_init.S	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/board/apx9328/lowlevel_init.S	2006-12-03 12:06:16.000000000 +0100
+@@ -0,0 +1,443 @@
++/*
++ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
++ * 02111-1307, USA.
++ *
++ */
++
++#include <config.h>
++#include <version.h>
++#include <asm/arch/imx-regs.h>
++
++.globl lowlevel_init
++lowlevel_init:
++
++	mov	r10, lr
++
++/* Change PERCLK1DIV to 14 ie 14+1 */
++	ldr		r0,	=PCDR
++	ldr		r1,	=CFG_PCDR_VAL
++	str		r1,	[r0]
++
++/* set MCU PLL Control Register 0 */
++
++	ldr		r0,	=MPCTL0
++	ldr		r1,	=CFG_MPCTL0_VAL
++	str		r1,	[r0]
++
++/* set MCU PLL Control Register 1 */
++
++	ldr		r0,	=MPCTL1
++	ldr		r1,	=CFG_MPCTL1_VAL
++	str		r1,	[r0]
++
++/* set mpll restart bit */
++	ldr		r0, =CSCR
++	ldr		r1, [r0]
++	orr		r1,r1,#(1<<21)
++	str		r1, [r0]
++
++	mov		r2,#0x10
++1:
++	mov		r3,#0x2000
++2:
++	subs	r3,r3,#1
++	bne		2b
++
++	subs	r2,r2,#1
++	bne		1b
++
++/* set System PLL Control Register 0 */
++
++	ldr		r0,	=SPCTL0
++	ldr		r1,	=CFG_SPCTL0_VAL
++	str		r1,	[r0]
++
++/* set System PLL Control Register 1 */
++
++	ldr		r0,	=SPCTL1
++	ldr		r1,	=CFG_SPCTL1_VAL
++	str		r1,	[r0]
++
++/* set spll restart bit */
++	ldr		r0, =CSCR
++	ldr		r1, [r0]
++	orr		r1,r1,#(1<<22)
++	str		r1, [r0]
++
++	mov		r2,#0x10
++1:
++	mov		r3,#0x2000
++2:
++	subs	r3,r3,#1
++	bne		2b
++
++	subs	r2,r2,#1
++	bne		1b
++
++	ldr		r0,	=CSCR
++	ldr		r1,	=CFG_CSCR_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GPCR
++	ldr		r1,	=CFG_GPCR_VAL
++	str		r1,	[r0]
++
++/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
++ *this.....
++ *
++ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
++ * register 1, this stops it using the output of the PLL and thus runs at the
++ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
++ * use the value set in the CM_OSC registers...regardless of what you set it
++ * too!  Thus, although i thought i was running at 140MHz, i'm actually running
++ * at 40!..
++
++ * Slapping this into my bootloader does the trick...
++
++ * MRC p15,0,r0,c1,c0,0	 ; read core configuration register
++ * ORR r0,r0,#0xC0000000	; set asynchronous clocks and not fastbus mode
++ * MCR p15,0,r0,c1,c0,0	 ; write modified value to core configuration
++ * register
++ */
++	MRC p15,0,r0,c1,c0,0
++	ORR r0,r0,#0xC0000000
++	MCR p15,0,r0,c1,c0,0
++
++/*	ldr		r0,	=GPR(0) 
++	ldr		r1,	=CFG_GPR_A_VAL
++	str		r1,	[r0]
++*/
++
++	ldr		r0,	=DR(0)
++	ldr		r1,	=CFG_DR_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR1(0)
++	ldr		r1,	=CFG_OCR1_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR2(0)
++	ldr		r1,	=CFG_OCR2_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA1(0)
++	ldr		r1,	=CFG_ICFA1_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA2(0)
++	ldr		r1,	=CFG_ICFA2_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB1(0)
++	ldr		r1,	=CFG_ICFB1_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB2(0)
++	ldr		r1,	=CFG_ICFB2_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR1(0)
++	ldr		r1,	=CFG_ICR1_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR2(0)
++	ldr		r1,	=CFG_ICR2_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=IMR(0)
++	ldr		r1,	=CFG_IMR_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DDIR(0)
++	ldr		r1,	=CFG_DDIR_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GPR(0)
++	ldr		r1,	=CFG_GPR_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=PUEN(0)
++	ldr		r1,	=CFG_PUEN_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GIUS(0)
++	ldr		r1,	=CFG_GIUS_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DR(1)
++	ldr		r1,	=CFG_DR_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR1(1)
++	ldr		r1,	=CFG_OCR1_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR2(1)
++	ldr		r1,	=CFG_OCR2_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA1(1)
++	ldr		r1,	=CFG_ICFA1_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA2(1)
++	ldr		r1,	=CFG_ICFA2_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB1(1)
++	ldr		r1,	=CFG_ICFB1_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB2(1)
++	ldr		r1,	=CFG_ICFB2_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR1(1)
++	ldr		r1,	=CFG_ICR1_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR2(1)
++	ldr		r1,	=CFG_ICR2_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=IMR(1)
++	ldr		r1,	=CFG_IMR_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DDIR(1)
++	ldr		r1,	=CFG_DDIR_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GPR(1)
++	ldr		r1,	=CFG_GPR_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=PUEN(1)
++	ldr		r1,	=CFG_PUEN_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GIUS(1)
++	ldr		r1,	=CFG_GIUS_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DR(2)
++	ldr		r1,	=CFG_DR_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR1(2)
++	ldr		r1,	=CFG_OCR1_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR2(2)
++	ldr		r1,	=CFG_OCR2_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA1(2)
++	ldr		r1,	=CFG_ICFA1_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA2(2)
++	ldr		r1,	=CFG_ICFA2_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB1(2)
++	ldr		r1,	=CFG_ICFB1_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB2(2)
++	ldr		r1,	=CFG_ICFB2_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR1(2)
++	ldr		r1,	=CFG_ICR1_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR2(2)
++	ldr		r1,	=CFG_ICR2_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=IMR(2)
++	ldr		r1,	=CFG_IMR_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DDIR(2)
++	ldr		r1,	=CFG_DDIR_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GPR(2)
++	ldr		r1,	=CFG_GPR_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=PUEN(2)
++	ldr		r1,	=CFG_PUEN_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GIUS(2)
++	ldr		r1,	=CFG_GIUS_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DR(3)
++	ldr		r1,	=CFG_DR_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR1(3)
++	ldr		r1,	=CFG_OCR1_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR2(3)
++	ldr		r1,	=CFG_OCR2_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA1(3)
++	ldr		r1,	=CFG_ICFA1_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA2(3)
++	ldr		r1,	=CFG_ICFA2_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB1(3)
++	ldr		r1,	=CFG_ICFB1_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB2(3)
++	ldr		r1,	=CFG_ICFB2_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR1(3)
++	ldr		r1,	=CFG_ICR1_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR2(3)
++	ldr		r1,	=CFG_ICR2_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=IMR(3)
++	ldr		r1,	=CFG_IMR_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DDIR(3)
++	ldr		r1,	=CFG_DDIR_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GPR(3)
++	ldr		r1,	=CFG_GPR_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=PUEN(3)
++	ldr		r1,	=CFG_PUEN_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GIUS(3)
++	ldr		r1,	=CFG_GIUS_D_VAL
++	str		r1,	[r0]
++
++/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
++
++	ldr		r0,	=FMCR
++	ldr		r1,	=CFG_FMCR_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS0U
++	ldr		r1,	=CFG_CS0U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS0L
++	ldr		r1,	=CFG_CS0L_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS1U
++	ldr		r1,	=CFG_CS1U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS1L
++	ldr		r1,	=CFG_CS1L_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS2U
++	ldr		r1,	=CFG_CS2U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS2L
++	ldr		r1,	=CFG_CS2L_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS3U
++	ldr		r1,	=CFG_CS3U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS3L
++	ldr		r1,	=CFG_CS3L_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS4U
++	ldr		r1,	=CFG_CS4U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS4L
++	ldr		r1,	=CFG_CS4L_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS5U
++	ldr		r1,	=CFG_CS5U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS5L
++	ldr		r1,	=CFG_CS5L_VAL
++	str		r1,	[r0]
++
++	adr	r0, sdramsetup	/* r0 <- current position of code */
++	ldr	r1, =CFG_SDRAM_1_BASE	/* test if we run from flash or RAM */
++	cmp	r1, r0		/* don't reloc during debug*/
++	bhi		sdramsetup
++	ldr	r1, =CFG_FLASH_BASE	/* test if we run from flash or RAM */
++	cmp	r0, r1		/* don't reloc during debug */
++	bmi		endofmemsetup
++
++/* SDRAM Setup */
++sdramsetup:
++	ldr		r0, =SDCTL0
++	ldr		r1, =CFG_PRECHARGE_CMD
++	str		r1,	[r0]
++
++	ldr		r1, =CFG_SDRAM_1_BASE+CFG_SDRAM_PRECHARGE_ALL_VAL
++	ldr		r2,	[r1]
++
++	ldr		r1, =CFG_AUTOREFRESH_CMD
++	str		r1,	[r0]
++
++	ldr		r1, =CFG_SDRAM_1_BASE
++	ldr		r2,	[r1] /* Issue AutoRefresh Command */
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++
++	ldr		r1, =CFG_SET_MODE_REG_CMD
++	str		r1,	[r0]
++
++	ldr		r1, =CFG_SDRAM_1_BASE+CFG_SDRAM_MODE_REGISTER_VAL
++	str		r2,	[r1]
++
++	ldr		r1, =CFG_NORMAL_RW_CMD 
++	str		r1,	[r0]
++
++endofmemsetup:
++	mov	pc,r10
+diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/Makefile u-boot-1.1.6/board/apx9328/Makefile
+--- ref/u-boot-1.1.6/board/apx9328/Makefile	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/board/apx9328/Makefile	2006-11-26 20:28:03.000000000 +0100
+@@ -0,0 +1,47 @@
++#
++# (C) Copyright 2000-2004
++# Wolfgang Denk, DENX Software Engineering, wd...@de....
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= lib$(BOARD).a
++
++OBJS	:= apx9328.o i2c.o apx9328fpga.o fpga.o
++SOBJS	:= lowlevel_init.o
++
++$(LIB):	$(OBJS) $(SOBJS)
++	$(AR) crv $@ $^
++
++clean:
++	rm -f $(SOBJS) $(OBJS)
++
++distclean:	clean
++	rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -purN -x '*~' ref/u-boot-1.1.6/board/apx9328/u-boot.lds u-boot-1.1.6/board/apx9328/u-boot.lds
+--- ref/u-boot-1.1.6/board/apx9328/u-boot.lds	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/board/apx9328/u-boot.lds	2006-11-26 20:28:03.000000000 +0100
+@@ -0,0 +1,56 @@
++/*
++ * (C) Copyright 2000-2004
++ * Wolfgang Denk, DENX Software Engineering, wd...@de....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++	. = 0x00000000;
++
++	. = ALIGN(4);
++	.text      :
++	{
++		cpu/arm920t/start.o	(.text)
++		*(.text)
++	}
++
++	. = ALIGN(4);
++	.rodata : { *(.rodata) }
++
++	. = ALIGN(4);
++	.data : { *(.data) }
++
++	. = ALIGN(4);
++	.got : { *(.got) }
++
++	__u_boot_cmd_start = .;
++	.u_boot_cmd : { *(.u_boot_cmd) }
++	__u_boot_cmd_end = .;
++
++	. = ALIGN(4);
++	__bss_start = .;
++	.bss : { *(.bss) }
++	_end = .;
++}
+diff -purN -x '*~' ref/u-boot-1.1.6/include/configs/apx9328.h u-boot-1.1.6/include/configs/apx9328.h
+--- ref/u-boot-1.1.6/include/configs/apx9328.h	1970-01-01 01:00:00.000000000 +0100
++++ u-boot-1.1.6/include/configs/apx9328.h	2006-12-03 12:08:06.000000000 +0100
+@@ -0,0 +1,954 @@
++/*
++ * Eric Jarrige <jo...@us...>
++ *
++ * Configuation settings for the Armadeus Project motherboard 9328 board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * 2005/01/14 Initial version taken from the scb9328 configuration file
++ * 2005/03/10 apx9328 configuration file and trial to improve of
++ *		hardware register control.
++ * 2005/08/16 added APX9328 fpgas and ethernet
++ * 2005/12/02 added filesystem boot over NFS
++ * 2006/11/26 added filesystem boot over NFS
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++#define CONFIG_IDENT_STRING	" apx9328 patch 2.7"
++
++#define CONFIG_ARM920T		1	/* this is an ARM920T CPU */
++#define CONFIG_IMX		1	/* in a Motorola MC9328MXL Chip */
++#define CONFIG_APX9328		1	/* on a Armadeus project board */
++#undef	CONFIG_USE_IRQ			/* don't need use IRQ/FIQ */
++
++/*
++ * Enable the call to misc_init_r() for miscellaneous platform
++ * dependent initialization.
++ */
++
++#define CONFIG_MISC_INIT_R
++
++/*
++ * Select serial console configuration
++ */
++#define CONFIG_IMX_SERIAL1
++#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
++#define CONFIG_BAUDRATE 	115200
++
++/*
++ * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if
++ * neccessary in include/cmd_confdefs.h file. (Un)comment for getting
++ * functionality or size of u-boot code.
++ */
++#define CONFIG_COMMANDS		(CONFIG_CMD_DFL		\
++				| CFG_CMD_NET		\
++				| CFG_CMD_PING		\
++				| CFG_CMD_DHCP		\
++				| CFG_CMD_JFFS2		\
++				| CFG_CMD_I2C		\
++				| CFG_CMD_DATE		\
++				| CFG_CMD_EEPROM	\
++				| CONFIG_CMD_ALL	\
++				)
++
++#include <cmd_confdefs.h>
++
++/*
++ * Select some advanced features of the commande line parser
++ */
++#define CONFIG_AUTO_COMPLETE 	1	/* Enable auto completion of */
++					/* commands using TAB */
++#define CFG_HUSH_PARSER		1	/* enable the "hush" shell */
++#define CFG_PROMPT_HUSH_PS2	"> "	/* secondary prompt string */
++#define CONFIG_CMDLINE_EDITING  1
++/* eval_board=evk9328
++ * Boot options. Setting delay to -1 stops autostart count down.
++ */
++#define CONFIG_BOOTDELAY	20
++
++#define CONFIG_BOOTARGS \
++	CONFIG_CONSOLE " root=/dev/mtdblock4 rootfstype=jffs2 "CONFIG_MTDPARTS
++
++#define CONFIG_CONSOLE "console=ttySMX0,"MK_STR(CONFIG_BAUDRATE)"n8"
++#define CONFIG_MTDMAP  "apf9328_flash"
++#define CONFIG_MTDPARTS "mtdparts=" CONFIG_MTDMAP ":256k(U-boot)ro,"    \
++			"128k(U-boot_env),256k(firmware),1536k(kernel),6016k(root)"
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++	"fileaddr="		MK_STR(CFG_LOAD_ADDR)		"\0"	\
++	"filesize="		MK_STR(CFG_MONITOR_LEN)		"\0"	\
++	"console="		CONFIG_CONSOLE			"\0"	\
++	"mtdparts="		CONFIG_MTDPARTS			"\0"	\
++	"uboot_addr="		MK_STR(CFG_MONITOR_BASE)	"\0"	\
++	"uboot_len="		MK_STR(CFG_MONITOR_LEN)		"\0"	\
++	"env_addr="		MK_STR(CFG_ENV_ADDR)		"\0"	\
++	"env_len="		MK_STR(CFG_ENV_SIZE)		"\0"	\
++	"firmware_addr="	MK_STR(CONFIG_FIRMWARE_ADDR)	"\0"	\
++	"firmware_len="	MK_STR(CONFIG_FIRMWARE_LEN)	"\0"	\
++	"kernel_addr="		MK_STR(CONFIG_KERNEL_ADDR)	"\0"	\
++	"kernel_len="		MK_STR(CONFIG_KERNEL_LEN)	"\0"	\
++	"rootfs_addr="		MK_STR(CONFIG_ROOTFS_ADDR)	"\0"	\
++	"rootfs_len="		MK_STR(CONFIG_ROOTFS_LEN)	"\0"	\
++	"mmcroot=/dev/mmcblk0p1\0"					\
++	"mmcrootfstype=ext2\0"						\
++	"addnfsargs=setenv bootargs ${bootargs} "			\
++		"root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"    \
++	"addjffsargs=setenv bootargs ${bootargs} "			\
++		"root=/dev/mtdblock4 rootfstype=jffs2\0"   		\
++	"addmmcargs=setenv bootargs ${bootargs} "			\
++		"root=${mmcroot} rootfstype=${mmcrootfstype}\0"   		\
++	"addipargs=setenv bootargs ${bootargs} "			\
++		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off \0"\
++	"nfsboot=setenv bootargs ${console} ${mtdparts};"		\
++		"run addnfsargs addipargs; bootm ${kernel_addr}\0"	\
++	"jffsboot=setenv bootargs ${console} ${mtdparts};"		\
++		"run addjffsargs addipargs; bootm ${kernel_addr}\0"	\
++	"mmcboot=setenv bootargs ${console} ${mtdparts};"		\
++		"run addmmcargs addipargs; bootm ${kernel_addr}\0"	\
++	"firmware_autoload=0\0"						\
++	"flash_uboot=protect off ${uboot_addr} +${uboot_len};"		\
++		"era ${uboot_addr} +${uboot_len};"			\
++		"if cp.b ${fileaddr} ${uboot_addr} ${filesize};"	\
++			"then protect on ${uboot_addr} +${uboot_len};"	\
++				"echo Flashing uboot succeed;"		\
++			"else echo Flashing uboot failed;"		\
++		"fi; \0"						\
++	"flash_firmware=era ${firmware_addr} +${firmware_len};"		\
++		"if cp.b ${fileaddr} ${firmware_addr} ${filesize} ;"	\
++			"then echo Flashing Firmware succeed;"		\
++			"else echo Flashing Firmware failed;"		\
++		"fi\0"							\
++	"flash_kernel=era ${kernel_addr} +${kernel_len};"		\
++		"if cp.b ${fileaddr} ${kernel_addr} ${filesize} ;"	\
++			"then echo Flashing kernel succeed;"		\
++			"else echo Flashing kernel failed;"		\
++		"fi\0"							\
++	"flash_rootfs=era ${rootfs_addr} +${rootfs_len};"		\
++		"if cp.b ${fileaddr} ${rootfs_addr} ${filesize};"	\
++			"then echo Flashing rootfs succeed;"		\
++			"else echo Flashing rootfs failed;"		\
++		"fi\0"							\
++	"flash_reset_env=protect off ${env_addr} +${env_len};"		\
++		"era ${env_addr} +${env_len};"				\
++		"echo Erasinf flash environment variables done!"	\
++
++#define CONFIG_BOOTCOMMAND	"run jffsboot"
++#define CFG_AUTOLOAD		"no"
++
++#define MACH_TYPE_APX9328	MACH_TYPE_SCB9328
++
++#define CONFIG_MACH_TYPE MACH_TYPE_APF9328
++#define CONFIG_BOOT_PARAMS_ADDR	0x08000100
++
++/*
++ * #define CONFIG_SHOW_BOOT_PROGRESS
++ */
++
++#define CONFIG_ETHADDR		00:1E:AC:00:00:01
++#define CONFIG_NETMASK		255.255.255.0
++#define CONFIG_IPADDR		192.168.000.10
++#define CONFIG_HOSTNAME		"armadeus"
++#define CONFIG_GATEWAYIP	192.168.000.1
++#define CONFIG_SERVERIP		192.168.000.1
++#define CONFIG_ROOTPATH		"/tftpboot/root"
++
++/*
++ * General options for u-boot. Modify to save memory foot print
++ */
++
++#define CFG_LONGHELP
++#define CFG_PROMPT		"BIOS> "	/* prompt string      */
++#define CFG_CBSIZE		256		/* console I/O buffer */
++#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* print buffer size  */
++#define CFG_MAXARGS		16		/* max command args   */
++#define CFG_BARGSIZE		CFG_CBSIZE	/* boot args buf size */
++
++#define CFG_MEMTEST_START	0x08000000	/* memtest test area  */
++#define CFG_MEMTEST_END		0x08700000
++
++#undef	CFG_CLKS_IN_HZ				/* use HZ for freq. display  */
++#define CFG_HZ			1000000		/* incrementer freq: 1 MHz   */
++
++/*
++ * Definitions related to passing arguments to kernel.
++ */
++
++#define CONFIG_CMDLINE_TAG	1	/* send commandline to Kernel        */
++#define CONFIG_SETUP_MEMORY_TAGS 1	/* send memory definition to kernel */
++#define CONFIG_INITRD_TAG	1	/* send initrd params                */
++#undef	CONFIG_VFD			/* do not send framebuffer setup    */
++
++/*
++ * Malloc pool need to host env + 128 Kb reserve for other allocations.
++ */
++#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + (128<<10) )
++
++#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
++
++#define CONFIG_STACKSIZE	(120<<10)	/* stack size                 */
++
++#ifdef CONFIG_USE_IRQ
++#define CONFIG_STACKSIZE_IRQ	(4<<10)		/* IRQ stack                  */
++#define CONFIG_STACKSIZE_FIQ	(4<<10)		/* FIQ stack                  */
++#endif
++
++/*
++* Clocks configuration
++*/
++/*
++ * PLL configuration
++
++   f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
++   f_ref=16,777216MHz
++   32768 Hz xtal
++   0x07B32DA5: 192.0000173
++   0x002a141f: 191,9944MHz
++   0x040b2007: 144MHz
++   0x0FB32DA5: 96.00000864 MHz
++   0x042a141f: 96MHz
++   0x0811140d: 64MHz
++   0x040e200e: 150MHz
++   0x00321431: 200MHz
++
++  16 MHz xtal 
++   0x08001800: 64MHz mit 16er Quarz
++   0x04001800: 96MHz mit 16er Quarz
++   0x04002400: 144MHz mit 16er Quarz
++
++   31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
++      |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------|
++ */
++
++#define CFG_OSC32	32768	/* 32768 or 32000 Hz crystal */
++#undef  CFG_OSC16		/* there is no external 16MHz external clock */
++
++/* MPU CLOCK source before PLL  (should be named CFG_SYS_CLK_FREQ) */
++#define CONFIG_SYS_CLK_FREQ	(512*CFG_OSC32)
++#define CFG_MPCTL0_VAL		0x07B32DA5	/* 192.000017 MHz */
++#define CFG_MPCTL1_VAL		0
++
++/* system clock source before PLL (should be named CFG_SYSPLL_CLK_FREQ) */
++#ifndef CFG_OSC16
++#define CONFIG_SYSPLL_CLK_FREQ	(512*CFG_OSC32)
++#if (CFG_OSC32 == 32000)
++#define CFG_SPCTL0_VAL		0x043F1437	/* 96 MHz */
++#define CFG_SPCTL1_VAL		0
++#define CONFIG_SYS_FREQ		96		/* MHz */
++#else /* CFG_OSC32 == 32768*/
++#define CFG_SPCTL0_VAL		0x0FB32DA5	/* 96.000009 MHz */
++#define CFG_SPCTL1_VAL		0
++#define CONFIG_SYS_FREQ		96		/* MHz */
++#endif /* CFG_OSC32 */
++#else /* CFG_OSC16 in use*/
++#define CONFIG_SYSPLL_CLK_FREQ	CFG_OSC16
++#define CFG_SPCTL0_VAL		0x04001401	/* 96 MHz */
++#define CFG_SPCTL1_VAL		0x0C000040
++#define CONFIG_SYS_FREQ		96		/* MHz */
++#endif /* CFG_OSC16 */
++
++/* external bus frequency (have to be a CONFIG_SYS_FREQ ratio) */
++#define CONFIG_SYS_BUS_FREQ 	96	/* 96|48... MHz (BCLOCK and HCLOCK) */
++#define CONFIG_USB_FREQ		48	/* 48 MHz */
++#define CONFIG_PERIF1_FREQ	16	/* 16 MHz UART, Timer PWM*/
++#define CONFIG_PERIF2_FREQ 	48	/* 48 MHz LCD SD SPI*/
++#define CONFIG_PERIF3_FREQ	16	/* 16 MHz SSI*/
++
++
++/*
++ * SDRAM definition parameter
++ */
++#define CONFIG_NR_DRAM_BANKS	1	/* we have and support only 1 bank of SDRAM */
++
++#define CFG_SDRAM_MBYTE_SYZE 16
++
++#if (CFG_SDRAM_MBYTE_SYZE == 8)
++/* micron 8MB */
++#define CFG_SDRAM_1_BASE	0x08000000 /* SDRAM bank #1 32bits         */
++#define CFG_SDRAM_1_SIZE	0x00800000 /* 8 MB                */
++#define CFG_SDRAM_NUM_COL		8  /* 8, 9, 10 or 11 column address bits */
++#define CFG_SDRAM_NUM_ROW		11 /* 11, 12 or 13 row address bits */
++#define CFG_SDRAM_REFRESH		2  /* 0=OFF 1=2048 2=4096 3=8192 refresh */
++#define CFG_SDRAM_CLOCK_CYCLE_CL_1	20 /* ns clock cycle time when CL=1 */
++#define CFG_SDRAM_ROW_PRECHARGE_DELAY	20 /* ns SRP */
++#define CFG_SDRAM_ROW_2_COL_DELAY	20 /* ns SRCD */
++#define CFG_SDRAM_ROW_CYCLE_DELAY	70 /* ns SRC */
++#define CFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
++#define CFG_SDRAM_SINGLE_ACCESS		0  /* 1= single access; 0 = Burst mode */
++#endif
++
++#if (CFG_SDRAM_MBYTE_SYZE == 16)
++/* micron 16MB */
++#define CFG_SDRAM_1_BASE	0x08000000 /* SDRAM bank #1 32bits    */
++#define CFG_SDRAM_1_SIZE	0x01000000 /* 16 MB                   */
++#define CFG_SDRAM_NUM_COL		8  /* 8, 9, 10 or 11 column address bits */
++#define CFG_SDRAM_NUM_ROW		12 /* 11, 12 or 13 row address bits */
++#define CFG_SDRAM_REFRESH		2  /* 0=OFF 1=2048 2=4096 3=8192 refresh */
++#define CFG_SDRAM_CLOCK_CYCLE_CL_1	20 /* ns clock cycle time when CL=1 */
++#define CFG_SDRAM_ROW_PRECHARGE_DELAY	20 /* ns SRP */
++#define CFG_SDRAM_ROW_2_COL_DELAY	20 /* ns SRCD */
++#define CFG_SDRAM_ROW_CYCLE_DELAY	70 /* ns SRC */
++#define CFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
++#define CFG_SDRAM_SINGLE_ACCESS		0  /* 1= single access; 0 = Burst mode */
++#endif
++
++#if (CFG_SDRAM_MBYTE_SYZE == 32)
++/* micron 32MB */
++#define CFG_SDRAM_1_BASE	0x08000000 /* SDRAM bank #1 32bits    */
++#define CFG_SDRAM_1_SIZE	0x02000000 /* 32 MB                   */
++#define CFG_SDRAM_NUM_COL		9  /* 8, 9, 10 or 11 column address bits */
++#define CFG_SDRAM_NUM_ROW		12 /* 11, 12 or 13 row address bits */
++#define CFG_SDRAM_REFRESH		2  /* 0=OFF 1=2048 2=4096 3=8192 refresh */
++#define CFG_SDRAM_CLOCK_CYCLE_CL_1	20 /* ns clock cycle time when CL=1 */
++#define CFG_SDRAM_ROW_PRECHARGE_DELAY	20 /* ns SRP */
++#define CFG_SDRAM_ROW_2_COL_DELAY	20 /* ns SRCD */
++#define CFG_SDRAM_ROW_CYCLE_DELAY	70 /* ns SRC */
++#define CFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
++#define CFG_SDRAM_SINGLE_ACCESS		0  /* 1= single access; 0 = Burst mode */
++#endif
++
++#if (CFG_SDRAM_MBYTE_SYZE == 64)
++/* micron 64MB */
++#define CFG_SDRAM_1_BASE	0x08000000 /* SDRAM bank #1 32bits    */
++#define CFG_SDRAM_1_SIZE	0x04000000 /* 64 MB                   */
++#define CFG_SDRAM_NUM_COL		9  /* 8, 9, 10 or 11 column address bits */
++#define CFG_SDRAM_NUM_ROW		13 /* 11, 12 or 13 row address bits */
++#define CFG_SDRAM_REFRESH		3  /* 0=OFF 1=2048 2=4096 3=8192 refresh */
++#define CFG_SDRAM_CLOCK_CYCLE_CL_1	20 /* ns clock cycle time when CL=1 */
++#define CFG_SDRAM_ROW_PRECHARGE_DELAY	20 /* ns SRP */
++#define CFG_SDRAM_ROW_2_COL_DELAY	20 /* ns SRCD */
++#define CFG_SDRAM_ROW_CYCLE_DELAY	70 /* ns SRC */
++#define CFG_SDRAM_BURST_LENGTH		3  /* 2^N BYTES (N=0..3) */
++#define CFG_SDRAM_SINGLE_ACCESS		0  /* 1= single access; 0 = Burst mode */
++#endif
++
++/*
++ * Configuration for a maximum 32MB of FLASH memory
++ */
++#define CFG_MAX_FLASH_BANKS	1	/* FLASH banks count (not chip count) */
++#define CFG_MAX_FLASH_SECT	256	/* number of sector in FLASH bank     */
++#define CFG_FLASH_BASE		0x10000000 /* location of flash memory        */
++
++/* This should be defined if CFI FLASH device is present. */
++#define	CFG_FLASH_CFI			1
++#define CFG_FLASH_CFI_DRIVER		1
++#define CFG_FLASH_USE_BUFFER_WRITE 	1 /* use buffered writes (20x faster) */
++#define CFG_FLASH_PROTECTION		1
++
++/*
++ * This is setting for JFFS2 support in u-boot.
++ * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support.
++ */
++#define CFG_JFFS2_FIRST_BANK		0
++#define CFG_JFFS2_FIRST_SECTOR		5
++#define CFG_JFFS2_NUM_BANKS		1
++/*
++ * Environment setup. Definitions of monitor location and size with
++ * definition of environment setup ends up in 2 possibilities.
++ * 1. Embeded environment - in u-boot code is space for environment
++ * 2. Environment is read from predefined sector of flash
++ * Right now we support 2. possiblity, but expecting no env placed
++ * on mentioned address right now. This also needs to provide whole
++ * sector for it - for us 256Kb is really waste of memory. U-boot uses
++ * default env. and until kernel parameters could be sent to kernel
++ * env. has no sense to us.
++ */
++
++#define	CFG_MONITOR_BASE	0x10000000
++#define	CFG_MONITOR_LEN		0x00040000	/* 256kB ( 2 flash sector )  */
++#define	CFG_ENV_IS_IN_FLASH	1
++#define	CFG_ENV_ADDR		0x10040000	/* absolute address for now  */
++#define	CFG_ENV_SIZE		0x00020000
++#define	CFG_ENV_SECT_SIZE	0x00020000
++#define	CONFIG_ENV_OVERWRITE	1		/* env is writable now   */
++#define	CONFIG_FIRMWARE_ADDR	0x10060000
++#define	CONFIG_FIRMWARE_LEN	0x00040000	/* 256kB ( 2 flash sector )  */
++#define	CONFIG_KERNEL_ADDR	0x100A0000
++#define	CONFIG_KERNEL_LEN	0x00180000	/* 1.5MB */
++#define	CONFIG_ROOTFS_ADDR	0x10220000
++#define	CONFIG_ROOTFS_LEN	0x005E0000	/* almost 6MB */
++
++/*
++ * Default load address for user programs and kernel
++ */
++#define CFG_LOAD_ADDR		0x08000000
++#define	CONFIG_LOADADDR		0x08000000
++#define CFG_TFTP_LOADADDR	0x08000000
++/*
++ * Hardware drivers
++ */
++
++/* DM9000 ethernet chipset assigned to CS4 */
++/* For the apf board DM9000 base is 0x15C00000 and data is base+2	*/
++/* For the apm board DM9000 base is 0x15C3FFFC and data is base+4	*/
++#define CONFIG_DRIVER_DM9000	1
++#undef  CONFIG_DM9000_DEBUG
++#define CONFIG_DM9000_BASE    0x15C00000
++#define DM9000_IO		CONFIG_DM9000_BASE
++#define DM9000_DATA		(CONFIG_DM9000_BASE+2)
++#define CONFIG_DM9000_USE_16BIT
++
++/*-----------------------------------------------------------------------
++ * FPGA stuff
++ */
++#define CONFIG_FPGA_COUNT	1
++/* only digital value for CONFIG_FPGA is supported (investigation pending)    */
++#define CONFIG_FPGA		0x801		/* CFG_XILINX_SPARTAN3 */
++#define CFG_FPGA_WAIT		250
++#define CFG_FPGA_PROG_FEEDBACK
++#define CFG_FPGA_CHECK_CTRLC
++#define CFG_FPGA_CHECK_ERROR
++/* FPGA program pin configuration */
++#define CFG_FPGA_PRG	(GPIO_PORTB | 18)	/* FPGA prog pin (SSI output) */
++#define CFG_FPGA_CLK	(GPIO_PORTB | 19)	/* FPGA clk pin  (SSI output) */
++#define CFG_FPGA_DATA	(GPIO_PORTB | 17)	/* FPGA data pin (SSI output) */
++#define CFG_FPGA_INIT	(GPIO_PORTB | 15)	/* FPGA init pin (SSI input)  */
++#define CFG_FPGA_DONE	(GPIO_PORTB | 16)	/* FPGA done pin (SSI input)  */
++
++/*
++ * I2C bus
++ */
++
++#define	CONFIG_HARD_I2C		1	/* I2C with hardware support    */
++
++#define CFG_I2C_SPEED		400000	/* 400 kHz */
++#define CFG_I2C_SLAVE		0x7F
++
++# define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM 24LC256               */
++# define CFG_I2C_EEPROM_ADDR_LEN 2	/* bytes of address             */
++/* mask of address bits that overflow into the "EEPROM chip address"    */
++/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x00*/
++#define CFG_EEPROM_PAGE_WRITE_BITS	6
++#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec */
++
++#define CONFIG_RTC_DS1374
++
++/*
++ * External interfaces module
++ *
++ * CSxU_VAL:
++ * 63|    x    |x|x x|x x x x|x x| x | x  |x x x x|48
++ *   |DTACK_SEL|0|BCD|  BCS  |PSZ|PME|SYNC|  DOL  |
++ *
++ * 47| x x  | x x x x x x | x | x x x x | x x x x |32
++ *   | CNC  |     WSC     | 0 |   WWS   |   EDC   |
++ *
++ * CSxL_VAL:
++ * 31|  x x x x  | x x x x  | x x x x  | x x x x  |24
++ *   |    OEA    |   OEN    |   WEA    |   WEN    |
++ * 23|x x x x| x | x x x | x x  x x |x x| x |  x  | 0
++ *   |  CSA  |EBC|  DSZ  | 0|SP|0|WP|0 0|PA |CSEN |
++ */
++
++/* CS0 configuration for  flash memory Micron MT28F128J3-150 */
++#define CFG_CS0_CHIP_SELECT_ENABLE	1	/* 1 : enable CS0 peripherals */
++#define CFG_CS0_DATA_PORT_SIZE		0x5	/* 5=16 bits on D[15:0] pins  */
++						/* 3=8bits on D[7:0] 6=32 bits..*/
++#define CFG_CS0_SUPERVISOR_PROTECT	0   /* 1 : user mode access prohibited  */
++#define CFG_CS0_WRITE_PROTECT		0   /* 1 : write access prohibited  */
++#define CFG_CS0_EB_SIGNAL_CONTROL_WRITE	1   /* 1 when EB is used as write signal */
++#define CFG_CS0_READ_CYC_LGTH		150	/* ns */
++#define CFG_CS0_OE_ASSERT_DLY		0	/* ns */
++#define CFG_CS0_OE_NEG_DLY		0	/* ns */
++
++#define CFG_CS0_CS_NEG_LGTH 	0	/* ns CS HIGH to CS LOW : tCWH */
++#define CFG_CS0_XTRA_DEAD_CYC	35	/* ns from CS HIGH to tristate bus */
++
++#define CFG_CS0_WRITE_XTRA_LGTH		0	/* ns */
++#define CFG_CS0_EB_ASSERT_DLY		0	/* ns */
++#define CFG_CS0_EB_NEG_DLY		0	/* ns */
++#define CFG_CS0_CS_ASSERT_NEG_DLY	0	/* ns */
++
++#define CFG_CS0_SYNC_ENABLE		1	/* enable synchronous burst mode */
++#define CFG_CS0_SYNC_PAGE_MODE_EMUL	1	/* enable page mode emulation */
++#define CFG_CS0_SYNC_PAGE_SIZE		0	/* 4 words page size (8bytes) */
++#define CFG_CS0_SYNC_BURST_CLK_START	0	/* 0 ns burst clock delay */
++#define CFG_CS0_SYNC_BURST_CLK_DIV	0	/* 0 : divider is 1 */
++#define CFG_CS0_SYNC_DAT_OUT_LGTH	25	/* ns */
++
++/* CS1 configuration for  */
++#define CFG_CS1_CHIP_SELECT_ENABLE	1	/* 1 : enable CS0 peripherals  */
++#define CFG_CS1_PIN_ASSERT		0	/* chip select pin state when */
++						/* chip select disabled  */
++#define CFG_CS1_DATA_PORT_SIZE		0x5	/* 5=16 bits on D[15:0] pins*/
++						/* 3=8bits on D[7:0] 6=32 bits..*/ 
++#define CFG_CS1_SUPERVISOR_PROTECT	0	/* 1 : user mode access prohibited  */
++#define CFG_CS1_WRITE_PROTECT		0	/* 1 : write access prohibited  */
++#define CFG_CS1_EB_SIGNAL_CONTROL_WRITE	1	/* 1 when EB is used as write signal */
++
++#define CFG_CS1_READ_CYC_LGTH		30	/* ns */
++#define CFG_CS1_OE_ASSERT_DLY		0	/* ns */
++#define CFG_CS1_OE_NEG_DLY		0	/* ns */
++
++#define CFG_CS1_CS_NEG_LGTH 	0	/* max 30 ns CS HIGH to CS LOW at 100MHz */
++#define CFG_CS1_XTRA_DEAD_CYC	0	/* ns from CS HIGH to tristate bus */
++
++#define CFG_CS1_WRITE_XTRA_LGTH		0	/* ns */
++#define CFG_CS1_EB_ASSERT_DLY		0	/* ns */
++#define CFG_CS1_EB_NEG_DLY		0	/* ns */
++#define CFG_CS1_CS_ASSERT_NEG_DLY	0	/* ns */
++
++#define CFG_CS1_SYNC_ENABLE		0	/* enable synchronous burst mode */
++#define CFG_CS1_SYNC_PAGE_MODE_EMUL	0	/* enable page mode emulation */
++#define CFG_CS1_SYNC_PAGE_SIZE		0	/* 4 words page size (8bytes) */
++#define CFG_CS1_SYNC_BURST_CLK_START	0	/* 0 ns burst clock delay */
++#define CFG_CS1_SYNC_BURST_CLK_DIV	0	/* 0 : divider is 1 */
++#define CFG_CS1_SYNC_DAT_OUT_LGTH	0	/* ns */
++
++/* CS2 configuration for  */
++#define CFG_CS2_CHIP_SELECT_ENABLE	0	/* 1 : enable CS0 peripherals  */
++#define CFG_CS2_PIN_ASSERT		0	/* chip select pin state when */
++						/*chip select disabled  */
++#define CFG_CS2_DATA_PORT_SIZE		0x5	/* 5=16 bits on D[15:0] pins */
++						/* 3=8bits on D[7:0] 6=32 bits..*/
++#define CFG_CS2_SUPERVISOR_PROTECT	0	/* 1 : user mode access prohibited  */
++#define CFG_CS2_WRITE_PROTECT		0	/* 1 : write access prohibited  */
++#define CFG_CS2_EB_SIGNAL_CONTROL_WRITE	1	/* 1 when EB is used as write signal */
++
++#define CFG_CS2_READ_CYC_LGTH		0	/* ns */
++#define CFG_CS2_OE_ASSERT_DLY		0	/* ns */
++#define CFG_CS2_OE_NEG_DLY		0	/* ns */
++
++#define CFG_CS2_CS_NEG_LGTH 	0	/* max 30 ns CS HIGH to CS LOW at 100MHz */
++#define CFG_CS2_XTRA_DEAD_CYC	0	/* ns from CS HIGH to tristate bus */
++
++#define CFG_CS2_WRITE_XTRA_LGTH		0	/* ns */
++#define CFG_CS2_EB_ASSERT_DLY		0	/* ns */
++#define CFG_CS2_EB_NEG_DLY		0	/* ns */
++#define CFG_CS2_CS_ASSERT_NEG_DLY	0	/* ns */
++
++#define CFG_CS2_SYNC_ENABLE		0	/* enable synchronous burst mode */
++#define CFG_CS2_SYNC_PAGE_MODE_EMUL	0	/* enable page mode emulation*/
++#define CFG_CS2_SYNC_PAGE_SIZE		0	/* 4 words page size (8bytes) */
++#define CFG_CS2_SYNC_BURST_CLK_START	0	/* 0 ns burst clock delay */
++#define CFG_CS2_SYNC_BURST_CLK_DIV	0	/* 0 : divider is 1 */
++#define CFG_CS2_SYNC_DAT_OUT_LGTH	0	/* ns */
++
++/* CS3 configuration for  */
++#define CFG_CS3_CHIP_SELECT_ENABLE	1	/* 1 : enable CS0 peripherals  */
++#define CFG_CS3_PIN_ASSERT		0	/* chip select pin state when */
++						/* chip select disabled  */
++#define CFG_CS3_DATA_PORT_SIZE		0x5	/* 5=16 bits on D[15:0] pins */
++						/* 3=8bits on D[7:0] 6=32 bits..*/
++#define CFG_CS3_SUPERVISOR_PROTECT	0	/* 1: user mode access prohibited*/
++#define CFG_CS3_WRITE_PROTECT		0	/* 1: write access prohibited  */
++#define CFG_CS3_EB_SIGNAL_CONTROL_WRITE	1	/* 1 when EB is used as write signal*/
++
++#define CFG_CS3_READ_CYC_LGTH		0	/* ns */
++#define CFG_CS3_OE_ASSERT_DLY		0	/* ns */
++#define CFG_CS3_OE_NEG_DLY		0	/* ns */
++
++#define CFG_CS3_CS_NEG_LGTH 	0	/* max 30 ns CS HIGH to CS LOW at 100MHz */
++#define CFG_CS3_XTRA_DEAD_CYC	0	/* ns from CS HIGH to tristate bus */
++
++#define CFG_CS3_WRITE_XTRA_LGTH		0	/* ns */
++#define CFG_CS3_EB_ASSERT_DLY		0	/* ns */
++#define CFG_CS3_EB_NEG_DLY		0	/* ns */
++#define CFG_CS3_CS_ASSERT_NEG_DLY	0	/* ns */
++
++#define CFG_CS3_SYNC_ENABLE		0	/* enable synchronous burst mode*/
++#define CFG_CS3_SYNC_PAGE_MODE_EMUL	0	/* enable page mode emulation*/
++#define CFG_CS3_SYNC_PAGE_SIZE		0	/* 4 words page size (8bytes) */
++#define CFG_CS3_SYNC_BURST_CLK_START	0	/* 0 ns burst clock delay */
++#define CFG_CS3_SYNC_BURST_CLK_DIV	0	/* 0 : divider is 1 */
++#define CFG_CS3_SYNC_DAT_OUT_...
 
[truncated message content]

[Armadeus-commitlog] SF.net SVN: armadeus: [820] trunk/buildroot/package/fbgrab/fbgrab-1.0.patch

From: <ar...@us...> - 2008-06-06 21:33:08

Revision: 820
          http://armadeus.svn.sourceforge.net/armadeus/?rev=820&view=rev
Author:   artemys
Date:     2008-06-06 14:33:08 -0700 (Fri, 06 Jun 2008)

Log Message:
-----------
[BUILDROOT] Makes fbgrab package compilation produce a working executable

Modified Paths:
--------------
    trunk/buildroot/package/fbgrab/fbgrab-1.0.patch

Modified: trunk/buildroot/package/fbgrab/fbgrab-1.0.patch
===================================================================
--- trunk/buildroot/package/fbgrab/fbgrab-1.0.patch	2008-06-05 15:01:47 UTC (rev 819)
+++ trunk/buildroot/package/fbgrab/fbgrab-1.0.patch	2008-06-06 21:33:08 UTC (rev 820)
@@ -1,20 +1,21 @@
---- fbgrab-1.0.org/Makefile	2008-05-15 14:30:23.000000000 +0200
-+++ fbgrab-1.0/Makefile	2008-05-15 14:31:25.000000000 +0200
-@@ -4,13 +4,8 @@
+diff -urN fbgrab-1.0/Makefile fbgrab-1.0.mod/Makefile
+--- fbgrab-1.0/Makefile	2002-03-20 20:49:06.000000000 +0100
++++ fbgrab-1.0.mod/Makefile	2008-06-06 21:42:56.000000000 +0200
+@@ -4,8 +4,8 @@
  ###
  
  fbgrab: fbgrab.c
 -	splint +posixlib fbgrab.c
 -	gcc -g -Wall fbgrab.c -lpng -lz -o fbgrab
--
--install:
--	strip fbgrab
--	install fbgrab /usr/bin/fbgrab
--	install fbgrab.1.man /usr/man/man1/fbgrab.1
-+	$(CC) -c $(CFLAGS) $(INCLUDES) -o fbgrab fbgrab.c
++	#splint +posixlib fbgrab.c
++	$(CC) -Wall fbgrab.c -lpng -lz -o fbgrab
  
+ install:
+ 	strip fbgrab
+@@ -13,4 +13,4 @@
+ 	install fbgrab.1.man /usr/man/man1/fbgrab.1
+ 
  clean:
 -	rm -f fbgrab *~ \#*\#
-\ No newline at end of file
+\ Pas de fin de ligne à la fin du fichier.
 +	rm -f fbgrab *~ \#*\#
-+


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[Armadeus-commitlog] SF.net SVN: armadeus: [819] trunk/target/linux/modules/backlight/imx_bl_2.6 .23.c

From: <th...@us...> - 2008-06-05 15:01:59

Revision: 819
          http://armadeus.svn.sourceforge.net/armadeus/?rev=819&view=rev
Author:   thom25
Date:     2008-06-05 08:01:47 -0700 (Thu, 05 Jun 2008)

Log Message:
-----------
[LINUX] fix build error when PM is activated

Modified Paths:
--------------
    trunk/target/linux/modules/backlight/imx_bl_2.6.23.c

Modified: trunk/target/linux/modules/backlight/imx_bl_2.6.23.c
===================================================================
--- trunk/target/linux/modules/backlight/imx_bl_2.6.23.c	2008-06-02 15:48:28 UTC (rev 818)
+++ trunk/target/linux/modules/backlight/imx_bl_2.6.23.c	2008-06-05 15:01:47 UTC (rev 819)
@@ -65,7 +65,7 @@
 #ifdef CONFIG_PM
 static int imxbl_suspend(struct platform_device *dev, pm_message_t state)
 {
-	struct backlight_device *bd = platform_get_drvdata(pdev);
+	struct backlight_device *bd = platform_get_drvdata(dev);
 
 	imxbl_flags |= IMXBL_SUSPENDED;
 	backlight_update_status(bd);
@@ -74,7 +74,7 @@
 
 static int imxbl_resume(struct platform_device *dev)
 {
-	struct backlight_device *bd = platform_get_drvdata(pdev);
+	struct backlight_device *bd = platform_get_drvdata(dev);
 
 	imxbl_flags &= ~IMXBL_SUSPENDED;
 	backlight_update_status(bd);


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[Armadeus-commitlog] SF.net SVN: armadeus: [818] trunk/target/linux/modules/isp1761/hal/hal_imx. c

From: <th...@us...> - 2008-06-02 15:48:22

Revision: 818
          http://armadeus.svn.sourceforge.net/armadeus/?rev=818&view=rev
Author:   thom25
Date:     2008-06-02 08:48:28 -0700 (Mon, 02 Jun 2008)

Log Message:
-----------
[LINUX] Fix bug 1960067: ISP1761 scratch register

Modified Paths:
--------------
    trunk/target/linux/modules/isp1761/hal/hal_imx.c

Modified: trunk/target/linux/modules/isp1761/hal/hal_imx.c
===================================================================
--- trunk/target/linux/modules/isp1761/hal/hal_imx.c	2008-06-02 15:24:26 UTC (rev 817)
+++ trunk/target/linux/modules/isp1761/hal/hal_imx.c	2008-06-02 15:48:28 UTC (rev 818)
@@ -834,15 +834,18 @@
 #endif
 
     loc_dev = &(isp1761_loc_dev[ISP1761_HC]);
-    isp1761_reg_write16(loc_dev, HC_SCRATCH_REG, 0xFACE);
-    udelay(100);
+    isp1761_reg_write16(loc_dev, HC_SCRATCH_REG, 0xFACE);
+    /* perform a read of the chip ID to avoir bus hold effect when
+    * reading back the scratch register */
+    isp1761_reg_read16(loc_dev, HC_CHIP_ID_REG, reg_data);
+    udelay(100); 
     reg_data = isp1761_reg_read16(loc_dev, HC_SCRATCH_REG,reg_data);
 
     /* Host Controller presence is detected by writing to scratch register
      * and reading back and checking the contents are same or not
      */
     if(reg_data != 0xFACE) {
-        err("%s scratch register mismatch %x",
+        err("%s scratch register mismatch %x. Unable to find the ISP176x device",
                 isp1761_driver_name,reg_data);
         status = -ENODEV;
         goto clean;


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[Armadeus-commitlog] SF.net SVN: armadeus: [817] trunk/buildroot/target/device/armadeus/linux/ kernel-patches

From: <th...@us...> - 2008-06-02 15:24:27

Revision: 817
          http://armadeus.svn.sourceforge.net/armadeus/?rev=817&view=rev
Author:   thom25
Date:     2008-06-02 08:24:26 -0700 (Mon, 02 Jun 2008)

Log Message:
-----------
[LINUX] change UART/DM9000 irq trig method from level to edge. (adeos compatibility)

Modified Paths:
--------------
    trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff
    trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.24.3/021-linux-2.6.24.3-apf9328.diff

Modified: trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff
===================================================================
--- trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff	2008-06-02 15:09:07 UTC (rev 816)
+++ trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/021-linux-2.6.23.1-apf9328.diff	2008-06-02 15:24:26 UTC (rev 817)
@@ -1323,9 +1323,9 @@
 +    // Init generic IRQs
 +    imx_init_irq();
 +    // Init our custom IRQs
-+    set_irq_type(APF9328_UART1_IRQ, IRQF_TRIGGER_LOW);
++    set_irq_type(APF9328_UART1_IRQ, IRQF_TRIGGER_FALLING);
 +#ifdef CONFIG_DM9000
-+    set_irq_type(APF9328_ETH_IRQ, IRQF_TRIGGER_LOW);
++    set_irq_type(APF9328_ETH_IRQ, IRQF_TRIGGER_FALLING);
 +#endif // CONFIG_DM9000
 +#ifdef CONFIG_SPI_TSC2102
 +    set_irq_type( IRQ_GPIOD(TSC2102_INT_GPIOD), IRQF_TRIGGER_FALLING );

Modified: trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.24.3/021-linux-2.6.24.3-apf9328.diff
===================================================================
--- trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.24.3/021-linux-2.6.24.3-apf9328.diff	2008-06-02 15:09:07 UTC (rev 816)
+++ trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.24.3/021-linux-2.6.24.3-apf9328.diff	2008-06-02 15:24:26 UTC (rev 817)
@@ -505,9 +505,9 @@
 +    // Init generic IRQs
 +    imx_init_irq();
 +    // Init our custom IRQs
-+    set_irq_type(APF9328_UART1_IRQ, IRQF_TRIGGER_LOW);
++    set_irq_type(APF9328_UART1_IRQ, IRQF_TRIGGER_FALLING);
 +#ifdef CONFIG_DM9000
-+    set_irq_type(APF9328_ETH_IRQ, IRQF_TRIGGER_LOW);
++    set_irq_type(APF9328_ETH_IRQ, IRQF_TRIGGER_FALLING);
 +#endif // CONFIG_DM9000
 +#ifdef CONFIG_SPI_TSC2102
 +    set_irq_type( IRQ_GPIOD(8), IRQF_TRIGGER_FALLING );


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[Armadeus-commitlog] SF.net SVN: armadeus: [816] trunk/buildroot/target/device/armadeus/linux/ kernel-patches

From: <th...@us...> - 2008-06-02 15:09:07

Revision: 816
          http://armadeus.svn.sourceforge.net/armadeus/?rev=816&view=rev
Author:   thom25
Date:     2008-06-02 08:09:07 -0700 (Mon, 02 Jun 2008)

Log Message:
-----------
[LINUX] fix error when writing on an ext2 SD/MMC

Modified Paths:
--------------
    trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/040-linux-2.6.23.1-imx_mmc.diff
    trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.24.3/040-linux-2.6.24.3-imx_mmc.diff

Modified: trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/040-linux-2.6.23.1-imx_mmc.diff
===================================================================
--- trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/040-linux-2.6.23.1-imx_mmc.diff	2008-06-01 14:40:55 UTC (rev 815)
+++ trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.23.1/040-linux-2.6.23.1-imx_mmc.diff	2008-06-02 15:09:07 UTC (rev 816)
@@ -83,3 +83,17 @@
  			loops, where, *pstat, stat_mask);
  	return loops;
  }
+--- linux-org/drivers/mmc/host/imxmmc.c	2008-06-02 04:25:41.000000000 +0200
++++ linux-imx/drivers/mmc/host/imxmmc.c	2008-06-02 04:22:21.000000000 +0200
+@@ -336,6 +336,12 @@ static void imxmci_start_cmd(struct imxm
+ 	/* Ensure, that clock are stopped else command programming and start fails */
+ 	imxmci_stop_clock(host);
+ 
++	/*force check of busy bit DO after CMD25 + CMD12 
++		to avoid hang up of the controler */
++	if( cmd->opcode == 13){
++		cmdat |= CMD_DAT_CONT_BUSY; 
++	}
++
+ 	if (cmd->flags & MMC_RSP_BUSY)
+ 		cmdat |= CMD_DAT_CONT_BUSY;

Modified: trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.24.3/040-linux-2.6.24.3-imx_mmc.diff
===================================================================
--- trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.24.3/040-linux-2.6.24.3-imx_mmc.diff	2008-06-01 14:40:55 UTC (rev 815)
+++ trunk/buildroot/target/device/armadeus/linux/kernel-patches/2.6.24.3/040-linux-2.6.24.3-imx_mmc.diff	2008-06-02 15:09:07 UTC (rev 816)
@@ -72,4 +72,28 @@
  #define PB11_AF_MS_SDIO      ( GPIO_PORTB | GPIO_AF | 11 )
  #define PB12_PF_SD_CLK       ( GPIO_PORTB | GPIO_PF | 12 )
  #define PB12_AF_MS_SCLK0     ( GPIO_PORTB | GPIO_AF | 12 )
-
+--- linux-org/drivers/mmc/host/imxmmc.c	2008-01-28 17:36:24.000000000 +0100
++++ linux-imx/drivers/mmc/host/imxmmc.c	2008-01-28 17:36:47.000000000 +0100
+@@ -220,7 +220,7 @@ static int imxmci_busy_wait_for_status(s
+ 
+ 	/* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
+ 	if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
+-		dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
++		dev_dbg(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
+ 			loops, where, *pstat, stat_mask);
+ 	return loops;
+ }
+--- linux-org/drivers/mmc/host/imxmmc.c	2008-06-02 04:25:41.000000000 +0200
++++ linux-imx/drivers/mmc/host/imxmmc.c	2008-06-02 04:22:21.000000000 +0200
+@@ -336,6 +336,12 @@ static void imxmci_start_cmd(struct imxm
+ 	/* Ensure, that clock are stopped else command programming and start fails */
+ 	imxmci_stop_clock(host);
+ 
++	/*force check of busy bit DO after CMD25 + CMD12 
++		to avoid hang up of the controler */
++	if( cmd->opcode == 13){
++		cmdat |= CMD_DAT_CONT_BUSY; 
++	}
++
+ 	if (cmd->flags & MMC_RSP_BUSY)
+ 		cmdat |= CMD_DAT_CONT_BUSY;


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[Armadeus-commitlog] SF.net SVN: armadeus: [815] trunk/target/linux/modules/imxlkeypad

From: <ar...@us...> - 2008-06-01 14:40:47

Revision: 815
          http://armadeus.svn.sourceforge.net/armadeus/?rev=815&view=rev
Author:   artemys
Date:     2008-06-01 07:40:55 -0700 (Sun, 01 Jun 2008)

Log Message:
-----------
[LINUX] Now keycodes can be passed as insmod/modprobe parameters to imxkeypad driver

Modified Paths:
--------------
    trunk/target/linux/modules/imxlkeypad/Makefile
    trunk/target/linux/modules/imxlkeypad/imxkeypad.c

Modified: trunk/target/linux/modules/imxlkeypad/Makefile
===================================================================
--- trunk/target/linux/modules/imxlkeypad/Makefile	2008-06-01 09:43:34 UTC (rev 814)
+++ trunk/target/linux/modules/imxlkeypad/Makefile	2008-06-01 14:40:55 UTC (rev 815)
@@ -14,7 +14,8 @@
 BASE_DIR="../../../../buildroot/"
 REL=`grep "BR2_PACKAGE_LINUX_VERSION=" $(BASE_DIR).config | \
       sed "s/BR2_PACKAGE_LINUX_VERSION=\\"//" | sed "s/\\"//"`
-ARMADEUS_KERNEL_DIR=$(BASE_DIR)build_arm_nofpu/linux-$(REL)
+BUILD_ARM=`ls ../../../../buildroot | grep "^build_arm"`
+ARMADEUS_KERNEL_DIR=$(BASE_DIR)/$(BUILD_ARM)/linux-$(REL)
 KDIR    := $(ARMADEUS_KERNEL_DIR)
 PWD	:= $(shell pwd)
 
@@ -22,6 +23,7 @@
 	$(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules
 
 clean:
+	rm -f .*.cmd
 	rm -f *.*o
 	rm -f Module.symvers
     

Modified: trunk/target/linux/modules/imxlkeypad/imxkeypad.c
===================================================================
--- trunk/target/linux/modules/imxlkeypad/imxkeypad.c	2008-06-01 09:43:34 UTC (rev 814)
+++ trunk/target/linux/modules/imxlkeypad/imxkeypad.c	2008-06-01 14:40:55 UTC (rev 815)
@@ -32,7 +32,6 @@
 #include <linux/moduleparam.h>
 #include <linux/init.h>
 #include <linux/input.h>
-#include <linux/ioport.h>
 #include <linux/delay.h>
 #include <linux/device.h>
 #include <linux/interrupt.h>
@@ -44,7 +43,7 @@
 #include <asm/irq.h>
 
 MODULE_AUTHOR("Eric Jarrige");
-MODULE_DESCRIPTION("IMX keypad driver");
+MODULE_DESCRIPTION("i.MXL keypad driver");
 MODULE_LICENSE("GPL");
 
 #define DEBUG
@@ -58,15 +57,15 @@
 #define KB_DELAY		8	/* uS */
 #define SCAN_INTERVAL		(HZ/10)
 
-static unsigned char imxkeypad_keycode[KPD_MAX_ROWS * KPD_MAX_COLS] = {
-	KEY_LEFT, KEY_RIGHT, KEY_ENTER, KEY_ESC,	/* 0 - 3 */
-	KEY_3, KEY_6, KEY_9, KEY_SPACE,			/* 4 - 7 */
-	KEY_2, KEY_5, KEY_8, KEY_0,			/* 8 - 11 */
-	KEY_1, KEY_4, KEY_7, KEY_KPASTERISK		/* 12 - 15 */
+static unsigned short imxkeypad_keycode[KPD_MAX_ROWS * KPD_MAX_COLS] = {
+	KEY_LEFT, KEY_RIGHT, KEY_ENTER, KEY_ESC,       /* 0 - 3 */
+	KEY_3,    KEY_6,     KEY_9,     KEY_SPACE,     /* 4 - 7 */
+	KEY_2,    KEY_5,     KEY_8,     KEY_0,         /* 8 - 11 */
+	KEY_1,    KEY_4,     KEY_7,     KEY_KPASTERISK /* 12 - 15 */
 };
 
 struct imxkeypad {
-	unsigned char keycode[KPD_MAX_ROWS * KPD_MAX_COLS];
+	unsigned short keycode[KPD_MAX_ROWS * KPD_MAX_COLS];
 	struct input_dev *input;
 	char phys[32];
 
@@ -96,6 +95,9 @@
 module_param_array(bit_offset, long, NULL, 0000);
 MODULE_PARM_DESC(bit_offset, "rows and cols bits offset in registers");
 
+module_param_array(imxkeypad_keycode, short, NULL, 0000); // imxkeypad_keycode declared line 60
+MODULE_PARM_DESC(imxkeypad_keycode, "rows and cols bits offset in registers");
+
 /* helper functions for reading the keyboard matrix */
 static inline void imxkeypad_charge_all(struct imxkeypad *kpdPtr)
 {
@@ -212,7 +214,7 @@
 
 static int __init imxkeypad_init(void)
 {
-	int i, ret;
+	int i, j, ret;
 
 	printk(KERN_INFO "Initializing Armadeus keypad driver\n");
 
@@ -233,7 +235,7 @@
 	imxkeypad.input->evbit[0] = BIT(EV_KEY) | BIT(EV_REP);
 	
 	imxkeypad.input->keycode = imxkeypad.keycode;
-	imxkeypad.input->keycodesize = sizeof(unsigned char);
+	imxkeypad.input->keycodesize = sizeof(unsigned short);
 	imxkeypad.input->keycodemax = ARRAY_SIZE(imxkeypad_keycode);
 	imxkeypad.input->private = &imxkeypad;
 


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[Armadeus-commitlog] SF.net SVN: armadeus: [814] trunk/target/demos/backlight_control

From: <ar...@us...> - 2008-06-01 09:43:33

Revision: 814
          http://armadeus.svn.sourceforge.net/armadeus/?rev=814&view=rev
Author:   artemys
Date:     2008-06-01 02:43:34 -0700 (Sun, 01 Jun 2008)

Log Message:
-----------
[DEMOS] Improve backlight tool (compiling and running on target

Modified Paths:
--------------
    trunk/target/demos/backlight_control/Makefile
    trunk/target/demos/backlight_control/README
    trunk/target/demos/backlight_control/backlight.c
    trunk/target/demos/backlight_control/backlight_sysctl.c
    trunk/target/demos/backlight_control/backlight_sysctl.h

Added Paths:
-----------
    trunk/target/demos/backlight_control/data/
    trunk/target/demos/backlight_control/data/cursor.bmp
    trunk/target/demos/backlight_control/data/empty.bmp
    trunk/target/demos/backlight_control/data/empty_end.bmp
    trunk/target/demos/backlight_control/data/full.bmp
    trunk/target/demos/backlight_control/data/full_end.bmp

Removed Paths:
-------------
    trunk/target/demos/backlight_control/cursor.bmp
    trunk/target/demos/backlight_control/empty.bmp
    trunk/target/demos/backlight_control/empty_end.bmp
    trunk/target/demos/backlight_control/full.bmp
    trunk/target/demos/backlight_control/full_end.bmp

Modified: trunk/target/demos/backlight_control/Makefile
===================================================================
--- trunk/target/demos/backlight_control/Makefile	2008-05-31 09:38:57 UTC (rev 813)
+++ trunk/target/demos/backlight_control/Makefile	2008-06-01 09:43:34 UTC (rev 814)
@@ -7,20 +7,22 @@
 	SDL_DIR:=$(BUILD_DIR)/SDL-1.2.11/
 	STAGING_DIR:=$(BUILD_DIR)/staging_dir/
 	ROOT_DIR:=$(BUILDROOT_DIR)/project_$(BUILD_DIR_EXT)/armadeus/root/
-        INSTALL_DIR:=$(ROOT_DIR)/usr/bin/
 
 	CC:=$(STAGING_DIR)/bin/arm-linux-gcc
 	DEFINES="TARGET"
 	CFLAGS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --cflags)
 	LIBS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --libs)
 else
-	INSTALL_DIR="./install"
+	ROOT_DIR:="/"
 	CFLAGS=`/usr/bin/sdl-config --cflags`
 	LIBS=`/usr/bin/sdl-config --libs`
 	CC=gcc
 	DEFINES="HOST"
 endif
 
+INSTALL_DIR:=$(ROOT_DIR)/usr/bin/
+INSTALL_DIR_DATA:=$(ROOT_DIR)/usr/share/apps/backlight/data
+
 CFLAGS+="-g"
 
 default: backlight
@@ -37,10 +39,16 @@
 backlight: backlight.o backlight_sysctl.o
 	$(CC)  $(LIBS) -o $@ $^
 
-install: backlight cursor.bmp empty.bmp empty_end.bmp full.bmp full_end.bmp
+install: install_tool install_data
+
+install_tool: backlight
 	mkdir -p $(INSTALL_DIR)
 	cp $^  $(INSTALL_DIR)
 
+install_data: data/cursor.bmp data/empty.bmp data/empty_end.bmp data/full.bmp data/full_end.bmp
+	mkdir -p $(INSTALL_DIR_DATA)
+	cp $^  $(INSTALL_DIR_DATA)
+
 clean: 
 	rm -rf backlight
 	rm -rf *.o

Modified: trunk/target/demos/backlight_control/README
===================================================================
--- trunk/target/demos/backlight_control/README	2008-05-31 09:38:57 UTC (rev 813)
+++ trunk/target/demos/backlight_control/README	2008-06-01 09:43:34 UTC (rev 814)
@@ -2,5 +2,5 @@
 * ARM compiling:
  $ make clean; make install
 * x86 compiling (SDL devt package should be installed on your system)
- $ make TARGET=x86 clean; make TARGET=x86
+ $ make TARGET=x86 clean; make TARGET=x86; sudo make TARGET=x86 install_data
 

Modified: trunk/target/demos/backlight_control/backlight.c
===================================================================
--- trunk/target/demos/backlight_control/backlight.c	2008-05-31 09:38:57 UTC (rev 813)
+++ trunk/target/demos/backlight_control/backlight.c	2008-06-01 09:43:34 UTC (rev 814)
@@ -1,5 +1,4 @@
 /*
- *
  * Small tool to demonstrate how to use (or not use ;-) ) Tslib + SDL library
  *   for the Armadeus project. www.armadeus.og
  *
@@ -23,7 +22,6 @@
 #include <unistd.h> // for sleep()
 
 #include "SDL.h"
-// To 
 #include "backlight_sysctl.h"
 
 
@@ -44,6 +42,8 @@
 #define false 0
 #define true  1
 
+#define DEFAULT_DATA_DIR "/usr/share/apps/backlight/data/"
+
 SDL_Surface *cursor;
 SDL_Surface *full_end;
 SDL_Surface *full;
@@ -61,11 +61,11 @@
 {
     int result = 0;
 
-    full_end = SDL_LoadBMP("./full_end.bmp");
-    full = SDL_LoadBMP("./full.bmp");
-    cursor = SDL_LoadBMP("./cursor.bmp");
-    empty = SDL_LoadBMP("./empty.bmp");
-    empty_end = SDL_LoadBMP("./empty_end.bmp");
+    full_end  = SDL_LoadBMP( DEFAULT_DATA_DIR "full_end.bmp" );
+    full      = SDL_LoadBMP( DEFAULT_DATA_DIR "full.bmp" );
+    cursor    = SDL_LoadBMP( DEFAULT_DATA_DIR "cursor.bmp" );
+    empty     = SDL_LoadBMP( DEFAULT_DATA_DIR "empty.bmp" );
+    empty_end = SDL_LoadBMP( DEFAULT_DATA_DIR "empty_end.bmp" );
 
     // Check if we got all images
     if( full_end == NULL || full == NULL || cursor == NULL || empty == NULL || empty_end == NULL )
@@ -83,7 +83,7 @@
     return(result);
 }
 
-// 
+//
 static void freeRessources()
 {
     SDL_FreeSurface( screen );
@@ -171,7 +171,7 @@
     int x=0;
 
     x = paddXPos( xpos );
-    drawImage( cursor, x, BAR_YPOSITION-5);    
+    drawImage( cursor, x, BAR_YPOSITION-5 );
 }
 
 //
@@ -183,6 +183,13 @@
     SDL_Flip( screen );
 }
 
+void cleanup( void )
+{
+    // Cleanup what we used
+    releaseBacklightControl();
+    freeRessources();
+    SDL_Quit();
+}
 
 //---- Main ----
 
@@ -190,34 +197,22 @@
 int main(int argc, char *argv[])
 {
     Uint8* keys;
-    int nbFrames = 0;
     int cursorPos = 0;
-    //Timer fps, update;
-    //Sint8 xspeed = 1, yspeed =1;
 
     // Initialize SDL
     if( SDL_Init( SDL_INIT_VIDEO | SDL_INIT_TIMER /*| SDL_INIT_EVENTTHREAD |SDL_INIT_NOPARACHUTE*/) < 0 )
     {
-        printf("Unable to init SDL: %s\n", SDL_GetError());
+        fprintf(stderr, "Unable to init SDL: %s\n", SDL_GetError());
         exit(1);
     }
-    if (SDL_InitSubSystem(SDL_INIT_TIMER) == -1)
-    {
-        fprintf(stderr, "SDL timer failed to initialize! Error: %s\n", SDL_GetError());
-        exit(1);
-    }
-    else
-    {
-        fprintf(stdout, "SDL timer initialized properly!\n");
-    }
     // Ask SDL to cleanup when exiting
-    atexit(SDL_Quit);
+    atexit(cleanup);
 
     // Get a screen to display our game
     screen=SDL_SetVideoMode( SCREEN_WIDTH, SCREEN_HEIGHT, 16, 0/*SDL_HWPALETTE*//*SDL_HWSURFACE|| SDL_DOUBLEBUF*/ );
     if( screen == NULL )
     {
-        printf("Unable to set %dx%dvideo mode: %s\n", SCREEN_WIDTH, SCREEN_HEIGHT, SDL_GetError());
+        fprintf(stderr, "Unable to set %dx%dvideo mode: %s\n", SCREEN_WIDTH, SCREEN_HEIGHT, SDL_GetError());
         exit(1);
     }
 
@@ -233,16 +228,12 @@
     {
         printf("Unable to find Backlight control on your system -> won't be activated\n");
     }
-    updateCursor( (getBacklight() * BAR_WIDTH / 100) + BAR_MIN_XPOSITION );
+    updateCursor( (getBrightness() * BAR_WIDTH / 100) + BAR_MIN_XPOSITION );
     int done=0, move=0;
 
     // Hide mouse
     SDL_ShowCursor(0);
 
-    /* // Start timer for Frame Rate calculation
-    update.start();
-    fps.start();*/
-
     // Main loop
     while(done == 0)
     {
@@ -280,36 +271,15 @@
         }
 
         if( cursorPos != 0 && move == 1 ) {
-
             //
-            setBacklight( calculateBacklight( cursorPos ) );
+            setBrightness( calculateBacklight( cursorPos ) );
 
             // Update screen
             updateCursor( cursorPos );
-	    nbFrames++;
         }
 
-        // Calculate and stabilize Frame Rate
-/*        if( update.getTicks() > 1000 )
-        {
-            printf("FPS: %f\n", (float)nbFrames  );
-            update.start();
-            nbFrames = 0;
-        }
-        while( fps.getTicks() < (1000 / NB_FRAMES_PER_SECOND) )
-        {
-            ;
-        }
-        fps.start();
-*/
         SDL_Delay(50);
     }
 
-    // Cleanup what we used
-    releaseBacklightControl();
-    freeRessources();
-    SDL_QuitSubSystem( SDL_INIT_TIMER );
-    SDL_Quit();
-
     return 0;
 }

Modified: trunk/target/demos/backlight_control/backlight_sysctl.c
===================================================================
--- trunk/target/demos/backlight_control/backlight_sysctl.c	2008-05-31 09:38:57 UTC (rev 813)
+++ trunk/target/demos/backlight_control/backlight_sysctl.c	2008-06-01 09:43:34 UTC (rev 814)
@@ -2,62 +2,65 @@
 #include <stdio.h>
 #include <stdlib.h>
 
-#include "backlight_sysctl.h"
 
-int playing, initialized = 0;
-FILE* fd;
-FILE* fda;
-unsigned char currentBacklight = 0;
+int initialized = 0;
+FILE* fd_bright;
+FILE* fd_max;
+unsigned char current_brightness = 0;
+int max_brightness = 255;
 
 #ifdef TARGET
-#define FREQ_SYS_FILE   "/sys/class/pwm/pwm0/frequency"
-#define ACTIVE_SYS_FILE "/sys/class/pwm/pwm0/active"
+#define BRIGHTNESS_SYS_FILE     "/sys/class/backlight/imxl-bl/brightness"
+#define MAX_BRIGHTNESS_SYS_FILE "/sys/class/backlight/imxl-bl/max_brightness"
 #else
-#define FREQ_SYS_FILE   "./backlight.dat"
-#define ACTIVE_SYS_FILE "./active"
+#define BRIGHTNESS_SYS_FILE     "./backlight.dat"
+#define MAX_BRIGHTNESS_SYS_FILE "./backlight.dat"
 #endif // TARGET
 
-SDL_TimerID myTimerID;
-
 /*
  * Initialize the system
- *
  */
 int initBacklightControl()
 {
     int result = -1;
+    int size = 0;
+    char buffer[6];
 
     if( !initialized )
     {
-        playing = 0;
-        fd  = fopen( FREQ_SYS_FILE, "w+" );
-        fda = fopen( ACTIVE_SYS_FILE, "w" );
+        fd_bright  = fopen( BRIGHTNESS_SYS_FILE, "w+" );
+        fd_max = fopen( MAX_BRIGHTNESS_SYS_FILE, "r" );
 
-        if( (fd != NULL) && (fda != NULL) )
+        if( (fd_bright != NULL) && (fd_max != NULL) )
         {
             result = 0;
             initialized = 1;
 #ifdef TARGET
-
+            size = fread( buffer, 1, 6, fd_max );
+            max_brightness = atoi(buffer);
+            printf("Max: %i\n", max_brightness);
+            size = fread( buffer, 1, 6, fd_bright );
+            current_brightness = atoi(buffer);
+            printf("Current: %i\n", current_brightness);
 #else
-            currentBacklight = 50; // %    
+            current_brightness = 50; // %    
 #endif // TARGET
-        } else
-            printf("Buzzer: can't open /sys interface\n");
+        } else {
+            printf("Backlight: can't open %s interface\n", BRIGHTNESS_SYS_FILE);
+        }
     }
     return( result );
 }
 
 /*
  * Free ressources allocated by the "library"
- *
  */
 void releaseBacklightControl()
 {
     if( initialized )
     {
-        fclose( fd );
-        fclose( fda );
+        fclose( fd_bright );
+        fclose( fd_max );
         initialized = 0;
     }
 }
@@ -65,25 +68,27 @@
 /*
  * 0-100 %
  */
-void setBacklight( unsigned char aValue )
+void setBrightness( unsigned char aValue )
 {
     if( initialized )
     {
         char value[4]; int nchar;
+        if( aValue > 100 ) aValue = 100;
+        aValue = (aValue * max_brightness) / 100;
 
-        // Program PWM with given frequency
+        // Send it to hardware
         nchar = sprintf( value, "%d", aValue);
-        fwrite( value, 1, nchar, fd );
-        fflush( fd );
-        currentBacklight = aValue;
+        fwrite( value, 1, nchar, fd_bright );
+        fflush( fd_bright );
+        current_brightness = aValue;
     }
 }
 
 /*
  * 0-100 %
  */
-unsigned char getBacklight( void )
+unsigned char getBrightness( void )
 {
-    return( currentBacklight );
+    return( (current_brightness * 100) / max_brightness  );
 }
 

Modified: trunk/target/demos/backlight_control/backlight_sysctl.h
===================================================================
--- trunk/target/demos/backlight_control/backlight_sysctl.h	2008-05-31 09:38:57 UTC (rev 813)
+++ trunk/target/demos/backlight_control/backlight_sysctl.h	2008-06-01 09:43:34 UTC (rev 814)
@@ -5,9 +5,12 @@
 // Initialize the Backlight control library
 int initBacklightControl( void );
 
-// Play a sound on buzzer at given frequency (Hz) and during given time (ms)
-void setBacklight( unsigned char aValue );
+// Set brightness to given value (0-100 %)
+void setBrightness( unsigned char );
 
+// Get current brightness (0-100 %)
+unsigned char getBrightness( void );
+
 // Free ressources allocated by the Backlight control library
 void releaseBacklightControl( void );
 

Deleted: trunk/target/demos/backlight_control/cursor.bmp
===================================================================
(Binary files differ)

Copied: trunk/target/demos/backlight_control/data/cursor.bmp (from rev 806, trunk/target/demos/backlight_control/cursor.bmp)
===================================================================
(Binary files differ)

Copied: trunk/target/demos/backlight_control/data/empty.bmp (from rev 806, trunk/target/demos/backlight_control/empty.bmp)
===================================================================
(Binary files differ)

Copied: trunk/target/demos/backlight_control/data/empty_end.bmp (from rev 806, trunk/target/demos/backlight_control/empty_end.bmp)
===================================================================
(Binary files differ)

Copied: trunk/target/demos/backlight_control/data/full.bmp (from rev 806, trunk/target/demos/backlight_control/full.bmp)
===================================================================
(Binary files differ)

Copied: trunk/target/demos/backlight_control/data/full_end.bmp (from rev 806, trunk/target/demos/backlight_control/full_end.bmp)
===================================================================
(Binary files differ)

Deleted: trunk/target/demos/backlight_control/empty.bmp
===================================================================
(Binary files differ)

Deleted: trunk/target/demos/backlight_control/empty_end.bmp
===================================================================
(Binary files differ)

Deleted: trunk/target/demos/backlight_control/full.bmp
===================================================================
(Binary files differ)

Deleted: trunk/target/demos/backlight_control/full_end.bmp
===================================================================
(Binary files differ)


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[Armadeus-commitlog] SF.net SVN: armadeus: [813] trunk/target/demos/armanoid

From: <ar...@us...> - 2008-05-31 09:38:53

Revision: 813
          http://armadeus.svn.sourceforge.net/armadeus/?rev=813&view=rev
Author:   artemys
Date:     2008-05-31 02:38:57 -0700 (Sat, 31 May 2008)

Log Message:
-----------
[DEMOS] Makes armanoid compiles again + install it in correct directories

Modified Paths:
--------------
    trunk/target/demos/armanoid/Makefile
    trunk/target/demos/armanoid/README
    trunk/target/demos/armanoid/armanoid.c

Added Paths:
-----------
    trunk/target/demos/armanoid/data/
    trunk/target/demos/armanoid/data/ball.bmp
    trunk/target/demos/armanoid/data/bar.bmp
    trunk/target/demos/armanoid/data/block.bmp

Removed Paths:
-------------
    trunk/target/demos/armanoid/ball.bmp
    trunk/target/demos/armanoid/bar.bmp
    trunk/target/demos/armanoid/block.bmp

Modified: trunk/target/demos/armanoid/Makefile
===================================================================
--- trunk/target/demos/armanoid/Makefile	2008-05-21 20:51:34 UTC (rev 812)
+++ trunk/target/demos/armanoid/Makefile	2008-05-31 09:38:57 UTC (rev 813)
@@ -7,14 +7,16 @@
 	SDL_DIR:=$(BUILD_DIR)/SDL-1.2.11/
 	STAGING_DIR:=$(BUILD_DIR)/staging_dir/
 	ROOT_DIR:=$(BUILDROOT_DIR)/project_$(BUILD_DIR_EXT)/armadeus/root/
-        INSTALL_DIR:=$(ROOT_DIR)/usr/bin/
+        INSTALL_DIR:=$(ROOT_DIR)/usr/games/
+	INSTALL_DATA_DIR:=$(ROOT_DIR)/usr/share/games/armanoid/
 
 	CC:=$(STAGING_DIR)/bin/arm-linux-gcc
 	DEFINES="TARGET"
 	CFLAGS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --cflags)
 	LIBS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --libs)
 else
-	INSTALL_DIR="."
+	INSTALL_DIR="/usr/games/"
+	INSTALL_DATA_DIR="/usr/share/games/armanoid/"
 	CFLAGS=`/usr/bin/sdl-config --cflags`
 	LIBS=`/usr/bin/sdl-config --libs`
 	CC=gcc
@@ -34,18 +36,19 @@
 collide.o: collide.c
 	$(CC) $(CFLAGS) -c -o $@ $^
 
-#timer.o: timer.cpp
-#	$(CC) $(CFLAGS) -c -o $@ $^
-
 buzzer.o: buzzer.c
 	$(CC) $(CFLAGS) -D$(DEFINES) -c -o $@ $^
 
 armanoid: armanoid.o collide.o buzzer.o
 	$(CC)  $(LIBS) -o $@ $^
 
-install: armanoid ball.bmp block.bmp bar.bmp
-	cp $^  $(INSTALL_DIR)
+install: armanoid data/ball.bmp data/block.bmp data/bar.bmp
+	mkdir -p $(INSTALL_DIR)
+	mkdir -p $(INSTALL_DATA_DIR)/data/
+	cp data/*.bmp  $(INSTALL_DATA_DIR)/data/
+	cp armanoid $(INSTALL_DIR)
 
 clean: 
 	rm -rf armanoid
 	rm -rf *.o
+

Modified: trunk/target/demos/armanoid/README
===================================================================
--- trunk/target/demos/armanoid/README	2008-05-21 20:51:34 UTC (rev 812)
+++ trunk/target/demos/armanoid/README	2008-05-31 09:38:57 UTC (rev 813)
@@ -10,6 +10,8 @@
 
 * ARM compiling:
  $ make clean; make install
+
 * x86 compiling (SDL devt package should be installed on your system)
- $ make clean; make TARGET=x86
-
+ $ make clean TARGET=x86; make TARGET=x86
+* x86 installing:
+ $ sudo make install TARGET=x86

Modified: trunk/target/demos/armanoid/armanoid.c
===================================================================
--- trunk/target/demos/armanoid/armanoid.c	2008-05-21 20:51:34 UTC (rev 812)
+++ trunk/target/demos/armanoid/armanoid.c	2008-05-31 09:38:57 UTC (rev 813)
@@ -44,6 +44,8 @@
 #define false 0
 #define true  1
 
+#define DEFAULT_DATA_DIR "/usr/share/games/armanoid/data/"
+
 SDL_Surface *back;
 SDL_Surface* block;
 SDL_Surface *screen;
@@ -112,10 +114,10 @@
 {
     int result = 0;
 
-    loadImage( &ball, "./ball.bmp");
-    loadImage( &bar, "./bar.bmp");
+    loadImage( &ball, DEFAULT_DATA_DIR "/ball.bmp");
+    loadImage( &bar, DEFAULT_DATA_DIR "/bar.bmp");
 
-    block = SDL_LoadBMP("./block.bmp");
+    block = SDL_LoadBMP( DEFAULT_DATA_DIR "/block.bmp" );
     BLOCK_HORI_SIZE = block->w;
     BLOCK_VERT_SIZE = block->h;
     // Check if we got all images

Deleted: trunk/target/demos/armanoid/ball.bmp
===================================================================
(Binary files differ)

Deleted: trunk/target/demos/armanoid/bar.bmp
===================================================================
(Binary files differ)

Deleted: trunk/target/demos/armanoid/block.bmp
===================================================================
(Binary files differ)

Copied: trunk/target/demos/armanoid/data/ball.bmp (from rev 800, trunk/target/demos/armanoid/ball.bmp)
===================================================================
(Binary files differ)

Copied: trunk/target/demos/armanoid/data/bar.bmp (from rev 800, trunk/target/demos/armanoid/bar.bmp)
===================================================================
(Binary files differ)

Copied: trunk/target/demos/armanoid/data/block.bmp (from rev 800, trunk/target/demos/armanoid/block.bmp)
===================================================================
(Binary files differ)


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[Armadeus-commitlog] SF.net SVN: armadeus: [812] trunk/target/demos

From: <ar...@us...> - 2008-05-21 20:51:38

Revision: 812
          http://armadeus.svn.sourceforge.net/armadeus/?rev=812&view=rev
Author:   artemys
Date:     2008-05-21 13:51:34 -0700 (Wed, 21 May 2008)

Log Message:
-----------
[TARGET] Add a small userspace tool to test keypad driver

Added Paths:
-----------
    trunk/target/demos/keypad_test/
    trunk/target/demos/keypad_test/Makefile
    trunk/target/demos/keypad_test/README
    trunk/target/demos/keypad_test/keypad.c

Added: trunk/target/demos/keypad_test/Makefile
===================================================================
--- trunk/target/demos/keypad_test/Makefile	                        (rev 0)
+++ trunk/target/demos/keypad_test/Makefile	2008-05-21 20:51:34 UTC (rev 812)
@@ -0,0 +1,44 @@
+
+ifeq ($(TARGET),)
+	BUILDROOT_DIR:=../../../buildroot/
+	BUILD_DIR_EXT:=$(shell ls $(BUILDROOT_DIR) | grep -e "^build_arm*")
+	BUILD_DIR:=$(BUILDROOT_DIR)/$(BUILD_DIR_EXT)
+
+	SDL_DIR:=$(BUILD_DIR)/SDL-1.2.11/
+	STAGING_DIR:=$(BUILD_DIR)/staging_dir/
+	ROOT_DIR:=$(BUILDROOT_DIR)/project_$(BUILD_DIR_EXT)/armadeus/root/
+        INSTALL_DIR:=$(ROOT_DIR)/usr/bin/
+
+	CC:=$(STAGING_DIR)/bin/arm-linux-gcc
+	DEFINES="TARGET"
+	CFLAGS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --cflags)
+	LIBS:=$(shell STAGING_DIR=$(STAGING_DIR) sh $(SDL_DIR)/sdl-config --libs)
+else
+	INSTALL_DIR="./install"
+	CFLAGS=`/usr/bin/sdl-config --cflags`
+	LIBS=`/usr/bin/sdl-config --libs`
+	CC=gcc
+	DEFINES="HOST"
+endif
+
+CFLAGS+="-g"
+
+default: keypad_test
+
+all: keypad_test
+
+
+keypad.o: keypad.c
+	$(CC) $(CFLAGS) -c -o $@ $^
+
+keypad_test: keypad.o
+	$(CC)  $(LIBS) -o $@ $^
+
+install: keypad_test
+	mkdir -p $(INSTALL_DIR)
+	cp $^  $(INSTALL_DIR)
+
+clean: 
+	rm -rf keypad_test
+	rm -rf *.o
+

Added: trunk/target/demos/keypad_test/README
===================================================================
--- trunk/target/demos/keypad_test/README	                        (rev 0)
+++ trunk/target/demos/keypad_test/README	2008-05-21 20:51:34 UTC (rev 812)
@@ -0,0 +1,6 @@
+
+* ARM compiling:
+ $ make clean; make install
+* x86 compiling (SDL devt package should be installed on your system)
+ $ make TARGET=x86 clean; make TARGET=x86
+

Added: trunk/target/demos/keypad_test/keypad.c
===================================================================
--- trunk/target/demos/keypad_test/keypad.c	                        (rev 0)
+++ trunk/target/demos/keypad_test/keypad.c	2008-05-21 20:51:34 UTC (rev 812)
@@ -0,0 +1,107 @@
+/*
+ * Small tool to test keypad (with the use of SDL library)
+ *   for the Armadeus project. www.armadeus.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h> // for sleep()
+
+#include "SDL.h"
+
+#define SCREEN_WIDTH  480
+#define SCREEN_HEIGHT 270
+
+#ifdef DEBUG
+#define debug( args...) printf( ## args )
+#else
+#define debug( args...) do {;} while(0);
+#endif
+
+#define bool  unsigned int
+#define false 0
+#define true  1
+
+SDL_Surface *screen;
+
+
+//---- Main ----
+
+int main(int argc, char *argv[])
+{
+    Uint8* keys;
+    int nbFrames = 0;
+    int cursorPos = 0;
+
+    // Initialize SDL
+    if( SDL_Init( SDL_INIT_VIDEO | SDL_INIT_TIMER /*| SDL_INIT_EVENTTHREAD |SDL_INIT_NOPARACHUTE*/) < 0 )
+    {
+        printf("Unable to init SDL: %s\n", SDL_GetError());
+        exit(1);
+    }
+    // Ask SDL to cleanup when exiting
+    atexit(SDL_Quit);
+
+    // Get a screen to display some stuff
+    screen=SDL_SetVideoMode( SCREEN_WIDTH, SCREEN_HEIGHT, 16, 0/*SDL_HWPALETTE*//*SDL_HWSURFACE|| SDL_DOUBLEBUF*/ );
+    if( screen == NULL )
+    {
+        printf("Unable to set %dx%dvideo mode: %s\n", SCREEN_WIDTH, SCREEN_HEIGHT, SDL_GetError());
+        exit(1);
+    }
+
+    int done=0, move=0;
+
+    // Hide mouse
+    SDL_ShowCursor(0);
+
+    // Main loop
+    while(done == 0)
+    {
+        SDL_Event event;
+        // Wait for SDL events
+        while ( SDL_PollEvent(&event) )
+        {
+            cursorPos = 0;
+            switch( event.type )
+            {
+                case SDL_QUIT:  {  done = 1; break; }
+
+                case SDL_KEYDOWN:
+                {
+			//if ( event.key.keysym.sym == SDLK_ESCAPE ) { done = 1; }
+			printf("Key down: %s\n", SDL_GetKeyName(event.key.keysym.sym));
+			break;
+                }
+
+                case SDL_KEYUP:
+                {
+                    //if ( event.key.keysym.sym == SDLK_ESCAPE ) { done = 1; }
+                    printf("Key up: %s\n", SDL_GetKeyName(event.key.keysym.sym));
+                    break;
+                }
+
+                default:
+		break;
+            }
+        }
+
+        SDL_Delay(50);
+    }
+
+    return 0;
+}


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[Armadeus-commitlog] SF.net SVN: armadeus: [811] trunk/firmware/apf_pkg

From: <Fa...@us...> - 2008-05-21 16:56:59

Revision: 811
          http://armadeus.svn.sourceforge.net/armadeus/?rev=811&view=rev
Author:   FabM
Date:     2008-05-21 09:56:39 -0700 (Wed, 21 May 2008)

Log Message:
-----------
[firmware][testbench] read/write function improvements (wsc can be set)

Modified Paths:
--------------
    trunk/firmware/apf_pkg/apf_test_pkg.vhd

Added Paths:
-----------
    trunk/firmware/apf_pkg/wishbone_test_pkg.vhd

Modified: trunk/firmware/apf_pkg/apf_test_pkg.vhd
===================================================================
--- trunk/firmware/apf_pkg/apf_test_pkg.vhd	2008-05-20 12:21:19 UTC (rev 810)
+++ trunk/firmware/apf_pkg/apf_test_pkg.vhd	2008-05-21 16:56:39 UTC (rev 811)
@@ -1,7 +1,7 @@
 ----------------------------------------------
 -- Design Name : Test bench utils
 -- File Name : apf_test_pkg.vhd
--- Function : Defines communication function between imx and fpga
+-- Function : Defines communication functions between imx and fpga
 -- Author   : Fabien Marteau <fab...@ar...>
 -- Version  : 1.00
 ---------------------------------------------
@@ -26,94 +26,127 @@
 use ieee.std_logic_1164.all;
 
 package apf_test_pkg is
-	-- read and write procedures
-	procedure imx_write(
-	address     : in std_logic_vector (15 downto 0);
-	value       : in std_logic_vector (15 downto 0);
-	signal   gls_clk     : in std_logic ;
-	signal   imx_cs_n    : out std_logic ;
-	signal   imx_oe_n    : out std_logic ;
-	signal   imx_eb3_n   : out std_logic ;
-	signal   imx_address : out std_logic_vector (12 downto 1);
-	signal   imx_data    : out std_logic_vector (15 downto 0)
+    -- write procedures
+    -- Params :
+    --    address      : Write address 
+    --    value        : value to write 
+    --    gls_clk      : clock signal
+    --    imx_cs_n     : Chip select 
+    --    imx_oe_n     : Read signal
+    --    imx_eb3_n    : Write signal
+    --    imx_address  : Address signal
+    --    imx_data     : Data signal
+    --    WSC          : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
+ 
+    procedure imx_write(
+    address     : in std_logic_vector (15 downto 0);
+    value       : in std_logic_vector (15 downto 0);
+    signal   gls_clk     : in std_logic ;
+    signal   imx_cs_n    : out std_logic ;
+    signal   imx_oe_n    : out std_logic ;
+    signal   imx_eb3_n   : out std_logic ;
+    signal   imx_address : out std_logic_vector (12 downto 0);
+    signal   imx_data    : out std_logic_vector (15 downto 0);
+    WSC         : natural
 );
-
+    -- read procedures
+    -- Params :
+    --    address      : Write address 
+    --    value        : value returned
+    --    gls_clk      : clock signal
+    --    imx_cs_n     : Chip select 
+    --    imx_oe_n     : Read signal
+    --    imx_eb3_n    : Write signal
+    --    imx_address  : Address signal
+    --    imx_data     : Data signal
+    --    WSC          : Value of imx WSC (see MC9328MXLRM.pdf p169) for sync=0
+ 
 procedure imx_read(
-address     : in std_logic_vector (15 downto 0);
-value       : out std_logic_vector (15 downto 0);
-signal   gls_clk     : in std_logic ;
-signal   imx_cs_n    : out std_logic ;
-signal   imx_oe_n    : out std_logic ;
-signal   imx_eb3_n   : out std_logic ;
-signal   imx_address : out std_logic_vector (12 downto 1);
-signal   imx_data    : in std_logic_vector (15 downto 0)
+    address     : in std_logic_vector (15 downto 0);
+    value       : out std_logic_vector (15 downto 0);
+    signal   gls_clk     : in std_logic ;
+    signal   imx_cs_n    : out std_logic ;
+    signal   imx_oe_n    : out std_logic ;
+    signal   imx_eb3_n   : out std_logic ;
+    signal   imx_address : out std_logic_vector (12 downto 0);
+    signal   imx_data    : in std_logic_vector (15 downto 0);
+    WSC         : natural
    );
 
 
 end package apf_test_pkg;
 
 package body apf_test_pkg is
-
-	-- Write value from imx
-	procedure imx_write(
-	address     : in std_logic_vector (15 downto 0);
-	value       : in std_logic_vector (15 downto 0);
-	signal   gls_clk     : in std_logic ;
-	signal   imx_cs_n    : out std_logic ;
-	signal   imx_oe_n    : out std_logic ;
-	signal   imx_eb3_n   : out std_logic ;
-	signal   imx_address : out std_logic_vector (12 downto 1);
-	signal   imx_data    : out std_logic_vector (15 downto 0)
+    
+    -- Write value from imx
+       
+    procedure imx_write(
+    address     : in std_logic_vector (15 downto 0);
+    value       : in std_logic_vector (15 downto 0);
+    signal   gls_clk     : in std_logic ;
+    signal   imx_cs_n    : out std_logic ;
+    signal   imx_oe_n    : out std_logic ;
+    signal   imx_eb3_n   : out std_logic ;
+    signal   imx_address : out std_logic_vector (12 downto 0);
+    signal   imx_data    : out std_logic_vector (15 downto 0);
+    WSC         : natural
 ) is
 begin
-	-- Write value
-	wait until falling_edge(gls_clk);
-	wait for 4 ns;
-	imx_address <= address(12 downto 1);
-	imx_cs_n <= '0';
-	imx_eb3_n <= '0';
-	wait until falling_edge(gls_clk);
-	wait for 2500 ps;
-	imx_data  <= value;
-	wait until falling_edge(gls_clk); --
-	wait until falling_edge(gls_clk); -- WSC = 2
-	wait for 1 ns;
-	imx_cs_n <= '1';
-	imx_eb3_n <= '1';
-	imx_address <= (others => 'Z');
-	imx_data  <= (others => 'Z');
+    -- Write value
+    wait until falling_edge(gls_clk);
+    wait for 4 ns;
+    imx_address <= address(12 downto 0);
+    imx_cs_n <= '0';
+    imx_eb3_n <= '0';
+    wait until falling_edge(gls_clk);
+    wait for 2500 ps;
+    imx_data  <= value;
+    if WSC <= 1 then
+        wait until falling_edge(gls_clk);
+    else
+        for n in 1 to WSC loop
+            wait until falling_edge(gls_clk); -- WSC = 2 
+        end loop;
+    end if;
+    wait for 1 ns;
+    imx_cs_n <= '1';
+    imx_eb3_n <= '1';
+    imx_address <= (others => 'Z');
+    imx_data  <= (others => 'Z');
 end procedure imx_write;
 
 -- Read a value from imx
 procedure imx_read(
-					address     : in std_logic_vector (15 downto 0);
-					value       : out std_logic_vector (15 downto 0);
-					signal   gls_clk     : in std_logic ;
-					signal   imx_cs_n    : out std_logic ;
-					signal   imx_oe_n    : out std_logic ;
-					signal   imx_eb3_n   : out std_logic ;
-					signal   imx_address : out std_logic_vector (12 downto 1);
-					signal   imx_data    : in std_logic_vector (15 downto 0)
-					   ) is
-					   begin
-						   -- Read value
-						   wait until falling_edge(gls_clk);
-						   wait for 4 ns;
-						   imx_address <= address(12 downto 1);
-						   imx_cs_n <= '0';
-						   imx_oe_n <= '0';
-						   wait until falling_edge(gls_clk);--
-						   wait until falling_edge(gls_clk);-- WSC = 2
-						   wait until rising_edge(gls_clk);
-						   value := imx_data;
-						   wait until falling_edge(gls_clk);
-						   imx_cs_n <= '1';
-						   imx_oe_n <= '1';
-						   imx_address <= (others => 'Z');
-						   wait for 20 ns;
+    address     : in std_logic_vector (15 downto 0);
+    value       : out std_logic_vector (15 downto 0);
+    signal   gls_clk     : in std_logic ;
+    signal   imx_cs_n    : out std_logic ;
+    signal   imx_oe_n    : out std_logic ;
+    signal   imx_eb3_n   : out std_logic ;
+    signal   imx_address : out std_logic_vector (12 downto 0);
+    signal   imx_data    : in std_logic_vector (15 downto 0);
+    WSC :  natural
+) is
+begin
+    -- Read value
+    wait until falling_edge(gls_clk);
+    wait for 4 ns;
+    imx_address <= address(12 downto 0);
+    imx_cs_n <= '0';
+    imx_oe_n <= '0';
+    if WSC <= 1 then
+        wait until falling_edge(gls_clk);
+    else
+        for n in 1 to WSC loop
+            wait until falling_edge(gls_clk); 
+        end loop;
+    end if;
+    value := imx_data;
+    wait until falling_edge(gls_clk);
+    imx_cs_n <= '1';
+    imx_oe_n <= '1';
+    imx_address <= (others => 'Z');
+    wait for 20 ns;
+end procedure imx_read;
 
-					   end procedure imx_read;
-
-
-
 end package body apf_test_pkg;

Added: trunk/firmware/apf_pkg/wishbone_test_pkg.vhd
===================================================================
--- trunk/firmware/apf_pkg/wishbone_test_pkg.vhd	                        (rev 0)
+++ trunk/firmware/apf_pkg/wishbone_test_pkg.vhd	2008-05-21 16:56:39 UTC (rev 811)
@@ -0,0 +1,39 @@
+---------------------------------------------------------------------------
+-- Company     : ARMades Systems
+-- Author(s)   : Fabien Marteau <fab...@ar...>
+-- 
+-- Creation Date : 15/04/2008
+-- File          : wishbone_test_pkg.vhd
+--
+-- Abstract : 
+--
+---------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+-- This program is free software; you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation; either version 2, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+package wishbone_test_pkg is
+-- read and write procedure
+	procedure wish_write(
+	address : in std_logic_vector( 15 downto 0);
+	value   : in std_logic_vector( 15 downto 0);
+	signal clk : in std_logic ;
+	signal rst : in std_logic ;
+	signal 


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[Armadeus-commitlog] SF.net SVN: armadeus: [810] trunk/buildroot/package/ch7024ctrl/ch70241ctrl. mk

From: <th...@us...> - 2008-05-20 12:21:25

Revision: 810
          http://armadeus.svn.sourceforge.net/armadeus/?rev=810&view=rev
Author:   thom25
Date:     2008-05-20 05:21:19 -0700 (Tue, 20 May 2008)

Log Message:
-----------
[PACKAGE] copy automatically the conf files in the rootfs

Modified Paths:
--------------
    trunk/buildroot/package/ch7024ctrl/ch70241ctrl.mk

Modified: trunk/buildroot/package/ch7024ctrl/ch70241ctrl.mk
===================================================================
--- trunk/buildroot/package/ch7024ctrl/ch70241ctrl.mk	2008-05-20 11:38:21 UTC (rev 809)
+++ trunk/buildroot/package/ch7024ctrl/ch70241ctrl.mk	2008-05-20 12:21:19 UTC (rev 810)
@@ -9,7 +9,9 @@
 CH7024CTRL_DIR:=$(BUILD_DIR)/ch7024ctrl-$(CH7024CTRL_VER)
 CH7024CTRL_CAT:=zcat
 CH7024CTRL_BINARY:=ch7024
-CH7024CTRL_TARGET_BINARY:=usr/bin/ch7024
+CH7024CTRL_TARGET_DIR:=usr/bin
+CH7024CTRL_TARGET_BINARY:=$(CH7024CTRL_TARGET_DIR)/$(CH7024CTRL_BINARY)
+CH7024CTRL_CONF_FILES:=ch*x*.conf
 
 $(CH7024CTRL_DIR)/ch7024.c:
 	set
@@ -22,10 +24,12 @@
 $(TARGET_DIR)/$(CH7024CTRL_TARGET_BINARY): $(CH7024CTRL_DIR)/$(CH7024CTRL_BINARY)
 	install -D $< $@
 	$(STRIPCMD) $(STRIP_STRIP_UNNEEDED) $(TARGET_DIR)/$(CH7024CTRL_TARGET_BINARY)
+	cp $(CH7024CTRL_DIR)/$(CH7024CTRL_CONF_FILES) $(TARGET_DIR)/$(CH7024CTRL_TARGET_DIR)
 
 ch7024ctrl: uclibc $(TARGET_DIR)/$(CH7024CTRL_TARGET_BINARY)
 
 ch7024ctrl-clean:
+	rm -f $(TARGET_DIR)/$(CH7024CTRL_TARGET_DIR)/$(CH7024CTRL_CONF_FILES)
 	rm -f $(TARGET_DIR)/$(CH7024CTRL_TARGET_BINARY)
 	-$(MAKE) -C $(CH7024CTRL_DIR) clean
 


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[Armadeus-commitlog] SF.net SVN: armadeus: [809] trunk/target/packages/ch7024ctrl

From: <th...@us...> - 2008-05-20 11:38:15

Revision: 809
          http://armadeus.svn.sourceforge.net/armadeus/?rev=809&view=rev
Author:   thom25
Date:     2008-05-20 04:38:21 -0700 (Tue, 20 May 2008)

Log Message:
-----------
[PACKAGE] add new config file for LQ043 likeinput format for Svideo 
output

Added Paths:
-----------
    trunk/target/packages/ch7024ctrl/ch500x320.conf
    trunk/target/packages/ch7024ctrl/ch500x320_readme.txt

Added: trunk/target/packages/ch7024ctrl/ch500x320.conf
===================================================================
--- trunk/target/packages/ch7024ctrl/ch500x320.conf	                        (rev 0)
+++ trunk/target/packages/ch7024ctrl/ch500x320.conf	2008-05-20 11:38:21 UTC (rev 809)
@@ -0,0 +1,15 @@
+00:45   01:00   02:00   03:03
+04:00   05:40   06:40   07:40
+08:80   09:05   0A:63   0B:08
+0C:00   0D:03   0E:00   0F:00
+10:A1   11:09   12:e0   13:f4
+14:00   15:06   16:00   17:05
+18:10   19:40   1A:30   1B:50
+1C:90   1D:9E   1E:05   1F:44
+20:00   21:30   22:00   23:7D
+24:00   25:00   26:00   27:00
+28:0E   29:09   2A:C0   2B:10
+2C:7A   2D:C0   2E:4b   2F:00
+30:09   31:14   32:5C   33:00
+34:01   35:1C   36:64   37:40
+62:32   63:C2   7E:00

Added: trunk/target/packages/ch7024ctrl/ch500x320_readme.txt
===================================================================
--- trunk/target/packages/ch7024ctrl/ch500x320_readme.txt	                        (rev 0)
+++ trunk/target/packages/ch7024ctrl/ch500x320_readme.txt	2008-05-20 11:38:21 UTC (rev 809)
@@ -0,0 +1,12 @@
+iMXL LCD controller parameters:
+LPCR: 0XF8C80085
+HCR:  0X28000500
+VCR:  0X0c001617
+
+LCD freq: 7630000Hz
+
+SysClk has to be changed from internal to external:
+CSCR = 0x03010003
+SPCTL0 = 0x04011402
+SPCTL1 = 0x00000040 
+


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[Armadeus-commitlog] SF.net SVN: armadeus: [808] trunk/target/linux/modules

From: <ar...@us...> - 2008-05-19 18:21:29

Revision: 808
          http://armadeus.svn.sourceforge.net/armadeus/?rev=808&view=rev
Author:   artemys
Date:     2008-05-19 11:20:51 -0700 (Mon, 19 May 2008)

Log Message:
-----------
[LINUX] Move i.MXL matrix keypad driver back to its correct directory

Modified Paths:
--------------
    trunk/target/linux/modules/Kconfig
    trunk/target/linux/modules/Makefile
    trunk/target/linux/modules/fpga/Kconfig

Added Paths:
-----------
    trunk/target/linux/modules/imxlkeypad/

Removed Paths:
-------------
    trunk/target/linux/modules/fpga/keypad/

Modified: trunk/target/linux/modules/Kconfig
===================================================================
--- trunk/target/linux/modules/Kconfig	2008-05-18 15:56:14 UTC (rev 807)
+++ trunk/target/linux/modules/Kconfig	2008-05-19 18:20:51 UTC (rev 808)
@@ -14,6 +14,8 @@
 
 source "drivers/armadeus/gpio/Kconfig"
 
+source "drivers/armadeus/imxlkeypad/Kconfig"
+
 comment "FPGA related"
 	depends on ARMADEUS_DRIVERS
 

Modified: trunk/target/linux/modules/Makefile
===================================================================
--- trunk/target/linux/modules/Makefile	2008-05-18 15:56:14 UTC (rev 807)
+++ trunk/target/linux/modules/Makefile	2008-05-19 18:20:51 UTC (rev 808)
@@ -8,7 +8,7 @@
 ifneq ($(KERNELRELEASE),)
 
 obj-$(CONFIG_ARMADEUS_DRIVERS)	+= gpio/ pwm/ backlight/ isp1761/ \
-	fpga/ps2keyboard/ fpga/keypad/ fpga/fpga_devtools/ fpga/Wb_led/ fpga/Wb_button/ \
+	fpga/ps2keyboard/ imxlkeypad/ fpga/fpga_devtools/ fpga/Wb_led/ fpga/Wb_button/ \
 	fpga/i2ctest/ fpga/fpgaaccess/
 
 # Part execute when called from standard make in this directory:

Modified: trunk/target/linux/modules/fpga/Kconfig
===================================================================
--- trunk/target/linux/modules/fpga/Kconfig	2008-05-18 15:56:14 UTC (rev 807)
+++ trunk/target/linux/modules/fpga/Kconfig	2008-05-19 18:20:51 UTC (rev 808)
@@ -13,8 +13,6 @@
 	
 source "drivers/armadeus/fpga/fpga_devtools/Kconfig"
 
-source "drivers/armadeus/fpga/keypad/Kconfig"
-
 source "drivers/armadeus/fpga/ps2keyboard/Kconfig"
 
 source "drivers/armadeus/fpga/Wb_led/Kconfig"

Copied: trunk/target/linux/modules/imxlkeypad (from rev 807, trunk/target/linux/modules/fpga/keypad)


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[Armadeus-commitlog] SF.net SVN: armadeus: [807] trunk/target/linux/modules/fpga/keypad/ imxkeypad.c

From: <ar...@us...> - 2008-05-18 15:56:25

Revision: 807
          http://armadeus.svn.sourceforge.net/armadeus/?rev=807&view=rev
Author:   artemys
Date:     2008-05-18 08:56:14 -0700 (Sun, 18 May 2008)

Log Message:
-----------
[LINUX] Add some commentaries in imxkeypad driver

Modified Paths:
--------------
    trunk/target/linux/modules/fpga/keypad/imxkeypad.c

Modified: trunk/target/linux/modules/fpga/keypad/imxkeypad.c
===================================================================
--- trunk/target/linux/modules/fpga/keypad/imxkeypad.c	2008-05-15 14:53:02 UTC (rev 806)
+++ trunk/target/linux/modules/fpga/keypad/imxkeypad.c	2008-05-18 15:56:14 UTC (rev 807)
@@ -55,7 +55,7 @@
 #define KB_ROWMASK(r)		(1 << (r + kpdPtr->rows_offset))
 #define SCANCODE(c,r)		( (c * kpdPtr->num_rows) + (r) )
 
-#define KB_DELAY		8
+#define KB_DELAY		8	/* uS */
 #define SCAN_INTERVAL		(HZ/10)
 
 static unsigned char imxkeypad_keycode[KPD_MAX_ROWS * KPD_MAX_COLS] = {
@@ -83,11 +83,11 @@
 	int 	debouncing;
 };
 
+/* module parameters definition */
 static int io_port=0;
 module_param(io_port, int, 0000);
 MODULE_PARM_DESC(io_port, "GPIO port (0..3)");
 
-
 static long int size[]={4,4};
 module_param_array(size, long, NULL, 0000);
 MODULE_PARM_DESC(size, "matrix size: num rows, num cols");
@@ -119,12 +119,12 @@
 }
 
 /*
- * The imx keypad only generates interrupts when a key is pressed.
+ * The i.MX keypad only generates interrupts when a key is pressed.
  * So when a key is pressed, we enable a timer.  This timer scans the
  * keyboard, and this is how we detect when the key is released.
  */
 
-/* Scan the hardware keyboard and push any changes up through the input layer */
+/* Scan the hardware keyboard and push any changes up to the Input layer */
 static void imxkeypad_scankeyboard(struct imxkeypad *kpdPtr) 
 {
 	unsigned int row, col, scancode;
@@ -157,7 +157,7 @@
 
 	input_sync(kpdPtr->input);
 
-	/* on key release repeat some scan to remove debounce */
+	/* on key release, repeat some scan to remove debounce */
 	if ((!num_pressed)&&(0 <= kpdPtr->debouncing)) {
 		kpdPtr->debouncing--;
 	}
@@ -171,7 +171,6 @@
 		/* if any keys are pressed or still checking debounce, enable the timer */
 		mod_timer(&kpdPtr->timer, jiffies + SCAN_INTERVAL);
 	}
-
 }
 
 /* 
@@ -246,7 +245,6 @@
 	imxkeypad.input->id.version = 0x0100;
 
 
-
 	printk(KERN_DEBUG "imxkeypad matrix size: %ld rows, %ld cols\n", size[0], size[1]);
 	imxkeypad.num_rows = size[0];
 	imxkeypad.num_cols = size[1];
@@ -278,12 +276,13 @@
 		
 	}	
 
-	/* Activate every column to detect any key pressed */
+	/* Activate(??) every column to detect any key pressed */
 	imxkeypad_activate_all(&imxkeypad);
 
+	/* register driver to the Linux Input layer */
 	input_register_device(imxkeypad.input);
 
-	/* attempt to get the interrupts */
+	/* attempt to reserve the interrupts (on i.MXL each GPIO can generate it's own interrupt) */
 	for (i = 0; i < imxkeypad.num_rows; i++) {
 		imxkeypad.irqs[i] = IMX_IRQS + 32*imxkeypad.port + imxkeypad.rows_offset + i;
 		printk(KERN_DEBUG "imxkeypad: requesting irq %d\n", imxkeypad.irqs[i]);
@@ -292,7 +291,7 @@
 			printk(KERN_ERR "imxkeypad: Can't get irq for keyboard\n");
 			goto free;
 		}
-		else set_irq_type( imxkeypad.irqs[i], IRQF_TRIGGER_FALLING );
+		else set_irq_type( imxkeypad.irqs[i], IRQF_TRIGGER_FALLING ); /* configure it as falling edge sensitive */
 	}
 	
 	return 0;


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