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Application defines templates of VHDL structures, which allows us comfortly generate most used VHDL structures. It can also work with VHDL testbench templates from which can be created VHDL testbenches of existing projects.
This project includes a set of tools and guidelines designed for rapid production of large-scale embedded systems projects. The tools enable quick generation of reusable, reconfigurable hardware, using a user-specified hardware description language.
A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.
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