Search Results for "user mode linux" - Page 3
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Showing 72 open source projects for "user mode linux"
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Manage your enterprise’s compensation lifecycle and accurately recognize top performers with a digitized, integrated system. Keep employees invested and your HR team in control while preventing compensation chaos.
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Parallelsimu provides interfaces for parallel simulation of RTL descriptions of complex hardware designs(SoCs, CPUs and etc.) written in Verilog HDL.
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This is an image coder with fixed sampling, at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with res. up to 352x288).
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Give your HR team the tools they need to streamline administrative tasks, support employees, and make informed decisions with the OrangeHRM free and open source HR software.
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OpenWebServo is an Open Source Hardware and Software project. Its main goal is to develop a web-controlled servo system. The project includes web application, firmware and hardware design.
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Compiler-like program that checks Verilog source for common design errors. This tool can help beginning Verilog programmers who aren't aware of common design pitfalls and advanced Verilog programmers who want to double check large projects.
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the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol
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Plugin Eclipse/VDT supports hardware development in VHDL/Verilog, allowing to easily integrate command-line controlled tools in Eclipse. Underlying Eclipse/ExDT plugin provides integration means that may be used for other languages and applications.
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This means every device on your network, and every interface on every device is automatically analyzed for performance, errors, QoS, and configuration.
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This project is a collection of Open Source crypto cores and implementations relating to high speed cryptanalysis/cracking and complex implementations.
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Software to support the JTAG bus (IEEE 1149.1). Primary purpose is for a JTAG programmer/debugger using FPGA's to provide ability to test and program JTAG devices.
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A software package that will combine different embedded computing platforms with home exercise equipment and a Qt client program in order to provide tracking of health and exercise performance.
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The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.
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The Affordable BIOS Restoration Tool provides VHDL and C code to recover from failed BIOS upgrades using affordable CPLD's. EEPROM's and Flash chips can be restored with this flash programmer. Interfaces for DIP and tsop packages are being developed.
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Yet Another DLX based Architecture System On a Chip (YADASOC) is a RTL Verilog implenetation of a DLX based CPU and subsystems.
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X-RT
X-RT: A portable multiprocessor real-time scheduling framework
... version supports major POSIX systems (Linux, QNX). 2) Hardware_GEDF_Scheduler: is a hardware implementation in VHDL (targeting FPGAs) of the G-EDF multiprocessor scheduling policy. -
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Design and implementation of silicon and software for baseband processors conforming to IEEE wireless standards. Initial focus on WiMAX and WiFi.
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The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.
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Picode is the ultimate VHDL picode 16 to 32 bits controller. It is described in only one entity and is implementable in standard FPGAs. It has it own compiler. Picode is designed to take only one or two clock cycle duration per instruction.
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Labcoat: Cleanroom Apps for SuperWikia
Labcoat; the VHDL graphic emulator.
Labcoat for SuperWikia Alpha fabrication manages new or revised fabrication processes. Its 'Cleanroom' applets allow codesmiths to access the lab environment, used to create semiconductors, substrate prototypes, chipset instruction blocks and other Labcoat projects. Our extensions in future releases will include UML support for C#/C++ conforming projects, import/export architecture schematics and refactoring sub-projects.