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This is a collection of tools and a code library to assist engineers who are developing SystemVerilog based verification environments. Components include utility libraries, scoreboard and shutdown manager implementation, register tool, etc.
PEP is a modelling and verification framework for parallel systems, providing a large number of different modelling languages and verification techniques (e.g. SDL, Petri nets and model checking)
This project aims at providing Open Source tools for the development and the verification of SystemC/TLM (Transaction Level Modeling) IP models, and at promoting their use by embedded software developers on SoC (System-On-Chip).