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SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
Antiexcel is a Microsoft-Excel file reader. It shows the excel file on a text console or an x-console.
It can be used as an attachment viewer for any text-based email client ( ex. mutt)
Wiki Text Formatting Engine (WTF Engine) converts simple text into HTML. It will run on any platform using a variety of languages such as PHP, Perl, JavaScript and VB Script. It is intended to be a library used in other software packages.