Search Results for "code::blocks"

...On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

Simple text editor. Run: $perl 01text0.pl

Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)

Build texts and documents bottom-up from building blocks using a language similar (and compatible with) that of GNU Make, in such a way that variants (e.g. translations) can be generated by overwriting parts of the text with minimal redundancy.

A language-neutral syntax highlighting module in Perl. Can be based off syntax files for popular text/code editors or custom parsing modules for a specific language.

Unicode Builder, generates code or a binary file for use in programs that require understanding of characters.