Search Results for "class code generator"

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)

A language-neutral syntax highlighting module in Perl. Can be based off syntax files for popular text/code editors or custom parsing modules for a specific language.

Unicode Builder, generates code or a binary file for use in programs that require understanding of characters.

The TeX Math Font Generator is a set of programs that can produce a set of TeX math fonts that resemble a given text font. If you want to typeset mathematics with TeX in a special font that you own, then MathGen is what you want.