Search Results for "assembly source code"
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Showing 5 open source projects for "assembly source code"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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Perl Text Editor
Source code for perl simple text editor.
Simple text editor. Run: $perl 01text0.pl -
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
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A language-neutral syntax highlighting module in Perl. Can be based off syntax files for popular text/code editors or custom parsing modules for a specific language.
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5
Unicode Builder, generates code or a binary file for use in programs that require understanding of characters.
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