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SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
English: Power C++ is an IDE for C++. Have suppor for C# files. This is a BETA version, which means that there is still work to be done.
Español: Power C++ es un IDE para el lenguage de programación C++. Tiene soporte para archivos de C#. Esta es una versión BETA, lo que significa que aun falta trabajo por hacer.