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Inventors: Validate Your Idea, Protect It and Gain Market Advantages
SenseIP is ideal for individual inventors, startups, and businesses
senseIP is an AI innovation platform for inventors, automating any aspect of IP from the moment you have an idea. You can have it researched for uniqueness and protected; quickly and effortlessly, without expensive attorneys. Built for business success while securing your competitive edge.
Advanced TECO dialect and interactive screen editor based on Scintilla
SciTECO is an interactive TECO dialect, similar to Video TECO. It also adds features from classic TECO-11, as well as unique new ideas.
Project development takes place here:
https://git.fmsbw.de/sciteco
The download archive is mirrored at Sourceforge, but for nightly builds check out:
https://sciteco.fmsbw.de/downloads/nightly/
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing