Open Source MinGW/MSYS2 Text Processing Software

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Text Processing Software for MinGW/MSYS2

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Browse free open source Text Processing software and projects for MinGW/MSYS2 below. Use the toggles on the left to filter open source Text Processing software by OS, license, language, programming language, and project status.

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  • 1
    Ada Class Library

    Ada Class Library

    Ada Class Library - an object orientated library for Ada.

    Text search and replace. Scripting (small tool programs). CGI scripts. Execution of external programs (incl. I/O redirection). Garbage Collection. Extendended Booch Components. CD-Recorder
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    Downloads: 69 This Week
    Last Update:
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  • 2
    SciTECO

    SciTECO

    Advanced TECO dialect and interactive screen editor based on Scintilla

    SciTECO is an interactive TECO dialect, similar to Video TECO. It also adds features from classic TECO-11, as well as unique new ideas. Project development takes place here: https://git.fmsbw.de/sciteco The download archive is mirrored at Sourceforge, but for nightly builds check out: https://sciteco.fmsbw.de/downloads/nightly/
    1 Review
    Downloads: 1 This Week
    Last Update:
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  • 3
    Luna Editor

    Luna Editor

    Write and edit your lua scripts in an easy way.

    Write and edit your lua scripts in an easy way.
    Downloads: 1 This Week
    Last Update:
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  • 4
    Ltxshell
    Shell for calling LaTeX and accompanying tools (dvi-viewer, dvips, ps-file-viewer, pdf-file-viewer) on Linux and Windows-systems
    Downloads: 0 This Week
    Last Update:
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  • 5

    Power C++

    C and C++ IDE

    English: Power C++ is an IDE for C++. Have suppor for C# files. This is a BETA version, which means that there is still work to be done. Español: Power C++ es un IDE para el lenguage de programación C++. Tiene soporte para archivos de C#. Esta es una versión BETA, lo que significa que aun falta trabajo por hacer.
    Downloads: 0 This Week
    Last Update:
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  • 6

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 0 This Week
    Last Update:
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