Search Results for "fsm"
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Showing 3 open source projects for "fsm"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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NunniMCAX is a minimal (19KB) C library for parsing XML. The API recall SAX and is sequential and event-driven. The parser strives to verify that the XML is well-formed, but no validation. NunniMCAX's FSM has been generated using NunniFSMGen
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NunniMJAX is a minimal java library for parsing XML. The API and functioning recall SAX and is sequential and event-driven. The parser strives to verify that the XML is well-formed, but no validation. NunniMJAX's FSM has been generated using NunniFSMGen
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