Search Results for "timing"
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2 projects for "timing" with 2 filters applied:
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SciTECO
Advanced TECO dialect and interactive screen editor based on Scintilla
SciTECO is an interactive TECO dialect, similar to Video TECO. It also adds features from classic TECO-11, as well as unique new ideas. Project development takes place here: https://git.fmsbw.de/sciteco The download archive is mirrored at Sourceforge, but for nightly builds check out: https://sciteco.fmsbw.de/downloads/nightly/ -
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SmGen
Verilog Finite State Machine (FSM) Code Generator
...SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
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