Search Results for "control system studio"

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

GitSync is a shell script designed to simplify the usage of the version control system GIT (see www.git-scm.com for more information) by providing a "do everything to sync my repository" command.