Browse free open source VHDL/Verilog Text Editors and projects below. Use the toggles on the left to filter open source VHDL/Verilog Text Editors by OS, license, language, programming language, and project status.

  • Our Free Plans just got better! | Auth0 Icon
    Our Free Plans just got better! | Auth0

    With up to 25k MAUs and unlimited Okta connections, our Free Plan lets you focus on what you do best—building great apps.

    You asked, we delivered! Auth0 is excited to expand our Free and Paid plans to include more options so you can focus on building, deploying, and scaling applications without having to worry about your security. Auth0 now, thank yourself later.
    Try free now
  • No-Nonsense Code-to-Cloud Security for Devs | Aikido Icon
    No-Nonsense Code-to-Cloud Security for Devs | Aikido

    Connect your GitHub, GitLab, Bitbucket, or Azure DevOps account to start scanning your repos for free.

    Aikido provides a unified security platform for developers, combining 12 powerful scans like SAST, DAST, and CSPM. AI-driven AutoFix and AutoTriage streamline vulnerability management, while runtime protection blocks attacks.
    Start for Free
  • 1

    Notepad++ Verilog Plugin

    Verilog plugin for Notepad++

    Verilog processor for Notepad++. Current features: - Instantiate a module - Insert registers/wires from a module - Generate a test bench template - Automatically inserts a default header for a test bench - Insert a clocked always block v1.2.0 now supports ANSI and non-ANSI module declarations. To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C. This selects the module and parses its components. After this, all other functions are available.
    Downloads: 5 This Week
    Last Update:
    See Project
  • 2

    VHDL Notepad++ Plugin

    VHDL Plugin for the Notepad++ Editor

    VHDL plugin based on http://sourceforge.net/projects/nppvhdlplugin/ This version is enhanced to include: - Insert Instantiation - Insert Signals - Create Test Bench Framework - Insert Component - Make comments Doxygen compliant - Create New Behavioral/Structural Entity Template - Create New Package File Template - Insert Synchronous Process - Insert Asynchronous Process - Insert a Default Header The default header is set in the vhdlConfig.txt file.
    Leader badge
    Downloads: 2 This Week
    Last Update:
    See Project
  • 3

    PLP

    Powerfull pre-processor

    Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
    Downloads: 0 This Week
    Last Update:
    See Project
  • 4

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 0 This Week
    Last Update:
    See Project
  • MongoDB 8.0 on Atlas | Run anywhere Icon
    MongoDB 8.0 on Atlas | Run anywhere

    Now available in even more cloud regions across AWS, Azure, and Google Cloud.

    MongoDB 8.0 brings enhanced performance and flexibility to Atlas—with expanded availability across 125+ regions globally. Build modern apps anywhere your users are, with the power of a modern database behind you.
    Learn More
  • Previous
  • You're on page 1
  • Next
Want the latest updates on software, tech news, and AI?
Get latest updates about software, tech news, and AI from SourceForge directly in your inbox once a month.