Search Results for "system control panel"
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Showing 3 open source projects for "system control panel"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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A backup/transfer files program to move and process files between computers in a production (industrial) process. The processing of file begins when it are created or copied to directory and they can be redirected to other machine to be used.
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tgen generates a Web site from a collection of input files of a variety of types, using a set of registered HTML autogenerators. Cvs-Brancher allows scheduling of web deployments. vwebedit provides web-based editing of cvs repositories.
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