Search Results for "control"
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Showing 4 open source projects for "control"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
...SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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PLP
Powerfull pre-processor
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc) -
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A backup/transfer files program to move and process files between computers in a production (industrial) process. The processing of file begins when it are created or copied to directory and they can be redirected to other machine to be used.
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tgen generates a Web site from a collection of input files of a variety of types, using a set of registered HTML autogenerators. Cvs-Brancher allows scheduling of web deployments. vwebedit provides web-based editing of cvs repositories.
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