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SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
A web editor designed to span the gap between wysiwyg and hand coding
The Andromeda editor is a project designed to form a bridge for those who use WYSIWYG editors that employ drag and drop techniques to move to using HTML, CSS and JS. There is also a facility to use PHP and SQLite databases under development.
There are also some built in tools that can be used both within the design UI or as standalone tools in their own right.