A simple Embedded System Framework that allows rapid development of applications build for AVR family. System is based on a super-loop architecture with check and skip (no-wait) flag event driver system.
Supports:
UART, SysTick Timer, ADC, SPI, EEPROM, PWM.
Also supports: Xilinx FPGA configuration, FPGA SSI interface, smart card reader etc.
Tested partially (different modules in each case) on ATMega163/16/32/323/8.
Awards
CodeProject 2010, Third Prize, Hardware and Device...