Search Results for "timing"
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Showing 3 open source projects for "timing"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
...SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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This tool monitors your Active Directory or OpenLDAP server via LDAP on a daily basis, and sends emails out to users who's account are about to expire. Notification timing, messages, and frequency can all be customized with multiple profiles.
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A simple command to convert calendar dates to julian dates. Quite useful in timing situations where you need elapsed time between dates. Also useful for astronomy applications.
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