Search Results for "eda"
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Showing 5 open source projects for "eda"
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Gemini 3 and 200+ AI Models on One PlatformBuild, govern, and optimize agents and models with Gemini Enterprise Agent Platform.
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Streamline Azure Security with Palo Alto Networks VM-SeriesImprove your security posture and reduce incident response time. Use the VM-Series to natively analyze Azure traffic and dynamically drive policy updates based on workload changes.
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VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
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UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It is a descendant of the popular openwince JTAG tools with a lot of additional features and enhancements.
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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unPIC is a Perl script that disassembles Microchip microcontroller's HEX files. This is a powerful tool for all reverse engeneers that creates a well understandable assembly source from a binary file. Creates xrefs, labels, subroutines and much more...
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Compliant and Reliable File Transfers Backed by Top Security CertificationsStop relying on non-certified, legacy file transfer tools that creak under the weight of modern security demands. Get full audit trails, advanced access controls and more supported by an award-winning team of experts. Start your free 25-day trial today.
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Grid-tools is a collection of scripts to aid in the submission of complex jobs to either Sun Grid Engine or LSF.
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