Search Results for "aztec code generator"

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

IOSEC PHP HTTP FLOOD PROTECTION ADDONS IOSEC is a php component that allows you to simply block unwanted access to your webpage. if a bad crawler uses to much of your servers resources iosec can block that. IOSec Enhanced...

Boiler-template (source) file generator. Automates (source) file generation from template files: speeds up developement of redundant or re-usable software and more. An example template for Linux Kernel Device Drivers generation, is included.

The goal of the A.I.G. project is to create a "front end" script that will custom build chart generation code for any environment based on user input.