Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
Contains a framework for Coldfire MCUs like 52254.
The framework supports a Command Line Interface (CLI) that may work from Serial port, USB or ENET.
The framework uses Processor Expert and IDE requirement is MCU Eclipse 10.4 from Freescale.
Includes the FunkOS Realtime Operating System by Funkenstein Software Consulting, available at http://funkos.sourceforge.net
Mainly it is a support package for the development board Perseus, but I have ported also the RTOS to MCF52233DEMO board.
More to come....
Verilog processor for Notepad++. Current features:
- Instantiate a module
- Insert registers/wires from a module
- Generate a test bench template
- Automatically inserts a default header for a test bench
- Insert a clocked always block
v1.2.0 now supports ANSI and non-ANSI module declarations.
To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C.
Writing Testbenches for FPGA/ASIC design is always a very fastidious and boring task.
This project helps any FPGA/ASIC designer by providing a full RTL test environment with C support.
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