Search Results for "eda software"
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Showing 46 open source projects for "eda software"
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BSC
Bluespec Compiler (BSC)
BSC is the open source compiler toolchain for Bluespec SystemVerilog, a high-level, rule-based hardware design language. It translates Bluespec descriptions into synthesizable Verilog, letting developers bring typed, modular abstractions into mainstream FPGA/ASIC flows. The compiler performs scheduling of atomic rules, elaborates parameterized modules, and enforces interface contracts, producing predictable RTL that integrates with existing EDA tools. A companion simulator enables fast... -
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SpinalHDL
Scala based HDL
SpinalHDL is a hardware description (HDL) framework embedded in Scala, enabling hardware designers to build digital circuits with modern programming abstractions. Instead of writing in Verilog or VHDL directly, users describe hardware components and their interconnects using Scala code and Spinal’s domain-specific library, which then emits synthesizable hardware (e.g. as Verilog). Because SpinalHDL is embedded in Scala, it allows reuse of functional abstractions, parameterization, modular... -
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AsyncAPI
Allows you to create machine-readable definitions of asynchronous APIs
AsyncAPI is an open-source initiative that seeks to improve the current state of Event-Driven Architecture (EDA). Our long-term goal is to make working with EDAs as easy as working with REST APIs. That goes from documentation to code generation, from discovery to event management, and beyond. The AsyncAPI Specification defines a standard, protocol-agnostic interface that describes message-based or event-driven APIs. The AsyncAPI document allows people or machines communicating with one... -
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wxArt2D gives wxWindows applications sophisticated vector drawing functionality. It is based on a framework supporting multiple views within a hierarchical document. Supports drawing & (Graph) editing. In-output in SVG, GDSII, XML, easy to extend.
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Pest Control Management SoftwareBuilt for the pest control industry, but also works great for Mosquito Control, Bin Cleaning, Window Washing, Solar Panel Cleaning, and other Home Service Businesses in need of an easy-to-use software that helps you simplify routing, scheduling, communications, payment processing, truck tracking, time tracking, and reporting.
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Rocket Chip
Rocket Chip Generator
Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. A diplomacy framework (LazyModules) lets designers wire components with negotiated parameters, enabling reuse and rapid exploration of... -
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Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.
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SkyWater PDK
Open source process design kit for usage with SkyWater Technology
The SkyWater PDK is the first broadly available open-source process design kit for a commercial-grade CMOS node, enabling researchers, startups, and students to design real ASICs without proprietary NDAs. It provides the essential artifacts for digital and analog flows: SPICE models, DRC/LVS rules, extraction decks, and technology files for open tools like Magic and KLayout. Standard-cell libraries and IO pads are included so digital designers can use open synthesis and place-and-route to... -
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JSDAI is a toolkit for STEP (ISO 10303), the STandard for the Exchange of Product Model data, that enables linking of CAD, CAM, PDM, PLM, CAx systems. JSDAI supports the development of Express data models (ISO 10303-11) and their implementation in Java.
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Smart Business Texting that Generates PipelineTextUs is the leading text messaging service provider for businesses that want to engage in real-time conversations with customers, leads, employees and candidates. Text messaging is one of the most engaging ways to communicate with customers, candidates, employees and leads. 1:1, two-way messaging encourages response and engagement. Text messages help teams get 10x the response rate over phone and email. Business text messaging has become a more viable form of communication than traditional mediums. The TextUs user experience is intentionally designed to resemble the familiar SMS inbox, allowing users to easily manage contacts, conversations, and campaigns. Work right from your desktop with the TextUs web app or use the Chrome extension alongside your ATS or CRM. Leverage the mobile app for on-the-go sending and responding.
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Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
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The project development has been moved on GitHub https://github.com/pcb2gcode/pcb2gcode The GUI for pcb2gcode can be found here https://github.com/pcb2gcode/pcb2gcodeGUI pcb2gcode is a command-line tool for isolation, routing and drilling of PCBs that provides full support for both single- and double-sided boards. For more information, see http://sourceforge.net/apps/mediawiki/pcb2gcode/
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Project 2306 IDE Rad MacOS MCU DeveR
Electronic design and programming tools suite like Eagle, MpLab
...Adobe PDF Help section SQL Connectivity Community Avail : https://www.facebook.com/Project-Core-2306-Nextgen-Eda-pcbradide-for-Mcumacoslinuxwindows-138250749681138/?fref=ts -
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NEW OPTIMIZATION TECHNOLOGY & PLANNING EXPERIMENT. Technology is designed for multidimensional optimization practical problems with continuous object functions. Technology higher efficiency than traditional optimization methods.
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This project is a general AVR bootloader, for different type of AVR device, all you need to do is modify macro definition, and you don not need to modify the main program.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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ApproxAdderLib
Library of Approximate Adders
We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as... -
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TimeDoctor is a tool to visualize execution traces of tasks, queues, cache behavior, etc. While originally targeting embedded media processors and includes specific features for analyzing audio/video streaming applications it has wider applicability.
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At the moment its simple command line tool to create nice looking schematic libraries in kicad. I hope that it would be usefull for someone. dont need to click anything just write/paste pin names and thats it.
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic... -
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JdonFramework
a Domain Driven Design + CQRS + EventSource java framework
1. INTRODUCTION --------------------------------------------- JdonFramework is a java framework to build your Domain Driven Design + CQRS + EventSource applications with asynchronous concurrency and higher throughput. 2. GETTING STARTED ------------------ In the "example" directory there are several examples for web application. You can run runTest.bat in this directory to see how to play JdonFramework in Application. In the "doc" directory there are all documents about... -
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EnDiskEx
Bulk extractor for Ensoniq-formatted disk images
EnDiskEx is a command-line tool that bulk extracts instruments, sequences, songs, and banks from Ensoniq-formatted disk images (RAW, GKH, EDE, and EDA) for the EPS/ASR family of samplers. The extracted files are saved as EFE / SMF / TXT files. EnDiskEx is designed to extract Ensoniq banks for re-creation within a different DAW. It will track down the instrument and song files from bank references even if they were saved on another disk. There also exists a disk mapping feature to... -
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Create the open-source algorithm for the EDA, it has released two products, GVeri- a code editor embeded compiler to design hardware, mini-router - a LEA algorithm for routing.
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This tool compares Value Change Dump files, which is useful for regression testing of Verilog models. VCD files are dumpfiles generated by EDA logic simulation tools.
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FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info in wiki.
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Gaphor is a UML modeling environment written in Python. Gaphor is small and very extensible. The repository is located at http://github.com/gaphor/gaphor.
