Search Results for "vcd"
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2 projects for "vcd" with 2 filters applied:
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This tool compares Value Change Dump files, which is useful for regression testing of Verilog models. VCD files are dumpfiles generated by EDA logic simulation tools.
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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
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