Search Results for "eda"
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32 projects for "eda" with 2 filters applied:
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wxArt2D gives wxWindows applications sophisticated vector drawing functionality. It is based on a framework supporting multiple views within a hierarchical document. Supports drawing & (Graph) editing. In-output in SVG, GDSII, XML, easy to extend.
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Rocket Chip
Rocket Chip Generator
...The generator supports custom accelerators through the RoCC interface, allowing domain-specific compute units to be plugged into the pipeline with shared cache and memory semantics. Tooling integrates with FIRRTL, Verilator, and commercial EDA flows, and the ecosystem around Rocket Chip (e.g., Chipyard) adds harnesses, peripherals, and verification infrastructure. -
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SkyWater PDK
Open source process design kit for usage with SkyWater Technology
...Because the PDK is open, it becomes a common target for community reference designs, open tapeouts, and teaching curricula. Documentation and example flows show how to assemble complete toolchains, from RTL to sign-off, using open EDA components. The project effectively lowers the barrier to custom silicon, catalyzing an ecosystem around an accessible 130-nm process. -
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Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
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Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.
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NEW OPTIMIZATION TECHNOLOGY & PLANNING EXPERIMENT. Technology is designed for multidimensional optimization practical problems with continuous object functions. Technology higher efficiency than traditional optimization methods.
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Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
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ApproxAdderLib
Library of Approximate Adders
We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as... -
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TimeDoctor is a tool to visualize execution traces of tasks, queues, cache behavior, etc. While originally targeting embedded media processors and includes specific features for analyzing audio/video streaming applications it has wider applicability.
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At the moment its simple command line tool to create nice looking schematic libraries in kicad. I hope that it would be usefull for someone. dont need to click anything just write/paste pin names and thats it.
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PHDL
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic... -
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JdonFramework
a Domain Driven Design + CQRS + EventSource java framework
1. INTRODUCTION --------------------------------------------- JdonFramework is a java framework to build your Domain Driven Design + CQRS + EventSource applications with asynchronous concurrency and higher throughput. 2. GETTING STARTED ------------------ In the "example" directory there are several examples for web application. You can run runTest.bat in this directory to see how to play JdonFramework in Application. In the "doc" directory there are all documents about... -
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EnDiskEx
Bulk extractor for Ensoniq-formatted disk images
...EnDiskEx has been tested and validated against a variety of RAW, GKH, EDE, and EDA images files the dev team has, including but not limited to, the ASR factory disks, the EPS 16+ factory disks, and the EPS (classic) factory disks. -
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This tool compares Value Change Dump files, which is useful for regression testing of Verilog models. VCD files are dumpfiles generated by EDA logic simulation tools.
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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
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vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
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The PARSEC CEE is the primary achievement of several years of effort at NASA's Marshall Space Flight Center. The CEE was developed to allow engineers in the Advanced Concepts Department to rapidly prototype launch vehicle and spacecraft concepts.
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This is a tool developed by 2nd yr CSE B.Techs at IIT Guwahati.We have designed a software in C++ language which,given some design specifications of an analog amplifier generates a netlist file in the current folder which can be opened in LTSpice.
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HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
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F- is an ANSish Forth that uses a VM generator to compile Forth into C-based VM suitable for living in a C-based (or assembly or HDL) microcontroller project. The VM supplies 32-bit math, I/O, multitasking and debugger in a ROM footprint as small as 4kB.
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unPIC is a Perl script that disassembles Microchip microcontroller's HEX files. This is a powerful tool for all reverse engeneers that creates a well understandable assembly source from a binary file. Creates xrefs, labels, subroutines and much more...
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pyLPCTools is a replacement for the Flash Programming Tools use with the Philips(tm)/NXP(tm) LPC2xxx series of ARM based microcontrollers. pyLPCTools is a script together with some ARM assembly language and a Python user interface. Please Donate !!
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Sk2Py is an wxPython-based IDE which assists in the migration of Cadence Skill(tm)-based PCells to Python PyCells for use in all Open Access environments. Please post any support requests or bug reports to the tracking system.
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Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.
