Search Results for "avx"

...Rather than serving as a standalone ML framework, XNNPACK provides high-performance computational primitives—such as convolutions, pooling, activation functions, and arithmetic operations—that are integrated into higher-level frameworks like TensorFlow Lite, PyTorch Mobile, ONNX Runtime, TensorFlow.js, and MediaPipe. The library is written in C/C++ and designed for maximum portability, efficiency, and performance, leveraging platform-specific instruction sets (e.g., NEON, AVX, SIMD) for optimized execution. It supports NHWC tensor layouts and allows flexible striding along the channel dimension to efficiently handle channel-split and concatenation operations without additional cost.

cpu_features is a cross-platform C library developed by Google that provides a simple and efficient way to detect available CPU features at runtime across a wide range of architectures and operating systems. It enables applications to determine which instruction sets (such as SSE, AVX, or NEON) are supported on the host machine, allowing developers to optimize performance dynamically. The library supports numerous architectures—including x86, ARM, AArch64, MIPS, POWER, RISCV, LoongArch, and s390x—and works on major operating systems like Linux, macOS, Windows, FreeBSD, Android, and iOS. Implemented in portable C99, it is thread-safe, has no memory allocations, and raises no exceptions, making it suitable even for use in low-level system libraries. ...

Vector Pascal is a language targeted at SIMD multi-core instruction-sets such as the AVX and SSE2 or x86-64-v3. It has a SIMD compiler which supports parallel vector operations, loop unrolling, common sub expression removal etc. It is implemented in Java.

...The assembler itself isn't a separate tool, but rather a collection of C/C++ header files, which applications need to include directly in order to use. At present, Intel SSE/SSE2/SSE4 and AVX/AVX2/AVX-512 (32/64-bit x86 ISAs), ARMv7 NEON/NEONv2, ARMv8 AArch32 and AArch64 NEON, SVE (32/64-bit ARM ISAs), MIPS 32/64-bit r5/r6 MSA and POWER 32/64-bit VMX/VSX (little/big-endian ISAs) are mostly implemented (/w horizontal reductions) although scalar improvements, wider SIMD vectors with zeroing/merging predicates in 3/4-operand instructions are planned as extensions to current 2/3-operand SPMD-driven vertical SIMD ISA. ...

...- Support for the Intel and AT&T syntax - An instruction renderer - An instruction parser - Instructions represented as generic models - UNIX/GNU/Linux and Windows support - Portable - written entirely in C (no external dependencies) - C++ wrapper - Supported instruction sets: MMX, 3D-Now!, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4A, AVX, AVX2, AES, TBM, BMI1, BMI2, HLE, ADX, CLMUL, RDRAND, RDSEED, FMA, FMA4, LWP, SVM, XOP, VMX, SMX, AVX-512 Source code moved to: https://github.com/swojtasiak/fcml-lib

JWasm is a Masm-compatible assembler. It supports 16-, 32- and 64-bit code, instructions up to AVX and various output formats. It's written in C.