Search Results for "avx"

...However, differences across CPU architectures and compilers make direct usage complex, which xsimd addresses by offering a unified API that maps efficiently to underlying hardware capabilities. The library supports a wide range of instruction sets, including SSE, AVX, NEON, and WebAssembly SIMD, ensuring portability across platforms. It provides vectorized implementations of common mathematical operations, allowing developers to operate on batches of values using familiar syntax. xsimd is widely adopted in performance-critical applications.

...Rather than serving as a standalone ML framework, XNNPACK provides high-performance computational primitives—such as convolutions, pooling, activation functions, and arithmetic operations—that are integrated into higher-level frameworks like TensorFlow Lite, PyTorch Mobile, ONNX Runtime, TensorFlow.js, and MediaPipe. The library is written in C/C++ and designed for maximum portability, efficiency, and performance, leveraging platform-specific instruction sets (e.g., NEON, AVX, SIMD) for optimized execution. It supports NHWC tensor layouts and allows flexible striding along the channel dimension to efficiently handle channel-split and concatenation operations without additional cost.

...It provides vector, matrix, and math operations with a syntax identical or very similar to HLSL, allowing seamless transition between shader code and application code. The library is optimized for performance and supports SIMD instructions across multiple architectures, including SSE, AVX, AVX2, AVX512, and ARM NEON, ensuring high efficiency on modern hardware. It also extends beyond standard HLSL capabilities by introducing additional features such as quaternion support, advanced matrix operations, and extended vector types like float8. The library is particularly valuable for game developers who need consistency between CPU and GPU computations, reducing errors and improving maintainability.

...Under the SPMD model, the programmer writes a program that generally appears to be a regular serial program, though the execution model is actually that a number of program instances execute in parallel on the hardware. ispc compiles a C-based SPMD programming language to run on the SIMD units of CPUs and GPUs; it frequently provides a 3x or more speedup on architectures with 4-wide vector SSE units and 5x-6x on architectures with 8-wide AVX vector units, without any of the difficulty of writing intrinsics code. Parallelization across multiple cores is also supported by ispc, making it possible to write programs that achieve performance improvement that scales by both numbers of cores and vector unit size. Build a small set of extensions to the C language that would deliver excellent performance to performance-oriented programmers.

cpu_features is a cross-platform C library developed by Google that provides a simple and efficient way to detect available CPU features at runtime across a wide range of architectures and operating systems. It enables applications to determine which instruction sets (such as SSE, AVX, or NEON) are supported on the host machine, allowing developers to optimize performance dynamically. The library supports numerous architectures—including x86, ARM, AArch64, MIPS, POWER, RISCV, LoongArch, and s390x—and works on major operating systems like Linux, macOS, Windows, FreeBSD, Android, and iOS. Implemented in portable C99, it is thread-safe, has no memory allocations, and raises no exceptions, making it suitable even for use in low-level system libraries. ...

...The assembler itself isn't a separate tool, but rather a collection of C/C++ header files, which applications need to include directly in order to use. At present, Intel SSE/SSE2/SSE4 and AVX/AVX2/AVX-512 (32/64-bit x86 ISAs), ARMv7 NEON/NEONv2, ARMv8 AArch32 and AArch64 NEON, SVE (32/64-bit ARM ISAs), MIPS 32/64-bit r5/r6 MSA and POWER 32/64-bit VMX/VSX (little/big-endian ISAs) are mostly implemented (/w horizontal reductions) although scalar improvements, wider SIMD vectors with zeroing/merging predicates in 3/4-operand instructions are planned as extensions to current 2/3-operand SPMD-driven vertical SIMD ISA. ...

cppcrypto provides optimized implementations of cryptographic primitives. Hash functions: BLAKE, BLAKE2, Echo, Esch, Groestl, JH, Kupyna, MD5, SHA-1, SHA-2, SHA-3, SHAKE, Skein, SM3, Streebog, Whirlpool. Block ciphers: Anubis, Aria, Camellia, CAST-256, Kalyna, Kuznyechik, Mars, Serpent, Simon, SM4, Speck, Threefish, Twofish, and Rijndael (AES) with all block/key sizes. Stream ciphers: HC-128, HC-256, Salsa20, XSalsa20, ChaCha, XChaCha. Encryption modes: CBC, CTR. AEAD modes:...

...- Support for the Intel and AT&T syntax - An instruction renderer - An instruction parser - Instructions represented as generic models - UNIX/GNU/Linux and Windows support - Portable - written entirely in C (no external dependencies) - C++ wrapper - Supported instruction sets: MMX, 3D-Now!, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4A, AVX, AVX2, AES, TBM, BMI1, BMI2, HLE, ADX, CLMUL, RDRAND, RDSEED, FMA, FMA4, LWP, SVM, XOP, VMX, SMX, AVX-512 Source code moved to: https://github.com/swojtasiak/fcml-lib

...The algorithms are optimized with using of different SIMD CPU extensions. In particular the library supports following CPU extensions: SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and AVX-512 for x86/x64, VMX(Altivec) and VSX(Power7) for PowerPC, NEON for ARM. The Simd Library has C API and also contains useful C++ classes and functions to facilitate access to C API. The library supports dynamic and static linking, 32-bit and 64-bit Windows, Android and Linux, MSVS, G++ and Clang compilers, MSVS project and CMake build systems.