4 projects for "open systemc" with 2 filters applied:

  • Paessler: Easy to Use With Enterprise Power. Free Trial Icon
    Paessler: Easy to Use With Enterprise Power. Free Trial

    A low-code dashboard makes monitoring intuitive for any admin, while scripting and custom sensors give experts full control.

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  • Veeam Data Platform v13.1 Icon
    Veeam Data Platform v13.1

    Move workloads across hypervisors and clouds with no vendor lock-in. Try VDP free today.

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  • 1
    ...SCNSL has migrated: please go to GitLab for the latest version: https://gitlab.com/open-kappa/scnsl
    Downloads: 0 This Week
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  • 2
    Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
    Downloads: 0 This Week
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  • 3
    HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
    Downloads: 1 This Week
    Last Update:
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  • 4
    Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
    Downloads: 0 This Week
    Last Update:
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  • MongoDB Atlas runs apps anywhere Icon
    MongoDB Atlas runs apps anywhere

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