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NEW OPTIMIZATION TECHNOLOGY & PLANNING EXPERIMENT. Technology is designed for multidimensional optimization practical problems with continuous object functions. Technology higher efficiency than traditional optimization methods.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
These classes are useful for signal processing in Matlab or C++. They bring together tools and methods which may be used interchangeably for Matlab and C++. Their initial use is in conjunction with work towards my degree at UC Berkeley.
Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.
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This is a tool developed by 2nd yr CSE B.Techs at IIT Guwahati.We have designed a software in C++ language which,given some design specifications of an analog amplifier generates a netlist file in the current folder which can be opened in LTSpice.
ESOMA is a component orientated framework for simulation and evaluation
of arbitrary microprocessor and DSP architectures. Simulators using
ESOMA are runtime configurable. Architectural changes do not need
recompiling. Programming language is C++ (Linu
Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
vIDE is a cross-platform tool for writing and simulating Verilog models. It provides user friendly project management and file editing, integrated simulation engine, waveform viewer, pre-compiled modules, and many other cool features.