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Approximate Adder for FPGA-based Image Processing Applications
Using Approximate Computing, we have designed an innovative approximate adder with real-world image processing applications. The uploaded project includes its Matlab and Verilog models for result reproduction. This is an ongoing study and we aim to formally publish it for better understanding of viewers.
The design of an open platform devoted to allow students perform distance practices
with a real FPGA device involves both hardware and software components.
The OpenFire processor is a Xilinx MicroBlaze-compatible processor being modified for use in Cyber Physical Systems research. This material is based upon work supported by the National Science Foundation under Grant No. CPS-0932113.
The Daedalus Design framework is a complete design flow for multi-media embedded Multi-processor System-on-Chip (MPSoC) platforms. It transforms a high level system description into an FPGA prototype in a largely automated way in only a matter of hours.
The "RISC-0" project is a collection of Python libraries and programs to support the RISC architecture described by Prof. Niklaus Wirth on his web page (http://www.inf.ethz.ch/personal/wirth/Articles/FPGA-relatedWork/index.html)