Search Results for "eda tool"

SimFPGA is a graphical user interface (GUI) tool designed to facilitate the simulation of VHDL projects. It enables users to select VHDL source files and testbenches, configure library and standard settings, and run simulations using GHDL. Additionally, it allows visualization of waveforms through GTKWave. SimFPGA elaborates the project files using GHDL and builds the VHDL project before simulating it. This ensures code verification without the need for additional compilation tools. If...

DLD V 2.0 Released Digital Logic Design is a Software tool for designing and simulating digital circuits. It provides digital parts ranging from simple gates to Arithmetic Logic Unit. You may start your circuit from simple gates and flipflops and keep on converting them into ICs. These ICs, later on, may be incorporated into other circuits to built more complex circuits like CPU. You may even use SOP expressions to generate digital circuits in IC form. You can use this software to...

This project is dedicated to the optimization of (any) electrical and electronic circuits and components using evolutionary and heuristic algorithms incorporated with SPICE simulators (such as HSPICE, ngSPICE, etc.). We provide Optimer, which is a user graphical interface for circuit design and optimization. Website: https://www.circuitoptimization.com/ E-mail: contact@circuitoptimization.com/

FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.

A simulation tool for Phase-Locked Loops with charge pump phase detectors. The tool simulates phase and frequency steps with continous reference and random bit stream reference for data clock recovery.

The developed graphical interface is based on the SKILL language which is a Lisp dialect used as a scripting language and PCell (Parameterized Cells) description language used in many EDA software suites by Cadence Design Systems.

This is a tool developed by 2nd yr CSE B.Techs at IIT Guwahati.We have designed a software in C++ language which,given some design specifications of an analog amplifier generates a netlist file in the current folder which can be opened in LTSpice.

Tool-independent Makefile generator for VHDL models.

Magnetostatic finite differences simulation tool based on GNU Octave and a Perl/Tk user interface.

NecJGui is an antennas design tool, interface for Numerical Electromagnetic Code. It allows easily making NEC input files, and viewing them in 3D. It also contains a version of the simulator, so it's complete IDE for full-wave EM simulation.