Search Results for "systemc"

...ipxact2verilog : Tool to convert IP-XACT into Verilog module ipxactinterface2svinterface : Converts IP-XACT Bus Definition / BusInterface into System Verilog Interface verilog2lib : Create Liberty .lib library from verilog module lib2verilog : Converts Liberty .lib Cells into empty verilog modules verilog2systemc : Tool to convert Verilog into SystemC keeping the original structure as much as possible. ipxactreg2xlsreg : Converts IP-XACT Address Block file into XLSX for review and documentation purpose xls2ipxact : Creates IP-XACT Address Block file from the legacy XLS/CSV based Register Management system.

SystemC Network Simulation Library (SCNSL) is an extension of SystemC to allow modelling packet-based networks such as wireless networks, ethernet, fieldbus, etc. As done by basic SystemC for signals on the bus, SCNSL provides primitives to model packet trasmission, reception, contention on the channel and wireless path loss. The use of SCNSL allows the easy and complete modelling of distributed applications of networked embedded systems such as wireless sensor networks, routers, and distributed plant controllers. ...

Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.

...You can log in to our Youtube channel to watch some videos about S2CBench and SystemC in general www.youtube.com/DARClabify or visit our labs web page at www.utdallas.edu/~schaferb/darclab To know more about the designs and why they were included in the benchmark suite you can read the following academic paper: B. Carrion Schafer and A. Mahapatra, "S2CBench:Synthesizable SystemC Benchmark Suite for High-Level Synthesis ", IEEE Embedded Systems Letters, 2014

SystemC-WMS (Wave Mixed Signal Simulator) is a class library that extends the standard SystemC kernel to allow modeling and simulation of complex systems comprising analog parts from heterogeneous domain (electrical, mechanical, thermal, ...).

Systemc simulation module controlling This tool is aimed to ease the systemc simulation processing.

PKtool is a SystemC/C++ environment dedicated to the power estimation for digital systems described in SystemC.

A networks-on-chip (NoC) simulator allows designers to early estimate performance (latency and throughput), energy efficiency (average/peak power, average energy per packet) and area of several networks on-chip configurations at different CMOS nodes. This tool is a cycle-accurate simulator and is open-source using SystemC, a C++ plugin, which is used to quickly model complex systems at a higher level but less details than RTL. NoCTweak was developed by Dr. Anh Tran and Dr. Bevan Baas at UC Davis. NoCTweak has been extended and integrated into McSim, a project developed by Dr. Abdoulaye Gamatié, Dr. Gilles Sassatelli, Dr. Manuel Selva et al. at LIRMM lab. ...

Power/Energy simulation in SystemC. Powersim is a SystemC class library aimed to the calculation of power and energy consumption of hardware described at system level. To this end C++ operators are monitored and different energy models can be used for each data type. Powersim does not require any change in the application source code. Current version is 0.3.0.

s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.

HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.

HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.

FERMAT's SystemC Parser using Doxygen and Xerces-C++ XML

Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.

The Open SystemC Initiative (OSCI) is a collaborative effort to support and advance SystemC as a de facto standard for system-level design. SystemC is an interoperable, C++ SoC/IP modeling platform for fast system-level design and verification

The project aims to build a MATHWORKS MATLAB Simulink like IDE environment by utilizing the SystemC and GNU scientific library.

Using SystemC to develop a System On Chip system. The Design includes a MIPS CPU, Arbiter, DMA controller, SRAM controller, UART controller. This design are compatible to the IBM CoreConnect™ Architecture and the On-chip Peripheral Bus (OPB) standard.