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Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
...Remove existing hierarchy
9. Associate the IP-XACT memory maps with the SoC component instances
10. Dump out the C Model for the entire design
11. Glue-Logic insertion
12. Spare port insertion across hierarchies
13. Automatic creation of the top module and it's ports based upon specified rule
14. Creates stub module