Search Results for "parallel port automation"

1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity...

Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API...

HOPSA, high oxygen pressure sputter automation, is a Python 3 project to control a step wise sample creation Process. Although written for this specific task it is easy to adopt for any experimental task which changes hardware parameters and waits for a specific condition before proceeding. The graphical interface (QT4) includes plotting (matplotlib), instrument configuration/monitoring and a program step creator. The communication with the hardware is independent of the GUI and any number...

FoamBlade provides a complete toolchain for hotwire foam-cutting. FoamBlade currently supports 4-axis hot-wire foamcutting machines that are connected to the parallel port. Generating cut-files from special built DXF-Files is also possible.

Mind this project is no longer maintained. You might be interested in having a look at http://pythonhosted.org/plasduino/ instead. Framework for data acquisition through the parallel port, suitable for performing simple didactic physics experiment.