Search Results for "java component"

Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API...

1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity...

Cca-forum unifies the Common Component Architecture tools and tutorial. It includes the CCA specifications, the Ccaffeine framework for HPC, and related tools. These support multilanguage scientific and parallel computing.

The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.

J-Sim (previously known as JavaSim) is a component-based, compositional simulation environment written in Java. It is built upon the autonomous component architecture (ACA), a component architecture at the implementation level.

The OO component based XML processing framework.The goal is to make the XML developer's life easier.It's going ot achieve that by providing reusable components for all stages of XML processsing with easy language and application binding.

VisAD is a Java component library for interactive and collaborative visualization and analysis of numerical data.