Search Results for "state machine editor"
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Showing 2 open source projects for "state machine editor"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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Automalator
State Dependency deconstructor and mapper for C source code.
Flowcharts not telling you what you want to know about some C source code? Try a State Dependency map! Every C source file is an implemention of a state machine. Implicit in the definition of a state machine is a network of dependencies between the states. The Automalator * deconstructs the C code into the core state machine * collates the transactions into the dependency net * generates a diagram-format file with the states and dependencies as the nodes and edges. ...
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