Search Results for "description logic"

...Quantum programs are described using the measurement-based quantum circuit model with support for classical feed-forward flow control based on measurement outcomes. OpenQASM presents a parameterized set of physical logic gates and concurrent real-time classical computations. Its main goal is to serve as an intermediate representation for higher-level compilers to communicate with quantum hardware. Allowances have been made for human usability. In particular, the language admits different representations of the same program as it is transformed from a high-level description to a pulse representation.

UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. ...

...The volume of the tetrahedron is then calculated. Tetrahedrons with back facing triangles are added and those with forward facing triangles are subtracted yielding the object volume. A detailed description of the process is presented in the ObjectVolumeTutorial.doc document as well as program logic and results. A key component in the program is a subroutine that calculates the volume of a tetrahedron. Four sets of equations were tested and to my surprise all four produced similar results in accuracy and timing.

...In case of usage, please refer to our publication: Muhammad Shafique, Rehan Hafiz, Semeen Rehman, Walaa El-Harouni, Jörg Henkel, "Cross-Layer Approximate Computing: From Logic to Architectures", Design Automation Conference (DAC), 2016. Contributors: Authors, Vanshika Baoni, M. Abdullah Hanif http://ces.itec.kit.edu/lpACLib.php

libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.