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Showing 22 open source projects for "rtl"
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Leku
Map location picker component for Android
Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker. Component library for Android that uses Google Maps and returns a latitude, longitude and an address based on the location picked with the Activity provided. Note that you have the voice_search_extra_language that is used for the language of the voice recognition. Replace it with the allowed voice recognition locale for your language. We encourage you to add these languages to this... -
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Free VHDL Parser with Java, Python and T
IEEE VHDL-93 LRM supported parser implemented in Java, APIs Python/Tcl
This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. ... -
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System Verilog Parser IEEE 1800 LRM
IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the users that they will be able to extract every bit of design information from the parsed database. ... -
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1. flattenverilog : Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist. 2. preprocessverilog : Verilog Preprocessor to resolve macros like nested `ifdef , `define 3. createhierarchy : Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents in the higher leve 5. removehierarchy : Verilog Hierarchy Removal Tool to ungroup all the instances in a given module 6. comparemoduleinterfaces - Diff module ports and parameter. ...
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IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
...ipxact2verilog - Generate Verilog module from IP-XACT definition ipxact2vhdlentity - Generate VHDL entity from IP-XACT Component definition verilog2ipxact - Generates IP-XACT definition from Verilog modules vhdl2ipxact - Generates IP-XACT definition from VHDL source ipxactcoherencycheckerverilog / ipxactcoherencycheckervhdl - Validates IP-XACT Component definition with RTL validateipxact - IP-XACT Linting tool -
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echoes
Echoes is a radio spectral analysis software for SDR devices
Echoes it's a radio spectral analysis software for SDR devices, designed for meteor scattering purposes. The older releases supported only RTL-SDR devices. They are very cheap SDR based on DVB-T TV tuner dongles based on Realtek's RTL2832U chipset. Starting from 0.50 Echoes embeds SoapySDR allowing the support of many other SDRs. Echoes doesn't demodulate neither decode any human-made signal. Its main goal is to analyze and record the total power of natural signals and generate screenshots and tabular data (CSV,) output in presence of particular peaks in a selected narrow range of frequencies. ... -
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gr-acars
ACARS decoder for GNURadio, for RTL-SDR, PlutoSDR or UHD receivers.
A "simple" demonstration software for decoding ACARS, a low-bandwidth communication protocol used by airplanes to communicate with airports. Detailed description of the operating principles is available at http://jmfriedt.free.fr/lm_sdr.pdf (French) and http://jmfriedt.free.fr/en_sdr.pdf (English). The latest 2022 release for GNU Radio 3.9 and 3,10, following 3.8 named ng for New Generation, aims at adding bitrate clock tracking + removes the external dependence with libfftw by using the GNU... -
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DEVS-Suite Simulator
Component, CA, and CCA models; superdense time, DB repo, testing, etc.
Integrated component-based and cellular automata (CA) Parallel DEVS simulator: https://acims.asu.edu/devs-suite/ OFFERS: 1) synchronized execution & animation, 2) run-time linear/superdense I/O & state trajectories, 3) Action Level Real-Time modeling & simulation, 4) model checking, 5) ABM, 6) CA & composable CA playback, 7) KIB interaction modeling, 8) hierarchical model libraries, 9) Black-Box testing & debugging, 10) PostgreSQL repository, 11) FMU (OpenModelica), 12) OSATE (AADL)... -
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Panoramic FFT analyzer direct access RTL
Panoramic spectrum analyzer with access to RTL
Panoramic spectrum analyzer with access to RTL: 1. Direct access to the RTL-SDR chip is used 2. Calculation of the spectrum by the FFT method 3. Panorama of the accumulation of spectral sections 4. The ability to cyclically record samples in a file in a circle -
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VlibTools
Tools and libraries for use with systemc and verilog
Tool suite and libraries for developing system-c models. Tools for managing RTL projects. -
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Libraries providing optimized alternative implementations for Delphi VCL/RTL functions, methods and classes.
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Arnav Digital Signal Processing
A real-time Discrete Signal Processing software and API for MS Windows
A real-time Discrete Signal Processing software and API for Microsoft Windows OS which can connect to SDR devices like RTL-SDR and USRP. The API can be called from C/C++ programs as well from any .NET 4.5 client applications. -
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RTLSDR Scanner
A cross platform Python frequency scanning GUI for rtl-sdr
A cross platform Python frequency scanning GUI for USB TV dongles, using the OsmoSDR rtl-sdr library. In other words a cheap, simple Spectrum Analyser. More information can be found at: http://eartoearoak.com/software/rtlsdr-scanner An installer and standalone versions for Windows are located here: https://github.com/EarToEarOak/RTLSDR-Scanner/releases Sources are available on GitHub: https://github.com/EarToEarOak/RTLSDR-Scanner ** The up to date installer is no longer maintained on this site and can now be found at https://github.com/EarToEarOak/RTLSDR-Scanner/releases ** -
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WS1281 decoder
Decoding of OOK signals transmitted by a weather sensor on 433,82 Mhz
WS1281DEC is a portable Win32 application that extract and display the data transmitted by WS1281 weather station external sensor, using the sound device of a PC computer and some additional hardware and software. Hardware requirements are RTL-SDR dongle (e4000 or R820T tuner ), external antenna, and a PC. As additional software, it is necessary to have SDR Sharp and Virtual Audio Cable. The whole system was tested on Windows 7 64 bit OS -
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Virastyar
Virastyar is an spell checker for low-resource languages
Virastyar is a free and open-source (FOSS) spell checker. It stands upon the shoulders of many free/libre/open-source (FLOSS) libraries developed for processing low-resource languages, especially Persian and RTL languages Publications: Kashefi, O., Nasri, M., & Kanani, K. (2010). Towards Automatic Persian Spell Checking. SCICT. Kashefi, O., Sharifi, M., & Minaie, B. (2013). A novel string distance metric for ranking Persian respelling suggestions. Natural Language Engineering, 19(2), 259-284. Rasooli, M. S., Kahefi, O., & Minaei-Bidgoli, B. (2011). ... -
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NoCTweak
a Parameterizable Simulator for Early Exploration of Networks On-Chip
...This tool is a cycle-accurate simulator and is open-source using SystemC, a C++ plugin, which is used to quickly model complex systems at a higher level but less details than RTL. NoCTweak was developed by Dr. Anh Tran and Dr. Bevan Baas at UC Davis. NoCTweak has been extended and integrated into McSim, a project developed by Dr. Abdoulaye Gamatié, Dr. Gilles Sassatelli, Dr. Manuel Selva et al. at LIRMM lab. McSim is a simulator for NoC-based many-core platforms, and is a part of the DreamCloud European project. ... -
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SOCDL generates RTL register interfaces and supporting infrastructure for Systems On a Chip from a single-point-of-edit master register description. Template-driven design eases customization.
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ANVIL - (A)(N)other (V)erilog (I)nteraction (L)evel. C++ and VPI/C code to easily instrument RTL/Verilog (dut) and C++ testbench (tb) for more powerful and efficient verification (i.e., C++/tb drives simulator).
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Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.
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LabVIEW/Linux toolkit for accessing unix files (and unix device files) in a Posix conform manner. Is in production use for raw device file and realtime fifo access. LabVIEW Versions [5.1, 6.0, 6.0.1, 6.0.2]. NMT-RTL and RTAI fifos tested.
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Various scripts for several EDA tools such as: RTL Compiler, spyglass, lec, temposync, etc. Scripts are useful in IC design.
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