Search Results for "smartgpu2.h"

GLMixer performs real time graphical blending of several movie clips and of computer generated graphics. Drop video files in the mixing workspace and place them in a circular area to change their opacity ; if you selects two videos, moving them together performs a fading transition. This principle generalizes to a large number of videos. Direct interaction with the video allows to be fast and reactive, and to move and deform them on screen. The output of your operations is shown in the...

Video processing source code for algorithms and tools used in software media pipelines. The currently available source code is written in C++ with their associated libraries and DirectShow Filters. Filters include an H.264 encoder, H.264 decoder, H.264 source filter, RTSP sink and source filters, YUV source, RGB to YUV color conversion, croppers, scalers, video mixing/picture in picture filters, rotate filter, virtual mic, and many more. Code is released under BSD license with exception of H.264 codec related classes which are released under LGPL.

This is an open-source real-time object detection and tracking software for H.264/AVC videos. It applies probabilistic spatiotemporal macroblock filtering (PSMF) and partial decoding processes to effectively detect and track multiple objects with fast computation in H.264|AVC bitstreams with stationary background. The codes were written in Visual C++. For more details, please visit https://www.wonsangyou.com/research/aivision.

zSVC provides an efficient implementation of the Scalable Video Coding extension of H.264. Its aim is a real-time SVC decoder framework on PC platform.

Optimized H.264 baseline codec for PC and TI DSP DM6437.SFIPExe is TI DSP DM6437 based video/audio/command/sensor interface for IP address activities controlling. Information available at: http://www.smallfishdev.com. "SFIPExe" Video availabe in YouTub

The H.264 VHDL core is a hardware implementation of the H.264 video compression algorithm. The core accepts up to the highest resolution HDTV video stream as input and outputs the encoded bitstream. Simple, fully synchronous design with low gate count.

A hardware H.264 video encoder written in VHDL suited to non-interlaced IP cameras and megapixel cameras. Designed to be synthesized into an FPGA or ASIC. Fast and small. Modular. Extensible.