Search Results for "fsm generator"

SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

The goal of this project is to create a simple and easy to use parser generator that will accept a textual grammar file as an input and output modularized classes representing a limited parser interface. Long term goals include a robust grammar file syntax, output suitable for multiple programming languages, and tools for better integrating compiler functionality, parse tree manipulation, and FSM based scanner generation.

A simple, fast, finite state machine (fsm) C code generator using an awk script to read a fsm specification (state, event, action, next state) to produce data for use by included transition function. You provide the fsm spec and the action functions.

NunniFSMGen generates a FSM (Finite State Machine) in Java, C or C++ starting from a transition table. NunniFSMGen cleanly separates logic from implementation by using a modified version of the state pattern, easing the development process!