Search Results for "eda" - Page 10
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Showing 545 open source projects for "eda"
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Power consumption analysis tools for embedded systems. MARTE to AADL model transformation with ATL for tools interoperability. More info on the project at http://sourceforge.net/apps/trac/lab-sticc/
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Gaphor is a UML modeling environment written in Python. Gaphor is small and very extensible. The repository is located at http://github.com/gaphor/gaphor.
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This is a simple viewer for the ``Stream Format'' for CALMA GDSII CAD libraries (``GDS II'', ``.gds'' or ``.sf'') with a couple of limitations. The main functionality is viewing the library layers with different colors.
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Desarrollo y soporte de software para programación de microcontroladores pic. Pic microcontrollers programming software support and development.
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Gnetman is primarily a netlist translator, capable of translating between formats such as VHDL, Verilog, and SPICE. Only structural gate-level netlists are supported. Various netlist manipulations are supported.
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This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee.
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These classes are useful for signal processing in Matlab or C++. They bring together tools and methods which may be used interchangeably for Matlab and C++. Their initial use is in conjunction with work towards my degree at UC Berkeley.
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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format. This project is ported to github and can be found at: https://github.com/chiphackers/covered
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This program provides for easy modification and viewing of SPICE circuit files. It will also read SPICE3 RAW format (as well as GnuCap) and create graphs of results through an interactive GUI. It supports waveform math, copying to clipboard, and saving.
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Projeto para controle da porta paralela em Linux. Este projeto pode ser utilizado como integrador em projetos de robotica ou automação industrial. Funciona na console e permite integração com diversas linguagens como java/php/c++ entre outras.
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O Projeto Cleusa - É uma interface de Gerenciamento de dispositivos. O projeto ROSANA aciona ações nos relês. O projeto Cleusa utiliza uma dispositivo de Hardware especifico, porem pode ser compatibilizado com qualquer outro hardware.
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simple digital logic circuit simulator, using only NAND gates. written as a standalone app for your web browser
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Nocmaker is a tool for the design space exploration tool to help in the design of Network on chips. Noc Maker is based on JHDL.
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IPC 175x Utilities is a collection of software tools to support the IPC 1750 series of supplier declaration standards. These utilities are being developed to help electronics industry supply chain stakeholders implement the IPC 1750 series of standard.
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The Daedalus Design framework is a complete design flow for multi-media embedded Multi-processor System-on-Chip (MPSoC) platforms. It transforms a high level system description into an FPGA prototype in a largely automated way in only a matter of hours.
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Lossi (LOgikSchaltungsSImulator - german for "logic circuit simulator"). It simulates logic circuits. Really.
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ReliaFree is a Python and PyGTK based suite of tools to assist in Reliability, Availability, Maintainability, and Safety (RAMS) analyses. ReliaFree is intended to be an Open Source alternative to proprietary RAMS analyses solutions.
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pyComPic is a GUI (Graphical User Interface) for picprog, sdcc and gpasm written in Python. It uses pyGTK and GTK2 for the interface. It's a good choice if you want to avoid the command line. It works with all PIC programmers supported by picprog
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GEZEL is a cycle-based hardware description language. The GEZEL tools offer stand-alone - and cosimulation, and code-generation into VHDL code. User-defined library-block extensions in C++ allow to add new cosimulation/cosynthesis interfaces.
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vMAGIC is a Java-API which helps creating VHDL generators and analyzers. vMAGIC comprises three parts: 1st a VHDL'93 compliant parser, 2nd a programming model to easily create and modify VHDL constructs, and 3rd a VHDL Writer to generate code.
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Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
