Search Results for "log analysis tools"
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Showing 7 open source projects for "log analysis tools"
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S.M.A.R.T. Monitoring Tools
Disk Inspection and Monitoring
smartmontools contains utility programs (smartctl, smartd) to control/monitor storage systems using the Self-Monitoring, Analysis and Reporting Technology System (S.M.A.R.T.) built into most modern ATA and SCSI disks. It is derived from smartsuite. -
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PC_Workman_HCK
AI-powered PC monitoring that explains. Not shows numbers/spikes.
PC_Workman is what 680 hours of coding after warehouse shifts looks like. Built on a laptop hitting 94°C, this AI-powered monitoring tool does what Task Manager can't: it understands your system, not just measures it. Features: - Time travel monitoring - debug issues from hours ago - AI diagnostics with HCK_GPT - Custom fan curves with profiles - Floating always-on-top widget - 2D system map - Cross-GPU support (NVIDIA/AMD/Intel) Four complete rebuilds. 29 features killed.... -
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An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the...
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VisualCube is a volumetric display out of 6*6*6 voxels, where each voxel get's represented by a 2-color LED. This project includes a bunch of tools used to control this peace of hardware, by taking advantage of the VisualCube library.
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Get and display the traffic counter of a Fritz!Box 7270 (or similar) in a human readable form on local host. The telnet daemon has to be enabled on the FritzBox to download the data file from the AVM router to local host.
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m4-la is a Logic Analyzer written in VHDL for the Xilinx ML403 Development board featuring the Virtex4 FPGA. The user interface is written in C for Windows32 based platforms. Xilinx ISE and EDK tools compile the VHDL and MS Visual Studio compiles the UI.
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FreeSP is an infrastructure for programming platform-independend online signal processing applications. Ports to specific platforms (like DSPs and microcontrollers) are made by simply exchanging the freeSP System-module.
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