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Showing 7 open source projects for "set"
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SmGen
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing -
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You can now find powerpc-utils and powerpc-utils-python on github. https://github.com/nfont/powerpc-utils https://github.com/nfont/powerpc-utils-python The powerpc-utils package provides a set of tools and utilities and utilities for maintaining and enabling certain features of Linux on Power.
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A Perl script that interfaces with the Devantech USB to I2C interface adapter. This script allows a user to read and write as a master to the i2c bus as well as set or get the value of the io pins.
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Linux based client software and a set of AVR microcontroller devices that support the SportIdent electronic punching system used in orienteering. Clients send card data to a PHP/SQL web application, that serves as full featured event software.
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This is a set of small programs and patches to configure the advanced features of some laptops, such as enabling the extra onetouch/multimedia keys, console blanking, battery and temperature reporting, etc. Many HPs and Toshiba Satellites are supported.
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KDE USB Automation - Add USB device notification and automatic set-up of storage devices to KDE & hotplug.
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Maiden-core is a Linux kernel robotics API module, extensible in Erc. The Maiden Project also documents and develops the Maiden architecture for mobile robots, a set of (optional) designs and standards for robots using the Maiden-core API.
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