Showing 2 open source projects for "integer set library"

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    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 4 This Week
    Last Update:
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  • 2
    Maiden-core is a Linux kernel robotics API module, extensible in Erc. The Maiden Project also documents and develops the Maiden architecture for mobile robots, a set of (optional) designs and standards for robots using the Maiden-core API.
    Downloads: 0 This Week
    Last Update:
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